© 2008 Microchip Technology Inc.
DS22103A-page 1
MCP23018/MCP23S18
Features
• 16-bit remote bidirectional I/O port:
- I/O pins default to input
• Open-drain outputs:
- 5.5V tolerant
- 25 mA sink capable (per pin)
- 400 mA total
• High-speed I
2
C™ interface: (MCP23018)
- 100 kHz
- 400 kHz
- 3.4 MHz
• High-speed SPI interface: (MCP23S18)
- 10 MHz: 2.7V
≤ V
DD
≤
5.5V
• Single hardware address pin: (MCP23018)
- Voltage input to allow up to eight devices on
the bus
• Configurable interrupt output pins:
- Configurable as active-high, active-low or
open-drain
• Configurable interrupt source:
- Interrupt-on-change from configured defaults
or pin change
• Polarity inversion register to configure the polarity
of the input port data
• External reset input
• Low standby current:
- 1 µA (-40°C
≤ T
A
≤ +85°C)
- 6 µA (+85°C
≤ T
A
≤ +125°C)
• Operating voltage:
- 1.8V to 5.5V
Packages
28-pin PDIP (300 mil)
28-pin SOIC (300 mil)
24-pin SSOP (MCP23018 only)
24-pin QFN (4x4 [mm])
Block Diagram
GPB7
GPB6
GPB5
GPB4
GPB3
GPB2
GPB1
GPB0
I
2
C
Control
GPIO
SCL
SDA
RESET
INTA
16
Configuration/
8
ADDR
Control
Registers
SPI
SI
SO
SCK
CS
MCP23S18
MCP23018
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
INTB
Interrupt
GPIO
Serializer/
Deserializer
Logic
Multi-bit
Decode
Open-drain
16-Bit I/O Expander with Open-Drain Outputs
MCP23018/MCP23S18
DS22103A-page 2
© 2008 Microchip Technology Inc.
Package Types:
MCP23018
PDIP/SOIC
SSOP
QFN
NC
28
GPA7
27
GPA6
26
GPA5
25
GPA4
24
GPA3
23
GPA2
22
GPA1
21
GPA0
20
INTA
19
INTB
18
NC
17
RESET
16
ADDR
15
V
SS
1
NC
2
GPB0
3
GPB1
4
GPB2
5
GPB3
6
GPB4
7
GPB5
8
GPB6
9
GPB7
10
V
DD
11
SCL
12
SDA
13
NC
14
GPA7
24
GPA6
23
GPA5
22
GPA4
21
GPA3
20
GPA2
19
GPA1
18
GPA0
17
INTA
16
INTB
15
RESET
14
ADDR
13
V
SS
1
GPB0
2
GPB1
3
GPB2
4
GPB3
5
GPB4
6
GPB5
7
GPB6
8
GPB7
9
V
DD
10
SCL
11
SDA
12
GP
A6
21
GP
A7
22
V
SS
23
GP
A5
20
GP
A4
19
GPA3
18
GPA2
17
GPA1
16
GPA0
15
INTA
14
GPB1
1
GPB2
2
GPB3
3
GPB4
4
GPB5
5
V
DD
8
SCL
9
SDA
10
ADDR
11
R
E
SET
12
GP
B0
24
GPB6
6
GPB7
7
INTB
13
EP
25
© 2008 Microchip Technology Inc.
DS22103A-page 3
MCP23018/MCP23S18
Package Types:
MCP23S18
PDIP/SOIC
QFN *
NC
28
GPA7
27
GPA6
26
GPA5
25
GPA4
24
GPA3
23
GPA2
22
GPA1
21
GPA0
20
INTA
19
INTB
18
NC
17
RESET
16
SO
15
V
SS
1
NC
2
GPB0
3
GPB1
4
GPB2
5
GPB3
6
GPB4
7
GPB5
8
GPB6
9
GPB7
10
V
DD
11
CS
12
SCK
13
SI
14
GP
A
6
21
GP
A
7
22
V
SS
23
GP
A
5
20
GP
A
4
19
GPA3
18
GPA2
17
GPA1
16
GPA0
15
INTA *
14
GPB1
1
GPB2
2
GPB3
3
GPB4
4
GPB5
5
V
DD
8
CS
9
SCK
10
SI
11
SO
12
GPB0
24
GPB6
6
GPB7
7
RESET
13
EP
25
* INTB is not bonded out. Can be controlled in
IOCON.MIRROR
MCP23018/MCP23S18
DS22103A-page 4
© 2008 Microchip Technology Inc.
1.0
DEVICE OVERVIEW
The MCP23X18 device provides 16-bit, general pur-
pose parallel I/O expansion for I
2
C bus or SPI
applications. The two devices differ only in the serial
interface.
• MCP23018 - I
2
C interface
• MCP23S18 - SPI interface
The MCP23X18 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits. The data
for each input or output is kept in the corresponding
input or output register. The polarity of the input port
register can be inverted with the polarity inversion
register. All registers can be read by the system master.
The 16-bit I/O port functionally consists of two (2) 8-bit
ports (PORTA and PORTB). The MCP23X18 can be
configured to operate in 8-bit mode or 16-bit mode via
IOCON.BANK.
There are two interrupt pins, INTA and INTB which can
be associated with their respective ports, or can be
logically OR’ed together so both pins will activate if
either port causes an interrupt.
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1.
When any input state differs from its
corresponding input port register state. This is
used to indicate to the system master that an
input state has changed.
2.
When an input state differs from a pre-
configured register value (DEFVAL register).
The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition
that caused the interrupt.
The Power-on Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pin is used to determine the
device address.
© 2008 Microchip Technology Inc.
DS22103A-page 5
MCP23018/MCP23S18
1.1
Pin Descriptions
TABLE 1-1:
I
2
C PINOUT DESCRIPTION (MCP23018)
Pin
Name
28L
PDIP/
SOIC
24L
QFN
24L
SSOP
Pin
Type
Standard Function
GPB0
3
24
2
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPB1
4
1
3
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPB2
5
2
4
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPB3
6
3
5
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPB4
7
4
6
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPB5
8
5
7
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPB6
9
6
8
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPB7
10
7
9
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
V
DD
11
8
10
P
Power
V
SS
1
23
1
P
Ground
SCL
12
9
11
I
Serial clock input
SDA
13
10
12
I/O
Serial data I/O
ADDR
15
11
13
I
Hardware address pin allows up to 8 slave devices on the bus
RESET
16
12
14
I
Hardware reset
INTB
18
13
15
O
Interrupt output for port B. Can be configured as active high, active low, or
open drain.
INTA
19
14
16
O
Interrupt output for port A. Can be configured as active high, active low, or
open drain.
GPA0
20
15
17
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPA1
21
16
18
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPA2
22
17
19
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPA3
23
18
20
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPA4
24
19
21
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPA5
25
20
22
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPA6
26
21
23
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
GPA7
27
22
24
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be
enabled for interrupt on change, and/or internal pull-up resistor.
NC
2, 14,
17, 28
—
—
Not connected
EP
—
25
—
Exposed Thermal Pad (EP). Do not electrically connect, or connect to V
SS
.
MCP23018/MCP23S18
DS22103A-page 6
© 2008 Microchip Technology Inc.
TABLE 1-2:
SPI PINOUT DESCRIPTION (MCP23S18)
Pin
Name
28L
PDIP/
SOIC
24L
QFN
Pin
Type
Standard Function
GPB0
3
24
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPB1
4
1
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPB2
5
2
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPB3
6
3
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPB4
7
4
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPB5
8
5
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPB6
9
6
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPB7
10
7
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
V
DD
11
8
P
Power (high current capable)
V
SS
1
23
P
Ground (high current capable)
CS
12
9
I
Chip select
SCK
13
10
I
Serial clock input
SI
14
11
I
Serial data input
SO
15
12
O
Serial data out
RESET
16
13
I
Hardware reset (must be externally biased)
INTB
18
—
O
Interrupt output for port B. Can be configured as active high, active low, or open
drain.
INTA
19
14
O
Interrupt output for port A. Can be configured as active high, active low, or open
drain.
GPA0
20
15
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPA1
21
16
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPA2
22
17
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPA3
23
18
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPA4
24
19
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPA5
25
20
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPA6
26
21
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GPA7
27
22
I/O
Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
NC
2, 17,
28
—
Not connected
EP
—
25
—
Exposed Thermal Pad (EP). Do not electrically connect, or connect to V
SS
.
© 2008 Microchip Technology Inc.
DS22103A-page 7
MCP23018/MCP23S18
1.2
Power-on Reset (POR)
The on-chip POR circuit holds the device in reset until
V
DD
has reached a high enough voltage to deactivate
the POR circuit (i.e., release the device from reset).
The maximum V
DD
rise time is specified in the
electrical specification section.
When the device exits the POR condition (releases
reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
1.3
Serial Interface
This block handles the functionality of the I
2
C
(MCP23018) or SPI (MCP23S18) interface protocol.
The MCP23X18 contains twenty two (22) individual
registers (eleven [11] register pairs) which can be
addressed through the Serial Interface block (
Table 1-
1
).
TABLE 1-1:
REGISTER ADDRESSES
1.3.1
BYTE MODE AND SEQUENTIAL
MODE
The MCP23X18 has the ability to operate in “Byte
Mode” or “Sequential Mode” (IOCON.SEQOP). Byte
mode and sequential mode are not to be confused with
I
2
C byte operations and sequential operations. The
modes explained here relate to the device’s internal
address pointer and whether or not it is incremented
after each byte is clocked on the serial interface.
Byte Mode disables automatic address pointer incre-
menting. When operating in Byte Mode, the
MCP23X18 does not increment its internal address
counter after each byte during the data transfer. This
gives the ability to continually access the same address
by providing extra clocks (without additional control
bytes). This is useful for polling the GPIO register for
data changes or for continually writing to the output
latches.
A special mode (Byte Mode with IOCON.BANK = 0)
causes the address pointer to toggle between associ-
ated A/B register pairs. For example, if the BANK bit is
cleared and the address pointer is initially set to
address 12h (GPIOA) or 13h (GPIOB), the pointer will
toggle between GPIOA and GPIOB. Note, the address
pointer can initially point to either address in the regis-
ter pair.
Sequential Mode enables automatic address pointer
incrementing. When operating in Sequential Mode, the
MCP23X18 increments its address counter after each
byte during the data transfer. The address pointer auto-
matically rolls over to address 00h after accessing the
last register.
These two modes are not to be confused with single
writes/reads and continuous writes/reads which are
serial protocol sequences. For example, the device
may be configured for Byte Mode and the master may
perform a continuous read. In this case, the
MCP23X18 would not increment the address pointer
and would repeatedly drive data from the same loca-
tion.
1.3.2
I
2
C INTERFACE
1.3.2.1
I
2
C Write Operation
The I
2
C write operation includes the control byte and
register address sequence, as shown in the bottom of
Figure 1-1
. This sequence is followed by eight bits of
data from the master and an Acknowledge (ACK) from
the MCP23018. The operation is ended with a stop (P)
or restart (SR) condition being generated by the mas-
ter.
Data is written to the MCP23018 after every byte trans-
fer. If a stop or restart condition is generated during a
data transfer, the data will not be written to the
MCP23018.
Both “byte mode” and “sequential mode” are supported
by the MCP23018. If sequential mode is enabled
(default), the MCP23018 increments its address
counter after each ACK during the data transfer.
Address
IOCON.BANK = 1
Address
IOCON.BANK = 0
Access to:
00h
00h
IODIRA
10h
01h
IODIRB
01h
02h
IPOLA
11h
03h
IPOLB
02h
04h
GPINTENA
12h
05h
GPINTENB
03h
06h
DEFVALA
13h
07h
DEFVALB
04h
08h
INTCONA
14h
09h
INTCONB
05h
0Ah
IOCON
15h
0Bh
IOCON
06h
0Ch
GPPUA
16h
0Dh
GPPUB
07h
0Eh
INTFA
17h
0Fh
INTFB
08h
10h
INTCAPA
18h
11h
INTCAPB
09h
12h
GPIOA
19h
13h
GPIOB
0Ah
14h
OLATA
1Ah
15h
OLATB
MCP23018/MCP23S18
DS22103A-page 8
© 2008 Microchip Technology Inc.
1.3.2.2
I
2
C Read Operation
I
2
C read operations include the control byte sequence,
as shown in the bottom of
Figure 1-1
. This sequence is
followed by another control byte (including the Start
condition and ACK) with the R/W bit equal to a logic
one (R/W = 1). The MCP23018 then transmits the data
contained in the addressed register. The sequence is
ended with the master generating a Stop or Restart
condition.
1.3.2.3
I
2
C Sequential Write/Read
For sequential operations (Write or Read), instead of
transmitting a Stop or Restart condition after the data
transfer, the master clocks the next byte pointed to by
the address pointer (see Section 1.3.1 “Byte Mode
and Sequential Mode” for details regarding sequential
operation control).
The sequence ends with the master sending a Stop or
Restart condition.
The MCP23018 address pointer will roll over to
address zero after reaching the last register address.
Refer to
Figure 1-1
.
1.3.3
SPI INTERFACE
1.3.3.1
SPI Write Operation
The SPI write operation is started by lowering CS. The
write command (slave address with R/W bit cleared) is
then clocked into the device. The opcode is followed by
an address and at least one data byte.
1.3.3.2
SPI Read Operation
The SPI read operation is started by lowering CS. The
SPI read command (slave address with R/W bit set) is
then clocked into the device. The opcode is followed by
an address, with at least one data byte being clocked
out of the device.
1.3.3.3
SPI Sequential Write/Read
For sequential operations, instead of deselecting the
device by raising CS, the master clocks the next byte
pointed to by the address pointer. (see Section 1.3.1
“Byte Mode and Sequential Mode” for details regard-
ing sequential operation control).
The sequence ends by the raising of CS.
The MCP23S18 address pointer will roll over to
address zero after reaching the last register address.
© 2008 Microchip Technology Inc.
DS22103A-page 9
MCP23018/MCP23S18
FIGURE 1-1:
MCP23018 I
2
C™ DEVICE PROTOCOL
S
P
SR
w
R
OP
ADDR
D
OUT
D
IN
- Start
- Restart
- Stop
- Write
- Read
- Device opcode
- Device address
- Data out from MCP23018
- Data in to MCP23018
S
P
SR
W
R
OP
ADDR
D
IN
D
IN
....
S
P
W
R
OP
ADDR
D
OUT
D
OUT
....
P
SR
W
OP
ADDR
D
IN
....
P
P
SR
R
D
OUT
D
OUT
....
P
OP
D
OUT
D
OUT
....
P
SR
OP
D
IN
....
P
OP
D
IN
S
P
W
OP
ADDR
D
IN
D
IN
....
Byte and Sequential Write
S
W
OP
SR
R
OP
D
OUT
D
OUT
....
P
Byte and Sequential Read
S
W
OP
ADDR
D
IN
P
S
W
OP
SR
R
OP
D
OUT
P
Byte
Sequential
Byte
Sequential
ADDR
ADDR
MCP23018/MCP23S18
DS22103A-page 10
© 2008 Microchip Technology Inc.
1.4
Multi-bit Address Decoder
The ADDR pin is used to set the slave address of the
MCP23018 (I
2
C only) to allow up to eight devices on
the bus using only a single pin. Typically, this would
require three pins.
The multi-bit Address Decoder employs a basic FLASH
ADC architecture (
Figure 1-4
). The seven comparators
generate 8 unique values based on the analog input.
This value is converted to a 3-bit code which corre-
sponds to the address bits (A2, A1, A0) in the serial
OPCODE.
Sequence of Operation (see
Figure 1-5
for
timings):
1.
Upon power up (after V
DD
stabilizes) the module
becomes active after time t
ADEN
. Note, the ana-
log value on the ADDR pin must be stable
before this point to ensure accurate address
assignment.
2.
The 3-bit address is latched after t
ADDRLAT.
3.
The module powers down after the first rising
edge of the serial clock is detected (t
ADDIS
).
Once the address bits are latched, the device will keep
the slave address until a POR or reset condition
occurs.
1.4.1
CALCULATING VOLTAGE ON ADDR
When calculating the required voltage on the ADDR pin
(V2), the set point should be the mid-point of the LSb of
the ADC.
The examples in
Figure 1-2
and
Figure 1-3
show how
to determine the mid point voltage (V2) and the range
of voltages based on a voltage divider circuit. The
maximum tolerance is 20%, however, it is recom-
mended to use 5% tolerance worst case (10% total tol-
erance).
FIGURE 1-2:
VOLTAGE DIVIDER EXAMPLE
R2
A0
A1
A2
V2
R1
V
DD
MCP23018
V
DD
V
SS
V
SS
ADDR