2011 Microchip Technology Inc.
DS22067J-page 1
11AA010/11LC010
11AA080/11LC080
11AA020/11LC020
11AA160/11LC160
11AA040/11LC040
11AA161/11LC161
Features:
• Single I/O, UNI/O
®
Serial Interface Bus
• Low-Power CMOS Technology:
- 1 mA active current, typical
- 1 µA standby current (max.) (I-temp)
• 128 x 8 through 2,048 x 8 Bit Organizations
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kbps Max. Bit Rate – Equivalent to 100 kHz
Clock Frequency
• Self-Timed Write Cycle (including Auto-Erase)
• Page-Write Buffer for up to 16 Bytes
• STATUS Register for Added Control:
- Write enable latch bit
- Write-In-Progress bit
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4,000V
• 3-lead SOT-23 and TO-92 Packages
• 4-lead Chip Scale Package
• 8-lead PDIP, SOIC, MSOP, TDFN Packages
• Pb-Free and RoHS Compliant
• Available Temperature Ranges:
Pin Function Table
Description:
The Microchip Technology Inc. 11AAXXX/11LCXXX
(11XX
*
) devices are a family of 1 Kbit through 16 Kbit
Serial Electrically Erasable PROMs. The devices are
organized in blocks of x8-bit memory and support the
patented** single I/O UNI/O
®
serial bus. By using
Manchester encoding techniques, the clock and data
are combined into a single, serial bit stream (SCIO),
where the clock signal is extracted by the receiver to
correctly decode the timing and value of each bit.
Low-voltage design permits operation down to 1.8V (for
11AAXXX devices), with standby and active currents of
only 1 uA and 1 mA, respectively.
The 11XX family is available in standard packages
including 8-lead PDIP and SOIC, and advanced pack-
aging including 3-lead SOT-23, 3-lead TO-92, 4-lead
Chip Scale, 8-lead TDFN, and 8-lead MSOP.
Package Types (not to scale)
- Industrial (I):
-40°C to
+85°C
- Automotive (E):
-40°C to +125°C
Name
Function
SCIO
Serial Clock, Data Input/Output
V
SS
Ground
V
CC
Supply Voltage
NC
NC
NC
Vss
1
2
3
4
8
7
6
5
V
CC
NC
NC
SCIO
PDIP/SOIC
(P, SN)
NC
NC
NC
V
SS
1
2
3
4
8
7
6
5
V
CC
NC
NC
SCIO
(MS)
TDFN
NC
NC
NC
V
SS
NC
NC
SCIO
5
6
7
8
4
3
2
1
V
CC
(MN)
MSOP
SOT23
2
3
1
SCIO
V
CC
V
SS
(TT)
Vcc
TO-92
SCIO
(TO)
1
2
3
4
V
CC
V
SS
NC
SCIO
(Top down view,
balls not visible
)
Note 1:
Available in I-temp, “AA” only.
Vss
CS (Chip Scale)
(1)
1K-16K UNI/O
®
Serial EEPROM Family Data Sheet
* 11XX
is used in this document as a generic part number for the 11 series devices.
** Microchip’s UNI/O
®
Bus products are covered by some or all of the following patents issued in the U.S.A.: 7,376,020 & 7,788,430.
11XX
DS22067J-page 2
2011 Microchip Technology Inc.
DEVICE SELECTION TABLE
Part Number
Density
(bits)
Organization
V
CC
Range
Page Size
(Bytes)
Temp.
Ranges
Device
Address
Packages
11LC010
1K
128 x 8
2.5-5.5V
16
I,E
0xA0
P, SN, MS, MN, TO, TT
11AA010
1K
128 x 8
1.8-5.5V
16
I
0xA0
P, SN, MS, MN, TO, TT, CS
11LC020
2K
256 x 8
2.5-5.5V
16
I,E
0xA0
P, SN, MS, MN, TO, TT
11AA020
2K
256 x 8
1.8-5.5V
16
I
0xA0
P, SN, MS, MN, TO, TT, CS
11LC040
4K
512 x 8
2.5-5.5V
16
I,E
0xA0
P, SN, MS, MN, TO, TT
11AA040
4K
512 x 8
1.8-5.5V
16
I
0xA0
P, SN, MS, MN, TO, TT, CS
11LC080
8K
1,024 x 8
2.5-5.5V
16
I,E
0xA0
P, SN, MS, MN, TO, TT
11AA080
8K
1,024 x 8
1.8-5.5V
16
I
0xA0
P, SN, MS, MN, TO, TT, CS
11LC160
16K
2,048 x 8
2.5-5.5V
16
I,E
0xA0
P, SN, MS, MN, TO, TT
11AA160
16K
2,048 x 8
1.8-5.5V
16
I
0xA0
P, SN, MS, MN, TO, TT,CS
11LC161
16K
2,048 x 8
2.5-5.5V
16
I, E
0xA1
P, SN, MS, MN, TO, TT
11AA161
16K
2,048 x 8
1.8-5.5V
16
I
0xA1
P, SN, MS, MN, TO, TT, CS
2011 Microchip Technology Inc.
DS22067J-page 3
11XX
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
............................................................................................................................................................................. 6.5V
SCIO w.r.t. V
SS
.....................................................................................................................................-0.6V to V
CC
+1.0V
Storage temperature ................................................................................................................................. -65°C to 150°C
Ambient temperature under bias............................................................................................................... -40°C to 125°C
ESD protection on all pins.......................................................................................................................................... 4 kV
TABLE 1-1:
DC CHARACTERISTICS
† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= 2.5V to 5.5V
T
A
= -40°C to +85°C
V
CC
= 1.8V to 2.5V
T
A
= -20°C to +85°C
Automotive (E):
V
CC
= 2.5V to 5.5V
T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
D1
V
IH
High-level input
voltage
0.7*V
CC
V
CC
+1
V
D2
V
IL
Low-level input
voltage
-0.3
-0.3
0.3*V
CC
0.2*V
CC
V
V
V
CC
2.5V
V
CC
< 2.5V
D3
V
HYS
Hysteresis of Schmitt
Trigger inputs (SCIO)
0.05*Vcc
—
V
V
CC
2.5V (
Note 1
)
D4
V
OH
High-level output
voltage
V
CC
-0.5
V
CC
-0.5
—
—
V
V
I
OH
= -300
A, V
CC
= 5.5V
I
OH
= -200
A, Vcc = 2.5V
D5
V
OL
Low-level output
voltage
—
—
0.4
0.4
V
V
I
O
I = 300
A, V
CC
= 5.5V
I
O
I = 200
A, Vcc = 2.5V
D6
I
O
Output current limit
(Note 2)
—
—
±4
±3
mA
mA
V
CC
= 5.5V (Note 1)
Vcc = 2.5V (Note 1)
D7
I
LI
Input leakage current
(SCIO)
—
±1
A
V
IN
= V
SS
or V
CC
D8
C
INT
Internal Capacitance
(all inputs and
outputs)
—
7
pF
T
A
= 25°C, F
CLK
= 1 MHz,
V
CC
= 5.0V (
Note 1
)
D9
I
CC
Read Read Operating
Current
—
—
3
1
mA
mA
V
CC
=5.5V; F
BUS
=100 kHz, C
B
=100 pF
V
CC
=2.5V; F
BUS
=100 kHz, C
B
=100 pF
D10
I
CC
Write Write Operating
Current
—
—
5
3
mA
mA
V
CC
= 5.5V
V
CC
= 2.5V
D11
Iccs
Standby Current
—
—
5
1
A
A
V
CC
= 5.5V
T
A
= 125°C
V
CC
= 5.5V
T
A
= 85°C
D12
I
CCI
Idle Mode Current
—
50
A
V
CC
= 5.5V
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
The SCIO output driver impedance will vary to ensure I
O
is not exceeded.
11XX
DS22067J-page 4
2011 Microchip Technology Inc.
TABLE 1-3:
AC TEST CONDITIONS
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= 2.5V to 5.5V
T
A
= -40°C to +85°C
V
CC
= 1.8V to 2.5V
T
A
= -20°C to +85°C
Automotive (E):
V
CC
= 2.5V to 5.5V
T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
1
F
BUS
Serial bus frequency
10
100
kHz
—
2
T
E
Bit period
10
100
µs
—
3
T
IJIT
Input edge jitter tolerance
—
±0.06
UI
(Note 3)
4
F
DRIFT
Serial bus frequency drift
rate tolerance
—
±0.50
% per byte —
5
F
DEV
Serial bus frequency drift
limit
—
±5
% per
command
—
6
T
OJIT
Output edge jitter
—
±0.25
UI
(Note 3)
7
T
R
SCIO input rise time
(
Note 1
)
—
100
ns
—
8
T
F
SCIO input fall time
(
Note 1
)
—
100
ns
—
9
T
STBY
Standby pulse time
600
—
µs
—
10
T
SS
Start header setup time
10
—
µs
—
11
T
HDR
Start header low pulse
time
5
—
µs
—
12
T
SP
Input filter spike
suppression (SCIO)
—
50
ns
(
Note 1
)
13
T
WC
Write cycle time
(byte or page)
—
—
5
10
ms
ms
Write, WRSR commands
ERAL, SETAL commands
14
—
Endurance (per page)
1M
—
cycles
25°C, V
CC
= 5.5V (
Note 2
)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance
™
Model which can be obtained on Microchip’s web site:
www.microchip.com.
3:
A Unit Interval (UI) is equal to 1-bit period (T
E
) at the current bus frequency.
AC Waveform:
V
LO
= 0.2V
V
H I
= V
CC
- 0.2V
C
L
= 100 pF
Timing Measurement Reference Level
Input
0.5 V
CC
Output
0.5 V
CC
2011 Microchip Technology Inc.
DS22067J-page 5
11XX
FIGURE 1-1:
BUS TIMING – START HEADER
FIGURE 1-2:
BUS TIMING – DATA
FIGURE 1-3:
BUS TIMING – STANDBY PULSE
FIGURE 1-4:
BUS TIMING – JITTER
SCIO
2
Data ‘0’
Data ‘1’
Data ‘0’
Data ‘1’
Data ‘0’
Data ‘1’
Data ‘0’
Data ‘1’
MAK bit NoSAK bit
11
10
2
SCIO
7
8
Data ‘0’
Data ‘1’
Data ‘1’
Data ‘0’
12
SCIO
9
Standby
Mode
Ideal Edge
3
2
3
6
6
2
6
6
Ideal Edge
Ideal Edge
Ideal Edge
from Master
from Master
from Slave
from Slave
11XX
DS22067J-page 6
2011 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
2.1
Principles of Operation
The 11XX family of serial EEPROMs support the
UNI/O
®
protocol. They can be interfaced with
microcontrollers, including Microchip’s PIC
®
microcon-
trollers, ASICs, or any other device with an available
discrete I/O line that can be configured properly to
match the UNI/O protocol.
The 11XX devices contain an 8-bit instruction register.
The devices are accessed via the SCIO pin.
Table 4-1
contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSb first, LSb
last.
Data is embedded into the I/O stream through
Manchester encoding. The bus is controlled by a
master device which determines the clock period, con-
trols the bus access and initiates all operations, while
the 11XX works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is active.
FIGURE 2-1:
BLOCK DIAGRAM
SCIO
STATUS
Register
I/O Control
Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
Vcc
Vss
Current-
Limited
Slope
Control
2011 Microchip Technology Inc.
DS22067J-page 7
11XX
3.0
BUS CHARACTERISTICS
3.1
Standby Pulse
When the master has control of SCIO, a standby pulse
can be generated by holding SCIO high for T
STBY
. At
this time, the 11XX will reset and return to Standby
mode. Subsequently, a high-to-low transition on SCIO
(the first low pulse of the header) will return the device
to the active state.
Once a command is terminated satisfactorily (i.e., via
a NoMAK/SAK combination during the Acknowledge
sequence), performing a standby pulse is not required
to begin a new command as long as the device to be
selected is the same device selected during the previ-
ous command. However, a period of T
SS
must be
observed after the end of the command and before the
beginning of the start header. After T
SS
, the start
header (including T
HDR
low pulse) can be transmitted
in order to begin the new command.
If a command is terminated in any manner other than a
NoMAK/SAK combination, then the master must per-
form a standby pulse before beginning a new com-
mand, regardless of which device is to be selected.
An example of two consecutive commands is shown in
Figure 3-1
. Note that the device address is the same
for both commands, indicating that the same device is
being selected both times.
A standby pulse cannot be generated while the slave
has control of SCIO. In this situation, the master must
wait for the slave to finish transmitting and to release
SCIO before the pulse can be generated.
If, at any point during a command, an error is detected
by the master, a standby pulse should be generated
and the command should be performed again.
FIGURE 3-1:
CONSECUTIVE COMMANDS EXAMPLE
3.2
Start Data Transfer
All operations must be preceded by a start header. The
start header consists of holding SCIO low for a period
of T
HDR
, followed by transmitting an 8-bit ‘
01010101
’
code. This code is used to synchronize the slave’s
internal clock period with the master’s clock period, so
accurate timing is very important.
When a standby pulse is not required (i.e., between
successive commands to the same device), a period of
T
SS
must be observed after the end of the command
and before the beginning of the start header.
Figure 3-2
shows the waveform for the start header,
including the required Acknowledge sequence at the
end of the byte.
FIGURE 3-2:
START HEADER
Note: After a POR/BOR event occurs, a low-
to-high transition on SCIO must be gen-
erated before proceeding with commu-
nication, including a standby pulse.
1
1
0
1
0
1
0
0
Start Header
SCIO
Device Address
MA
K
0
0
0
0
1
0
1
0
MA
K
No
SAK
SAK
Standby Pulse
(1)
1
1
0
1
0
1
0
0
Start Header
SCIO
Device Address
MA
K
0
0
0
0
1
0
1
0
MA
K
No
S
A
K
SAK
No
MAK
SAK
T
SS
Note 1: After a POR/BOR event, a low-to-high transition on SCIO is required to occur before the first
standby pulse.
SCIO
Data ‘0’
Data ‘1’
Data ‘0’
Data ‘1’
Data ‘0’
Data ‘1’
Data ‘0’
Data ‘1’
MAK
NoSAK
T
SS
T
HDR
11XX
DS22067J-page 8
2011 Microchip Technology Inc.
3.3
Acknowledge
An Acknowledge routine occurs after each byte is
transmitted, including the start header. This routine
consists of two bits. The first bit is transmitted by the
master, and the second bit is transmitted by the slave.
The Master Acknowledge, or MAK, is signified by trans-
mitting a ‘
1
’, and informs the slave that the current
operation is to be continued. Conversely, a Not
Acknowledge, or NoMAK, is signified by transmitting a
‘0’, and is used to end the current operation (and initiate
the write cycle for write operations).
The slave Acknowledge, or SAK, is also signified by
transmitting a ‘
1
’, and confirms proper communication.
However, unlike the NoMAK, the NoSAK is signified by
the lack of a middle edge during the bit period.
A NoSAK will occur for the following events:
• Following the start header
• Following the device address, if no slave on the
bus matches the transmitted address
• Following the command byte, if the command is
invalid, including Read, CRRD, Write, WRSR,
SETAL, and ERAL during a write cycle.
• If the slave becomes out of sync with the master
• If a command is terminated prematurely by using
a NoMAK, with the exception of immediately after
the device address.
See
Figure 3.3
and
Figure 3-4
for details.
If a NoSAK is received from the slave after any byte
(except the start header), an error has occurred. The
master should then perform a standby pulse and begin
the desired command again.
FIGURE 3-3:
ACKNOWLEDGE
ROUTINE
FIGURE 3-4:
ACKNOWLEDGE BITS
3.4
Device Addressing
A device address byte is the first byte received from the
master device following the start header. The device
address byte consists of a four-bit family code, for the
11XX this is set as ‘
1010
’. The last four bits of the
device address byte are the device code, which is
hardwired to ‘
0000
’ on the 11XXXX0 devices.
The device code on 11XXXX1 devices is hardwired to
‘0001’. This allows both 11XXXX0 and 11XXXX1
devices to be used on the same bus without address
conflicts.
FIGURE 3-5:
DEVICE ADDRESS BYTE
ALLOCATION
3.5
Bus Conflict Protection
To help guard against high current conditions arising
from bus conflicts, the 11XX features a current-limited
output driver. The I
OL
and I
OH
specifications describe
the maximum current that can be sunk or sourced,
respectively, by the SCIO pin. The 11XX will vary the
output driver impedance to ensure that the maximum
current level is not exceeded.
Note: A MAK must always be transmitted
following the start header.
Note: When a NoMAK is used to end a
WRITE
or
WRSR
instruction, the write
cycle is not initiated if no bytes of data
have been received.
Note: In order to guard against bus conten-
tion, a NoSAK will occur after the start
header.
Master
Slave
MAK
SAK
MAK (‘1’)
NoMAK (‘0’)
SAK (‘1’)
NoSAK
(1)
Note 1:
valid SAK.
A NoSAK is defined as any sequence that is not a
1
0
1
0
0
0
0
MAK
SLAVE ADDRESS
0
(1)
SAK
Note 1:
This bit is a ‘1’ on the 11XXXX1.
2011 Microchip Technology Inc.
DS22067J-page 9
11XX
3.6
Device Standby
The 11XX features a low-power Standby mode during
which the device is waiting to begin a new command.
A high-to-low transition on SCIO will exit low-power
mode and prepare the device for receiving the start
header.
Standby mode will be entered upon the following
conditions:
• A NoMAK followed by a SAK (i.e., valid termina-
tion of a command)
• Reception of a standby pulse
3.7
Device Idle
The 11XX features an Idle mode during which all serial
data is ignored until a standby pulse occurs. Idle mode
will be entered upon the following conditions:
• Invalid device address
• Invalid command byte, including Read, CRRD,
Write, WRSR, SETAL and ERAL during a write
cycle.
• Missed edge transition
• Reception of a MAK following a
WREN
,
WRDI
,
SETAL
, or
ERAL
command byte
• Reception of a MAK following the data byte of a
WRSR
command
An invalid start header will indirectly cause the device
to enter Idle mode. Whether or not the start header is
invalid cannot be detected by the slave, but will
prevent the slave from synchronizing properly with the
master. If the slave is not synchronized with the
master, an edge transition will be missed, thus causing
the device to enter Idle mode.
3.8
Synchronization
At the beginning of every command, the 11XX utilizes
the start header to determine the master’s bus clock
period. This period is then used as a reference for all
subsequent communication within that command.
The 11XX features re-synchronization circuitry which
will monitor the position of the middle data edge during
each MAK bit and subsequently adjust the internal time
reference in order to remain synchronized with the
master.
There are two variables which can cause the 11XX to
lose synchronization. The first is frequency drift,
defined as a change in the bit period, T
E
. The second is
edge jitter, which is a single occurrence change in the
position of an edge within a bit period, while the bit
period itself remains constant.
3.8.1
FREQUENCY DRIFT
Within a system, there is a possibility that frequencies
can drift due to changes in voltage, temperature, etc.
The re-synchronization circuitry provides some toler-
ance for such frequency drift. The tolerance range is
specified by two parameters, F
DRIFT
and F
DEV
. F
DRIFT
specifies the maximum tolerable change in bus fre-
quency per byte. F
DEV
specifies the overall limit in fre-
quency deviation within an operation (i.e., from the end
of the start header until communication is terminated
for that operation). The start header at the beginning of
the next operation will reset the re-synchronization cir-
cuitry and allow for another F
DEV
amount of frequency
drift.
3.8.2
EDGE JITTER
Ensuring that edge transitions from the master always
occur exactly in the middle or end of the bit period is not
always possible. Therefore, the re-synchronization cir-
cuitry is designed to provide some tolerance for edge
jitter.
The 11XX adjusts its phase every MAK bit, so T
IJIT
specifies the maximum allowable peak-to-peak jitter
relative to the previous MAK bit. Since the position of
the previous MAK bit would be difficult to measure by
the master, the minimum and maximum jitter values for
a system should be considered the worst-case. These
values will be based on the execution time for different
branch paths in software, jitter due to thermal noise,
etc.
The difference between the minimum and maximum
values, as a percentage of the bit period, should be cal-
culated and then compared against T
IJIT
to determine
jitter compliance.
Note: In the case of the
WRITE
,
WRSR
,
SETAL
,
or
ERAL
commands, the write cycle is initi-
ated upon receipt of the NoMAK, assuming
all other write requirements have been met.
Note: Because the 11XX only re-synchronizes
during the MAK bit, the overall ability to
remain synchronized depends on a combi-
nation of frequency drift and edge jitter (i.e.,
if the MAK bit edge is experiencing the max-
imum allowable edge jitter, then there is no
room for frequency drift). Conversely, if the
frequency has drifted to the maximum
amount tolerable within a byte, then no
edge jitter can be present.
11XX
DS22067J-page 10
2011 Microchip Technology Inc.
4.0
DEVICE COMMANDS
After the device address byte, a command byte must
be sent by the master to indicate the type of operation
to be performed. The code for each instruction is listed
in
Table 4-1
.
TABLE 4-1:
INSTRUCTION SET
4.1
Read Instruction
The Read command allows the master to access any
memory location in a random manner. After the
READ
instruction has been sent to the slave, the two bytes of
the Word Address are transmitted, with an Acknowl-
edge sequence being performed after each byte. Then,
the slave sends the first data byte to the master. If more
data is to be read, the master sends a MAK, indicating
that the slave should output the next data byte. This
continues until the master sends a NoMAK, which ends
the operation.
To provide sequential reads in this manner, the 11XX
contains an internal Address Pointer which is incre-
mented by one after the transmission of each byte. This
Address Pointer allows the entire memory contents to
be serially read during one operation. When the highest
address is reached, the Address Pointer rolls over to
address ‘0x000’ if the master chooses to continue the
operation by providing a MAK.
FIGURE 4-1:
READ COMMAND SEQUENCE
Instruction Name
Instruction Code
Hex Code
Description
READ
0000 0011
0x03
Read data from memory array beginning at specified address
CRRD
0000 0110
0x06
Read data from current location in memory array
WRITE
0110 1100
0x6C
Write data to memory array beginning at specified address
WREN
1001 0110
0x96
Set the write enable latch (enable write operations)
WRDI
1001 0001
0x91
Reset the write enable latch (disable write operations)
RDSR
0000 0101
0x05
Read STATUS register
WRSR
0110 1110
0x6E
Write STATUS register
ERAL
0110 1101
0x6D
Write ‘
0x00
’ to entire array
SETAL
0110 0111
0x67
Write ‘
0xFF
’ to entire array
7 6 5 4
Data Byte 1
3 2 1 0
7 6 5 4
Data Byte 2
3 2 1 0
7 6 5 4
Data Byte n
3 2 1 0
SCIO
MA
K
MA
K
No
MAK
1
1
0
1
0
1
0
0
Start Header
SCIO
Device Address
MA
K
0
0
(1)
0
0
1
0
1
0
MA
K
Command
0
1
0
0
0
0
0
1
MA
K
No
SAK
SAK
Standby Pulse
SCIO
SAK
15 14 13 12
Word Address MSB
11 10 9 8
MA
K
SAK
7 6 5 4
Word Address LSB
3 2 1 0
MA
K
SAK
SAK
SAK
SAK
Note 1: For the 11XXXX1, this bit must be a ‘1’.