2016 Microchip Technology Inc.
DS00002275A-page 1
Features
• Single-Chip 10BASE-T/100BASE-TX IEEE 802.3
Compliant Ethernet Transceiver
• MII Interface Support (KSZ8091MNX)
• RMII v1.2 interface support with a 50 MHz refer-
ence clock output to MAC, and an option to input
a 50 MHz reference clock (KSZ8091RNB)
• Back-to-Back Mode Support for a 100 Mbps Cop-
per Repeater
• MDC/MDIO Management Interface for PHY Reg-
ister Configuration
• Programmable Interrupt Output
• LED Outputs for Link and Activity Status Indica-
tion, plus speed indication for KSZ8091RNB
• On-Chip Termination Resistors for the Differential
Pairs
• Baseline Wander Correction
• HP Auto MDI/MDI-X to Reliably Detect and Cor-
rect Straight-Through and Crossover Cable Con-
nections with Disable and Enable Option
• Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100 Mbps) and
Duplex (Half/Full)
• Energy Efficient Ethernet (EEE) Support with
Low-Power Idle (LPI) Mode and Clock Stoppage
(MII Version Only) for 100BASE-TX and Transmit
Amplitude Reduction with 10BASE-Te Option
• Wake-on-LAN (WOL) Support with Either Magic
Packet, Link Status Change, or Robust Custom-
Packet Detection
• HBM ESD Rating (6 kV)
• Power-Down and Power-Saving Modes
• LinkMD
®
TDR-Based Cable Diagnostics to Iden-
tify Faulty Copper Cabling
• Parametric NAND Tree Support for Fault Detec-
tion Between Chip I/Os and the Board
• Loopback Modes for Diagnostics
• Single 3.3V Power Supply with V
DD
I/O Options
for 1.8V, 2.5V, or 3.3V
• Built-In 1.2V Regulator for Core
• Available in 32-pin 5 mm x 5 mm QFN Package
Target Applications
• Game Consoles
• IP Phones
• IP Set-Top Boxes
• IP TVs
• LOM
• Printers
KSZ8091MNX/RNB
10BASE-T/100BASE-TX
Physical Layer Transceiver
KSZ8091MNX/RNB
DS00002275A-page 2
2016 Microchip Technology Inc.
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2016 Microchip Technology Inc.
DS00002275A-page 3
KSZ8091MNX/RNB
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 5
3.0 Functional Description .................................................................................................................................................................. 15
4.0 Register Descriptions .................................................................................................................................................................... 40
5.0 Operational Characteristics ........................................................................................................................................................... 57
6.0 Electrical Characteristics ............................................................................................................................................................... 58
7.0 Timing Diagrams ........................................................................................................................................................................... 60
8.0 Reset Circuit ................................................................................................................................................................................. 69
9.0 Reference Circuits — LED Strap-In Pins ...................................................................................................................................... 70
10.0 Reference Clock - Connection and Selection ............................................................................................................................. 71
11.0 Magnetic - Connection and Selection ......................................................................................................................................... 72
12.0 Package Outline .......................................................................................................................................................................... 74
Appendix A: Data Sheet Revision History ........................................................................................................................................... 75
The Microchip Web Site ...................................................................................................................................................................... 76
Customer Change Notification Service ............................................................................................................................................... 76
Customer Support ............................................................................................................................................................................... 76
Product Identification System ............................................................................................................................................................. 77
KSZ8091MNX/RNB
DS00002275A-page 4
2016 Microchip Technology Inc.
1.0
INTRODUCTION
1.1
General Description
The KSZ8091 is a single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for transmission and
reception of data over standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ8091 is a highly integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip
termination resistors for the differential pairs, by integrating a low-noise regulator to supply the 1.2V core, and by offering
a flexible 1.8/2.5/3.3V digital I/O interface.
The KSZ8091MNX offers the Media Independent Interface (MII) and the KSZ8091RNB offers the Reduced Media Inde-
pendent Interface (RMII) for direct connection with MII/RMII-compliant Ethernet MAC processors and switches.
Energy Efficient Ethernet (EEE) provides further power saving during idle traffic periods and Wake-on-LAN (WOL) pro-
vides a mechanism for the KSZ8091 to wake up a system that is in standby power mode.
The KSZ8091 provides diagnostic features to facilitate system bring-up and debugging in production testing and in prod-
uct deployment. Parametric NAND tree support enables fault detection between KSZ8091 I/Os and the board. LinkMD
®
TDR-based cable diagnostics identify faulty copper cabling.
The KSZ8091MNX and KSZ8091RNB are available in 32-pin, lead-free QFN packages.
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
KSZ8091MNX/
KSZ8091RNB
MAGNETICS
RJ-45
CONNECTOR
MEDIA TYPES:
10BASE-T
100BASE-TX
ON-CHIP TERMINATION
RESISTORS
MII/RMII
MDC/ MDIO
MANAGEMENT
XO
XI
25MHz
XTAL
22pF
22pF
10/100Mbps
MII/RMII MAC
50MHz
(KSZ8091RNB)
REF_CLK
PME_N
(SYSTEM
POWER
CIRCUIT)
2016 Microchip Technology Inc.
DS00002275A-page 5
KSZ8091MNX/RNB
2.0
PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
32-PIN 5 MM X 5 MM QFN ASSIGNMENT, KSZ8091MNX (TOP VIEW)
TABLE 2-1:
SIGNALS - KSZ8091MNX
Pin
Number
Pin
Name
Type
Note
2-1
Description
1
GND
GND
Ground.
2
VDD_1.2
P
1.2V core V
DD
(power supplied by KSZ8091MNX)
Decouple with 2.2 µF and 0.1 µF capacitors to ground.
3
VDDA_3.3
P
3.3V analog V
DD
4
RXM
I/O
Physical receive or transmit signal (– differential)
5
RXP
I/O
Physical receive or transmit signal (+ differential)
GND
VDD_1.2
VDDA_3.3
RXM
RXP
TXM
TXP
XO
RXD3/PHY
AD0
MDC
MDIO
REXT
XI
RXD2/PHY
AD1
RXD1/PHY
AD2
RXD0/DUPLEX
1
2
3
4
5
6
7
8
9
10
11 12 13 14
15
16
24
23
22
21
20
19
18
17
32 31 30 29 28 27
26
25
TXD0
TXEN
TXC/PME_EN
INTRP/PME_N2/NAND_TREE#
RXER/ISO
RXC/B-CAST_OFF
RXDV/CONFIG2
VDDIO
COL/CONFIG0
CRS/CONFIG1
LED0/PME_N1/NW
A
YEN
TXER
RST#
TXD3
TXD2
TXD1
PADDLE
GROUND
(ON BOTTOM OF CHIP)
KSZ8091MNX/RNB
DS00002275A-page 6
2016 Microchip Technology Inc.
6
TXM
I/O
Physical transmit or receive signal (– differential)
7
TXP
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback for 25 MHz crystal
This pin is a no connect if an oscillator or external clock source is used.
9
XI
I
Crystal/Oscillator/External Clock input
25 MHz ±50 ppm
10
REXT
I
Set PHY transmit output current
Connect a 6.49 kΩ resistor to ground on this pin.
11
MDIO
Ipu/
Opu
Management Interface (MII) Data I/O
This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ
pull-up resistor.
12
MDC
Ipu
Management Interface (MII) Clock input
This clock pin is synchronous to the MDIO data pin.
13
RXD3/
PHYAD0
Ipu/O
MII mode: MII Receive Data Output[3] (
Note 2-2
)
Config mode: The pull-up/pull-down value is latched as PHYADDR[0] at the
de assertion of reset.
See the
Strap-In Options - KSZ8091MNX
section for details.
14
RXD2/
PHYAD1
Ipd/O
MII mode: MII Receive Data Output[2] (
Note 2-2
)
Config mode: The pull-up/pull-down value is latched as PHYADDR[1] at the
deassertion of reset.
See the
Strap-In Options - KSZ8091MNX
section for details.
15
RXD1/
PHYAD2
Ipd/O
MII mode: MII Receive Data Output[1] (
Note 2-2
)
Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the
de assertion of reset.
See the
Strap-In Options - KSZ8091MNX
section for details.
16
RXD0/
DUPLEX
Ipu/O
MII mode: MII Receive Data Output[0] (
Note 2-2
)
Config mode: The pull-up/pull-down value is latched as DUPLEX at the de-
assertion of reset.
See the
Strap-In Options - KSZ8091MNX
section for details.
17
VDDIO
P
3.3V, 2.5V, or 1.8V digital V
DD
18
RXDV/
CONFIG2
Ipd/O
MII mode: MII Receive Data Valid output
Config mode: The pull-up/pull-down value is latched as CONFIG2 at the de-
assertion of reset.
See the
Strap-In Options - KSZ8091MNX
section for details.
19
RXC/
B-CAST_OFF
Ipd/O
MII mode: MII Receive Clock output
Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the
de assertion of reset.
See the
Strap-In Options - KSZ8091MNX
section for details.
20
RXER/ISO
Ipd/O
MII mode: MII Receive Error output
Config mode: The pull-up/pull-down value is latched as ISOLATE at the de-
assertion of reset.
See the
Strap-In Options - KSZ8091MNX
section for details.
TABLE 2-1:
SIGNALS - KSZ8091MNX (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
Description
2016 Microchip Technology Inc.
DS00002275A-page 7
KSZ8091MNX/RNB
21
INTRP/
PME_N2/
NAND_Tree#
Ipu/
Opu
Interrupt output: Programmable interrupt output, with Register 1Bh as the
Interrupt Control/Status register, for programming the interrupt conditions and
reading the interrupt status. Register 1Fh, bit [9] sets the interrupt output to
active low (default) or active high.
PME_N output: Programmable PME_N output (pin option 2). When asserted
low, this pin signals that a WOL event has occurred.
Config mode: The pull-up/pull-down value is latched as NAND Tree# at the
deassertion of reset.
See the
Strap-In Options - KSZ8091MNX
section for details.
This pin has a weak pull-up and is an open-drain.
For Interrupt (when active low) and PME functions, this pin requires an exter-
nal 1.0 kΩ pull-up resistor to V
DDIO
(digital V
DD
).
22
TXC/
PME_EN
Ipd/O
MII mode: MII Transmit Clock output
MII back-to-back mode: No connection
Config mode: The pull-up/pull-down value is latched as PME_EN at the de-
assertion of reset.
See the
Strap-In Options - KSZ8091MNX
section for details.
23
TXEN
I
MII mode: MII Transmit Enable input
24
TXD0
I
MII mode: MII Transmit Data Input[0] (
Note 2-3
)
25
TXD1
I
MII mode: MII Transmit Data Input[1] (
Note 2-3
)
26
TXD2
I
MII mode: MII Transmit Data Input[2] (
Note 2-3
)
27
TXD3
I
MII Mode: MII Transmit Data Input[3] (
Note 2-3
)
28
COL/
CONFIG0
Ipd/O
MII mode: MII Collision Detect output
Config mode: The pull-up/pull-down value is latched as CONFIG0 at the de-
assertion of reset.
See the
Strap-In Options - KSZ8091MNX
section for details.
29
CRS/
CONFIG1
Ipd/O
MII mode: MII Carrier Sense output
Config mode: The pull-up/pull-down value is latched as CONFIG1 at the de-
assertion of reset.
See the
Strap-In Options - KSZ8091MNX
section for details.
TABLE 2-1:
SIGNALS - KSZ8091MNX (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
Description
KSZ8091MNX/RNB
DS00002275A-page 8
2016 Microchip Technology Inc.
Note 2-1
P = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Ipu = Input with internal pull-up (see
Electrical Characteristics
for value).
Ipd = Input with internal pull-down (see
Electrical Characteristics
for value).
Ipu/O = Input with internal pull-up (see
Electrical Characteristics
for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see
Electrical Characteristics
for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see
Electrical Characteristics
for value) and output with internal
pull-up (see
Electrical Characteristics
for value).
Note 2-2
MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0]
presents valid data to the MAC.
30
LED0/
PME_N1/
NWAYEN
Ipu/O
LED output: Programmable LED0 output
PME_N Output: Programmable PME_N Output (pin option 1)
In this mode, this pin has a weak pull-up, is an open-drain, and requires an
external 1.0 kΩ pull-up resistor to V
DDIO
(digital V
DD
).
Config mode: Latched as auto-negotiation enable (Register 0h, bit [12]) at the
de-assertion of reset.
See the
Strap-In Options - KSZ8091MNX
section for details.
The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined
as follows.
LED Mode = [00]
Link/Activity
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
Activity
Toggle
Blinking
LED Mode = [01]
Link
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
LED Mode = [10], [11]: Reserved
31
TXER
Ipd
MII mode: MII Transmit Error input
For EEE mode, this pin is driven by the EEEMAC to pull up this pin for
KSZ8091MNX transmit into the LPI state.
For non-EEE mode, this pin is not defined for error transmission from MAC to
KSZ8091MNX and can be left as a no connect.
For NAND Tree testing, this pin should be pulled high by a pull-up resistor.
32
RST#
Ipu
Chip reset (active low)
PADDLE
GND
GND
Ground
TABLE 2-1:
SIGNALS - KSZ8091MNX (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
Description
2016 Microchip Technology Inc.
DS00002275A-page 9
KSZ8091MNX/RNB
Note 2-3
MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0]
presents valid data from the MAC.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7 kΩ) or pull-downs (1.0 kΩ) should be added on these
PHY strap-in pins to ensure that the intended values are strapped-in correctly.
Note 2-4
Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up and output with internal pull-up.
TABLE 2-2:
STRAP-IN OPTIONS - KSZ8091MNX
Pin Number
Pin Name
Type
Note 2-4
Description
15
PHYAD2
Ipd/O
PHYAD[2:0] is latched at de-assertion of reset and is configurable to
any value from 0 to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY
address, but it can be assigned as a unique PHY address after pull-
ing the B-CAST_OFF strapping pin high or writing a ‘1’ to Register
16h, bit [9].
PHY Address bits [4:3] are set to 00 by default.
14
PHYAD1
Ipd/O
13
PHYAD0
Ipu/O
18
CONFIG2
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of
reset.
29
CONFIG1
CONFIG[2:0] Mode
000
MII (default)
28
CONFIG0
110
MII back-to-back
001 – 101,
111
Reserved, not used
22
PME_EN
Ipd/O
PME output for Wake-on-LAN
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register
16h, bit [15].
20
ISO
Ipd/O
Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h,
bit [10].
16
DUPLEX
Ipu/O
Duplex Mode:
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [8].
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable:
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [12].
19
B-CAST_OFF
Ipd/O
Broadcast Off – for PHY Address 0:
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY
address
At the de-assertion of reset, this pin value is latched by the chip.
21
NAND_Tree#
Ipu/Opu
NAND Tree Mode:
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
KSZ8091MNX/RNB
DS00002275A-page 10
2016 Microchip Technology Inc.
FIGURE 2-2:
32-PIN 5 MM X 5 MM QFN ASSIGNMENT, KSZ8091RNB (TOP VIEW)
TABLE 2-3:
SIGNALS - KSZ8091RNB
Pin
Number
Pin Name
Type
Note 2-1
Description
1
GND
GND
Ground.
2
VDD_1.2
P
1.2V core V
DD
(power supplied by KSZ8091RNB)
Decouple with 2.2 µF and 0.1 µF capacitors to ground.
3
VDDA_3.3
P
3.3V analog V
DD
4
RXM
I/O
Physical receive or transmit signal (– differential)
5
RXP
I/O
Physical receive or transmit signal (+ differential)
6
TXM
I/O
Physical transmit or receive signal (– differential)
7
TXP
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback for 25 MHz crystal
This pin is a no connect if an oscillator or external clock source is used.
GND
VDD_1.2
VDDA_3.3
RXM
RXP
TXM
TXP
XO
PHY
AD0
MDC
MDIO
REXT
XI
PHY
AD1
RXD1/PHY
AD2
RXD0/DUPLEX
1
2
3
4
5
6
7
8
9
10
11 12 13 14
15
16
24
23
22
21
20
19
18
17
32 31 30 29 28 27
26
25
TXD0
TXEN
PME_EN
INTRP/PME_N2/NAND_TREE#
RXER/ISO
REF_CLK/B-CAST_OFF
CRS_DV/CONFIG2
VDDIO
CONFIG0
CONFIG1
LED0/PME_N1/NW
A
YEN
LED1/SPEED
RST#
NC
NC
TXD1
PADDLE
GROUND
(ON BOTTOM OF CHIP)