IRLIB9343PbF
1
2017-04-27
Absolute Maximum Ratings
Symbol Parameter
Max.
Units
V
DS
Drain-to-Source
Voltage
-55
V
V
GS
Gate-to-Source Voltage
± 20
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ -10V
-14
A
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ -10V
-10
I
DM
Pulsed Drain Current -60
P
D
@T
C
= 25°C
Maximum Power Dissipation
33
W
P
D
@T
C
= 100°C
Maximum Power Dissipation
20
Linear Derating Factor
0.26
W/°C
T
J
Operating Junction and
-40 to + 175
T
STG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds (1.6mm from case)
300
Mounting torque, 6-32 or M3 screw
10lbin (1.1Nm)
Thermal Resistance
Symbol Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case –––
3.84
R
JA
Junction-to-Ambient (PCB Mount) –––
65
°C/W
G D S
Gate Drain
Source
HEXFET
®
Power MOSFET
TO-220 Full-Pak
G
D
S
Key Parameters
V
DS
-55
V
R
DS(ON)
typ. @ V
GS
=-10V
93
m
R
DS(ON)
typ. @ V
GS
= -4.5V
150
m
Q
g
typ.
31
nC
T
J
max
175
°C
Features
Advanced Process Technology
Key Parameters Optimized for Class-D Audio Amplifier
Applications
Low
R
DSON
for Improved Efficiency
Low
Q
G
and Q
sw
for Better THD and Improved Efficiency
Low
Q
rr
for Better THD and Lower EMI
175°C Operating Junction Temperature for Ruggedness
Repetitive Avalanche Capability for Robustness and
Reliability
Lead-Free
Description
This Digital Audio HEXFET
®
is specifically designed for Class-D audio amplifier applications. This MosFET utilizes the
latest processing techniques to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode
reverse recovery and internal Gate resistance are optimized to improve key Class-D audio amplifier performance factors
such as efficiency, THD and EMI. Additional features of this MosFET are 175°C operating junction temperature and
repetitive avalanche capability. These features combine to make this MosFET a highly efficient, robust and reliable
device for Class-D audio amplifier applications.
Base Part Number
Package Type
Standard Pack
Orderable Part Number
Form Quantity
IRLIB9343PbF
TO-220 Full-Pak
Tube
50 IRLIB9343PbF
IRLIB9343PbF
2
2017-04-27
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
starting T
J
= 25°C, L = 3.89mH, R
G
= 25
, I
AS
= -10A.
Pulse width
400µs; duty cycle 2%.
R
θ
is measured at T
J
of approximately 90°C.
Limited by T
jmax
. See Figs. 14, 15, 17a, 17b for repetitive avalanche information
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter Min.
Typ.
Max.
Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
-55
–––
–––
V
V
GS
= 0V, I
D
= -250µA
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
–––
-52
––– mV/°C Reference to 25°C, I
D
= -1mA
R
DS(on)
Static Drain-to-Source On-Resistance
––– 93 105
m
V
GS
= -10V, I
D
= -3.4A
150
170
V
GS
= -4.5V, I
D
= -2.7A
V
GS(th)
Gate Threshold Voltage
-1.0
–––
–––
V
V
DS
= V
GS
, I
D
= -250µA
V
GS(th)/
T
J
Gate Threshold Voltage Temp. Coefficient –––
-3.7
––– mV/°C
I
DSS
Drain-to-Source Leakage Current
––– ––– -2.0
µA
V
DS
= -55V, V
GS
= 0V
––– ––– -25
V
DS
= -55V,V
GS
= 0V,T
J
=125°C
I
GSS
Gate-to-Source Forward Leakage
–––
––– -100
nA
V
GS
= -20V
Gate-to-Source Reverse Leakage
–––
–––
100
V
GS
= 20V
gfs
Forward Trans conductance
5.3
–––
–––
S
V
DS
= -25V, I
D
= -14A
Q
g
Total Gate Charge
–––
31
47
nC
V
DS
= -44V
Q
gs
Pre-Vth Gate-to-Source Charge
–––
7.1
–––
I
D
= -14A,
Q
gd
Gate-to-Drain Charge
–––
8.5
–––
V
GS
= -10V
Q
godr
Gate Charge Overdrive
–––
15
–––
See Fig. 6 and 19.
t
d(on)
Turn-On Delay Time
–––
9.5
–––
ns
V
DD
= -28V, V
GS
= -10V
t
r
Rise Time
–––
24
–––
I
D
= -14A
t
d(off)
Turn-Off Delay Time
–––
21
–––
R
G
= 2.5
t
f
Fall Time
–––
9.5
–––
C
iss
Input Capacitance
–––
660
–––
pF
V
GS
= 0V
C
oss
Output Capacitance
–––
160
–––
V
DS
= -50V
C
rss
Reverse Transfer Capacitance
–––
72
–––
ƒ = 1.0MHz, See Fig. 5
C
oss
eff.
Effective Output Capacitance
–––
280
–––
V
GS
= 0V, V
DS
= 0V to –44V
L
D
Internal Drain Inductance
–––
4.5
–––
nH
Between lead,
6mm (0.25in.)
L
S
Internal Source Inductance
–––
7.5
–––
from package
and center of die contact
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
I
S
@ T
C
= 25°C
Continuous Source Current
––– ––– -14
A
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
––– ––– -60
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
–––
–––
-1.2
V T
J
= 25°C,I
S
= -14A,V
GS
= 0V
t
rr
Reverse Recovery Time
–––
57
86
ns T
J
= 25°C ,I
F
= -14A
Q
rr
Reverse Recovery Charge
–––
120
180
nC di/dt = 100A/µs
Avalanche Characteristics
Parameter
Typ. Max. Units
E
AS
Single Pulse Avalanche Energy
–––
190
mJ
I
AR
Avalanche Current
A
E
AR
Repetitive Avalanche Energy
mJ
See Fig. 14, 15, 17a, 17b
IRLIB9343PbF
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2017-04-27
Fig. 2 Typical Output Characteristics
Fig. 3
Typical Transfer Characteristics
Fig. 4
Normalized On-Resistance vs. Temperature
Fig. 1 Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
0.1
1
10
100
-VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
-I
D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
60µs PULSE WIDTH
Tj = 25°C
-2.5V
VGS
TOP -15V
-12V
-10V
-8.0V
-5.5V
-4.5V
-3.0V
BOTTOM
-2.5V
0.1
1
10
100
-VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
-I
D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
60µs PULSE WIDTH
Tj = 175°C
-2.5V
VGS
TOP -15V
-12V
-10V
-8.0V
-5.5V
-4.5V
-3.0V
BOTTOM
-2.5V
0.0
5.0
10.0
15.0
-VGS, Gate-to-Source Voltage (V)
0.1
1.0
10.0
100.0
-I
D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
)
VDS = -25V
60µs PULSE WIDTH
TJ = 25°C
TJ = 175°C
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = -14A
VGS = -10V
1
10
100
-VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
C
, C
ap
ac
ita
nc
e
(p
F
)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
0
10
20
30
40
50
QG Total Gate Charge (nC)
0
4
8
12
16
20
-V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= -44V
VDS= -28V
VDS= -11V
ID= -14A
FOR TEST CIRCUIT
SEE FIGURE 19
IRLIB9343PbF
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2017-04-27
Fig 8. Maximum Safe Operating Area
Fig 10. Threshold Voltage vs. Temperature
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs. Case Temperature
Fig. 7 Typical Source-to-Drain Diode
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-VSD, Source-to-Drain Voltage (V)
0.1
1.0
10.0
100.0
-I
S
D
,
R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
1
10
100
1000
-VDS , Drain-toSource Voltage (V)
1
10
100
1000
-I
D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
25
50
75
100
125
150
175
TJ , Junction Temperature (°C)
0
4
8
12
16
-I
D
, D
ra
in
C
ur
re
nt
(
A
)
-75 -50 -25
0
25
50
75 100 125 150 175
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
-V
G
S
(t
h)
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = -250µA
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
he
rm
al
R
es
po
ns
e
(
Z
th
JC
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
J
J
1
1
2
2
3
3
R
1
R
1
R
2
R
2
R
3
R
3
C
C
Ci=
iRi
Ci=
iRi
Ri (°C/W)
i (sec)
0.877
0.068578
2.089
2.593
0.8737
0.000799
IRLIB9343PbF
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2017-04-27
Fig 13. Maximum Avalanche Energy Vs. Drain Current
Fig 14. Typical Avalanche Current vs. Pulse width
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as T
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 17a, 17b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during
avalanche).
6. I
av
= Allowable avalanche current.
7.
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 11)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
T/ Z
thJC
I
av
= 2
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 12. On-Resistance Vs. Gate Voltage
4.0
6.0
8.0
10.0
-VGS, Gate-to-Source Voltage (V)
0
100
200
300
400
500
600
R
D
S
(o
n)
,
D
ra
in
-t
o
-S
ou
rc
e
O
n
R
es
is
ta
nc
e
(m
)
TJ = 25°C
TJ = 125°C
ID = -14A
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
0
200
400
600
800
1000
E
A
S
, S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
ID
TOP
-5.0A
-5.6A
BOTTOM
-10A
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
0.1
1
10
100
1000
-A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
40
80
120
160
200
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = -10A
IRLIB9343PbF
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2017-04-27
Fig 16. Peak Diode Recovery dv/dt Test Circuit for P-Channel HEXFET® Power MOSFETs
Fig 17a. Unclamped Inductive Test Circuit
Fig 17b. Unclamped Inductive Waveforms
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
Fig 19a. Gate Charge Test Circuit
Fig 19b. Gate Charge Waveform
IRLIB9343PbF
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2017-04-27
TO-220 Full-Pak Package Outline (Dimensions are shown in millimeters (inches))
TO-220 Full-Pak Part Marking Information
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/
TO-220AB Full-Pak packages are not recommended for Surface Mount Application.
IRLIB9343PbF
8
2017-04-27
Qualification information
Qualification level
Industrial
(per JEDEC JESD47F
†
guidelines )
Moisture Sensitivity Level
TO-220 Full-Pak
N/A
(per JEDEC J-STD-020D
†
)
RoHS compliant
Yes
†
Applicable version of JEDEC standard at the time of product release.
Revision History
Date Comments
04/27/2017
Changed datasheet with Infineon logo - all pages.
Corrected Package Outline on page 7.
Added disclaimer on last page.
Trademarks of Infineon Technologies AG
µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™,
CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™,
GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™,
OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID
FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™
Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2016-04-19
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Email:
erratum@infineon.com
Document reference
ifx1
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event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
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In addition, any information given in this
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contact your nearest Infineon Technologies office
(
www.infineon.com
).
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