IRLI520NPbF Product Datasheet

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IRLI520NPbF 

V

DSS 

100V 

R

DS(on)

    

0.18



I

D  

8.1A 

Description 
Fifth Generation HEXFETs from International Rectifier utilize 
advanced processing techniques to achieve extremely low  on-
resistance per silicon area.  This benefit, combined with the fast 
switching speed and ruggedized device design that HEXFET 
Power MOSFETs are well known for, provides the designer with 
an extremely efficient and reliable device for use in a wide variety 
of applications. 
 
The TO-220 Full Pak eliminates the need for additional insulating 
hardware in commercial-industrial applications. The molding 
compound used provides a high isolation capability and a low 
thermal resistance between the tab and external heat sink. This 
isolation is equivalent to using a 100 micron mica barrier with 
standard TO-220 product.  The Fullpak is mounted to a heat sink 
using a single clip or by a single screw fixing. 

 

2017-04-27 

 

Absolute Maximum Ratings 

Symbol Parameter 

Max. 

Units 

I

D

 @ T

C

 = 25°C 

Continuous Drain Current, V

GS

 @ 10V  

8.1 

I

D

 @ T

C

 = 100°C 

Continuous Drain Current, V

GS

 @ 10V  

5.7 

I

DM 

Pulsed Drain Current  35 

P

D

 @T

C

 = 25°C 

Maximum Power Dissipation   

30 

  

Linear Derating Factor 

0.20 

W/°C 

V

GS 

Gate-to-Source Voltage 

± 16

 

E

AS  

Single Pulse Avalanche Energy (Thermally Limited)  85 

mJ  

I

AR 

Avalanche Current  6.0 

E

AR 

Repetitive Avalanche Energy  3.0 

mJ 

dv/dt 

Peak Diode Recovery dv/dt 5.0 

V/ns 

T

J  

Operating Junction and 

-55  to + 175 

 

T

STG 

Storage Temperature Range 

  

°C 

  

Soldering Temperature, for 10 seconds (1.6mm from case) 

300 

 

 

Mounting torque, 6-32 or M3 screw 

10 lbf•in (1.1N•m) 

   

G D S 

Gate Drain Source 

  Logic –Level Gate Drive 

  Advanced Process Technology 
 Isolated 

Package 

  High Voltage Isolation = 2.5KVRMS  

  Sink to Lead Creepage Dist. = 4.8mm 

  Fully Avalanche Rated 

 Lead-Free 

HEXFET

® 

Power MOSFET 

TO-220 Full-Pak 

Base Part Number 

Package Type  

Standard Pack 

Orderable Part Number 

Form Quantity 

IRLI520NPbF 

TO-220 Full-Pak 

Tube 

50 IRLI520NPbF 

Thermal Resistance  

Symbol Parameter 

Typ. 

Max. 

Units 

R

JC

  

Junction-to-Case  

––– 

5.0 

R

JA

  

Junction-to-Ambient  

––– 

65 

°C/W   

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IRLI520NPbF 

 

2017-04-27 

Notes:

 Repetitive rating;  pulse width limited by max. junction temperature. (See fig. 11) 

  Starting  T

J

 = 25°C, L = 4.7mH, R

G

 = 25

, I

AS

 = 6.0A  (See fig. 12) 

  I

SD

 

6.0A, di/dt 340A/µs, V

DD

 

V

(BR)DSS

, T

J

 

 175°C. 

 Pulse width 

300µs; duty cycle  2%. 

  t=60s,  ƒ=60Hz 

  Uses IRL520N data and test conditions. 

Electrical Characteristics @ T

= 25°C (unless otherwise specified) 

  

Parameter Min. 

Typ. 

Max. 

Units 

Conditions 

V

(BR)DSS 

Drain-to-Source Breakdown Voltage 

100 

––– 

––– 

V  V

GS

 = 0V, I

D

 = 250µA 

V

(BR)DSS

/

T

J  

Breakdown Voltage Temp. Coefficient 

–––  0.11  –––  V/°C  Reference to 25°C, I

D

 = 1mA  

R

DS(on) 

   

Static Drain-to-Source On-Resistance    

––– ––– 0.18 



V

GS

 = 10V, I

D

 = 6.0A  

––– ––– 0.22 

V

GS

 = 5.0V, I

D

 = 6.0A  

––– ––– 0.26 

V

GS

 = 4.0V, I

D

 = 5.0A  

V

GS(th) 

Gate Threshold Voltage 

1.0 

––– 

2.0 

V  V

DS

 = V

GS

, I

D

 = 250µA 

gfs 

Forward Trans conductance 

3.1 

––– 

––– 

S  V

DS

 = 25V, I

D

 = 6.0A 

I

DSS 

  

Drain-to-Source Leakage Current   

––– –––  25 

µA 

V

DS

 = 100V, V

GS

 = 0V 

––– ––– 250 

V

DS

 = 80V,V

GS

 = 0V,T

J

 =150°C 

I

GSS 

  

Gate-to-Source Forward Leakage 

––– 

––– 

100 

nA 

V

GS

 = 16V 

Gate-to-Source Reverse Leakage 

––– 

–––  -100 

V

GS

 = -16V 

Q

Total Gate Charge  

––– 

––– 

20 

nC  

I

D

 = 6.0A 

Q

gs 

Gate-to-Source Charge 

––– 

––– 

4.6 

V

DS

 = 80V 

Q

gd 

Gate-to-Drain Charge 

––– 

––– 

10 

V

GS

 = 5.0V , See Fig. 6 and 13 

t

d(on) 

Turn-On Delay Time 

––– 

40 

––– 

ns 

V

DD

 = 50V 

t

Rise Time 

––– 

35 

––– 

I

D

 = 6.0A 

t

d(off) 

Turn-Off Delay Time 

––– 

23 

––– 

R

G

= 11

V

GS

 = 5.0V 

t

Fall Time 

––– 

22 

––– 

R

D

= 8.2

See Fig. 10 

L

D

 

Internal Drain Inductance 

––– 

4.5 

––– 

 nH  

Between lead, 
6mm (0.25in.) 

L

S

 

Internal Source Inductance 

––– 

7.5 

––– 

from package 
and center of die contact 

C

iss 

Input Capacitance 

––– 

440 

––– 

pF   

V

GS

 = 0V 

C

oss 

Output Capacitance 

––– 

97 

––– 

V

DS

 = 25V 

C

rss 

Reverse Transfer Capacitance 

––– 

50 

––– 

ƒ = 1.0MHz, See Fig. 5 

C

 

Drain to Sink Capacitance 

––– 

12 

––– 

ƒ = 1.0MHz 

Source-Drain Ratings and Characteristics 

  

        Parameter 

Min.  Typ.  Max.  Units 

Conditions 

I

  

Continuous Source Current  

––– –––  8.1 

MOSFET symbol 

(Body Diode) 

showing  the 

I

SM 

  

Pulsed Source Current 

––– –––  35 

integral reverse 

(Body Diode)

p-n junction diode. 

V

SD 

Diode Forward Voltage 

––– 

––– 

1.3 

V  T

J

 = 25°C,I

= 6.0A,V

GS

 = 0V 

t

rr  

Reverse Recovery Time  

––– 

110 

160 

ns   T

J

 = 25°C ,I

F

 = 6.0A 

Q

rr  

Reverse Recovery Charge  

––– 

410 

620 

nC    di/dt = 100A/µs 

t

on 

Forward Turn-On Time 

Intrinsic turn-on time is negligible (turn-on is dominated by L

S

+L

D

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IRLI520NPbF 

 

2017-04-27 

Fig. 2 Typical Output Characteristics 

Fig. 3 

Typical Transfer Characteristics

 

 

Fig. 4 Normalized On-Resistance 

vs. Temperature 

Fig. 1 Typical Output Characteristics 

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IRLI520NPbF 

 

2017-04-27 

Fig 5.  Typical Capacitance vs.  
 

      Drain-to-Source Voltage

 

 

Fig 8.  Maximum Safe Operating Area  

Fig. 7 Typical Source-to-Drain Diode 

 Forward Voltage 

Fig 6.  Typical Gate Charge vs. 
 

      Gate-to-Source Voltage

 

 

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IRLI520NPbF 

 

2017-04-27 

Fig 11.  Maximum Effective Transient Thermal Impedance, Junction-to-Case  

Fig 9.  Maximum Drain Current vs. Case Temperature 

Fig 10a.  Switching Time Test Circuit 

Fig 10b.  Switching Time Waveforms 

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IRLI520NPbF 

 

2017-04-27 

 

Fig 12c. Maximum Avalanche Energy 

 vs. Drain Current 

Fig 12a.  Unclamped Inductive Test Circuit 

Fig 12b.  Unclamped Inductive Waveforms 

RG

IAS

0.01

tp

D.U.T

L

VDS

+

- VDD

DRIVER

A

15V

20V

tp

V

(BR)DSS

I

AS

Fig 13b.  Gate Charge Test Circuit 

Fig 13a.   Gate Charge Waveform 

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IRLI520NPbF 

 

2017-04-27 

 

Fig 14. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs 

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IRLI520NPbF 

 

2017-04-27 

 

TO-220 Full-Pak Package Outline (Dimensions are shown in millimeters (inches)) 

TO-220 Full-Pak Part Marking Information 

TO-220AB  Full-Pak packages are not recommended for Surface Mount Application. 

Note: For the most current drawing please refer to  website at 

http://www.irf.com/package/

 

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IRLI520NPbF 

 

2017-04-27 

 

Qualification Information 

Qualification Level  

Industrial 

 (per JEDEC JESD47F) 

† 

TO-220 Full-Pak 

N/A

  

RoHS Compliant 

Yes 

Moisture Sensitivity Level    

†   Applicable version of JEDEC standard at the time of product release. 

Trademarks of Infineon Technologies AG 

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CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, 

GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, 

OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID 

FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™ 

 

Trademarks updated November 2015 

 

Other Trademarks 

All referenced product or service names and trademarks are the property of their respective owners. 

 Edition 2016-04-19 
Published by 
Infineon Technologies AG 
81726 Munich, Germany 
  
© 2016 Infineon Technologies AG. 

All Rights Reserved. 

  
Do you have a question about this 

document? 

Email: 

erratum@infineon.com

 

 

Document reference 
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Revision History  

Date Comments 

4/27/17 



Changed datasheet with Infineon logo - all pages. 



Corrected Package Outline on page 8. 



Added disclaimer on last page. 

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Infineon Technologies