IRFR825TRPbF Product datasheet

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IRFR825TRPbF

12/19/12

www.irf.com

1

HEXFET

®

 Power MOSFET

Features and Benefits

• Fast body diode eliminates the need for external

diodes in ZVS applications.

• Lower Gate charge results in simpler drive requirements.

• Higher Gate voltage threshold offers improved noise

immunity

.

Applications

• Zero Voltage Switching SMPS

• Uninterruptible Power Supplies

• Motor Control applications

PD - 96433A

S

D

G

Notes

  through 

‡

 are on page 2

D-Pak

IRFR825TRPbF

G

S

D

Absolute Maximum Ratings

Parameter

Max.

Units

I

D

 @ T

C

 = 25°C Continuous Drain Current, V

GS 

@ 10V

6.0

I

D

 @ T

C

 = 100°C Continuous Drain Current, V

GS

 @ 10V

3.9

A

I

DM

Pulsed Drain Current 

c

24

P

D

 @T

C

 = 25°C Power Dissipation  

119

W

Linear Derating Factor  

1.0

W/°C

V

GS

Gate-to-Source Voltage

 ± 20

V

dv/dt

Peak Diode Recovery dv/dt 

e

9.9

V/ns

T

Operating Junction and

-55  to + 150

T

STG

Storage Temperature Range

°C

Soldering Temperature, for 10 seconds

Diode Characteristics

        Parameter

Min. Typ. Max. Units

Conditions

I

S

Continuous Source Current 

MOSFET symbol

(Body Diode)

A

showing  the

I

SM

Pulsed Source Current

integral reverse

(Body Diode)

c

p-n junction diode.

V

SD

Diode Forward Voltage

––– –––

1.2

V

T

J

 = 25°C, I

S

 = 6.0A, V

GS

 = 0V 

f

t

rr

Reverse Recovery Time

–––

92

138

ns T

J

 = 25°C, I

F

 = 6.0A

––– 152

228

T

= 125°C, di/dt = 100A/μs 

f

Q

rr

Reverse Recovery Charge

––– 167

251

nC T

J

 = 25°C, I

S

 = 6.0A, V

GS

 = 0V 

f

––– 292

438

T

= 125°C, di/dt = 100A/μs 

f

I

RRM

Reverse Recovery Current

–––

3.6

5.4

A

t

on

Forward Turn-On Time

300 (1.6mm from case )

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

––– –––

–––

–––

6.0

24

T

J

 = 25°C, I

S

 = 6.0A, V

GS

 = 0V              

di/dt = 100A/μs 

f

V

DSS

R

DS(on)

 

typ.

Trr 

typ.

I

D

500V

1.05

Ω

92ns

6.0A

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IRFR825TRPbF

2

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 Repetitive rating; pulse width limited by max.

junction temperature. (See Fig. 11)

‚ Starting T

= 25°C, L = 40mH, R

= 25

Ω,I

AS 

= 3.0A.

(See Figure 13).

ƒ I

SD 

= 6.0A, di/dt ≤ 416A/μs, V

DD

V

(BR)DSS

,T

≤ 150°C.

„ Pulse width ≤ 300μs; duty cycle ≤ 2%.

Notes:

… C

oss

 eff. is a fixed capacitance that gives the same charging timeas

C

oss 

while V

DS 

is rising from 0 to 80% V

DSS

.

 C

oss

 eff.(ER) is a fixed

capacitance that stores the same energy as C

oss

 while V

DS

 is rising

from 0 to 80% V

DSS

.

† R

θ 

is measured at T

J

 approximately 90°C

‡ When mounted on 1" square PCB (FR-4 or G-10 Material). For

recommended footprint and soldering techniquea refer to  applocation
note # AN-  994 echniques refer to application note #AN-994.

Static @ T

J

 = 25°C (unless otherwise specified)

Parameter

Min. Typ. Max. Units

V

(BR)DSS

Drain-to-Source Breakdown Voltage

500

–––

–––

V

ΔV

(BR)DSS

/

ΔT

Breakdown Voltage Temp. Coefficient

–––

0.33

–––

V/°C

R

DS(on)

Static Drain-to-Source On-Resistance

–––

1.05

1.3

Ω

V

GS(th)

Gate Threshold Voltage

3.0

–––

5.0

V

I

DSS

Drain-to-Source Leakage Current

–––

–––

25

μA

–––

–––

2.0

mA

I

GSS

Gate-to-Source Forward Leakage

–––

–––

100

Gate-to-Source Reverse Leakage

–––

–––

-100

Dynamic @ T

J

 = 25°C (unless otherwise specified)

Parameter

Min. Typ. Max. Units

gfs

Forward Transconductance

7.5

–––

–––

S

Q

g

Total Gate Charge

–––

–––

34

Q

gs

Gate-to-Source Charge

–––

–––

11

nC

Q

gd

Gate-to-Drain ("Miller") Charge

–––

–––

14

t

d(on)

Turn-On Delay Time

–––

8.5

–––

t

r

Rise Time

–––

25

–––

ns

t

d(off)

Turn-Off Delay Time

–––

30

–––

t

f

Fall Time

–––

20

–––

C

iss

Input Capacitance

–––

1346

–––

C

oss

Output Capacitance

–––

76

–––

C

rss

Reverse Transfer Capacitance

–––

15

–––

C

oss

Output Capacitance

–––

1231

–––

pF

C

oss

Output Capacitance

–––

25

–––

C

oss

 eff.

Effective Output Capacitance

–––

51

–––

C

oss

 eff. (ER)

Effective Output Capacitance 
(Energy Related) 

Avalanche Characteristics

Parameter

Typ.

Units

E

AS

Single Pulse Avalanche Energy

d

–––

mJ

I

AR

Avalanche Current

c

–––

A

E

AR

Repetitive Avalanche Energy 

c

–––

mJ

Thermal Resistance

Parameter

Typ.

Units

R

θJC 

Junction-to-Case

h

–––

R

θJA 

Junction-to-Ambient (PCB Mount) 

i

–––

°C/W

R

θJA 

Junction-to-Ambient

–––

V

DS

 = V

GS

, I

D

 = 250μA

V

DS

 = 500V, V

GS

 = 0V

V

DS

 = 400V, V

GS

 = 0V, T

J

 = 125°C

Conditions

V

GS

 = 0V, I

D

 = 250μA

Reference to 25°C, I

D

 = 1mA

V

GS

 = 10V, I

D

 = 3.7A 

f

V

GS

 = 20V

Conditions

V

DS

 = 50V, I

D

 = 3.7A

V

GS

 = -20V

I

D

 = 6.0A

V

DS

 = 400V

V

GS

 = 10V, See Fig.14a &14b 

f

V

DD

 = 250V

I

D

 = 6.0A

R

G

 =7.5

Ω

V

GS

 = 10V, See Fig. 15a & 15b 

f

V

GS

 = 0V

V

DS

 = 25V

ƒ = 1.0KHz, See Fig. 5

3

11.9

Max.

178

V

GS

 = 0V,V

DS

 = 0V to 400V 

g

V

GS

 = 0V, V

DS

 = 1.0V, ƒ = 1.0MHz

V

GS

 = 0V, V

DS

 = 400V, ƒ = 1.0MHz

110

Max.

1.05

50

–––

43

–––

nA

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3

Fig 4.  Normalized On-Resistance

Vs. Temperature

Fig 2.  Typical Output Characteristics

Fig 1.  Typical Output Characteristics

Fig 3.  Typical Transfer Characteristics

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.01

0.1

1

10

100

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

VGS

TOP          

15V

10V

8.0V

7.0V

6.0V

5.8V

5.5V

BOTTOM

5.3V

≤60μs 

PULSE WIDTH Tj = 25°C

5.3V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.01

0.1

1

10

100

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

≤60μs 

PULSE WIDTH Tj = 150°C

5.3V

VGS

TOP          

15V

10V

8.0V

7.0V

6.0V

5.8V

5.5V

BOTTOM

5.3V

2

4

6

8

10

VGS, Gate-to-Source Voltage (V)

0.1

1

10

100

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 150°C

VDS = 50V
≤60μs PULSE WIDTH

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ , Junction Temperature (°C)

0.4

0.7

1.0

1.3

1.6

1.9

2.2

2.5

R

D

S

(o

n)

 ,

 D

ra

in

-t

o-

S

ou

rc

O

R

es

is

ta

nc

   

   

   

   

   

   

   

 (

N

or

m

al

iz

ed

)

ID = 6.0A

VGS = 10V

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4

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Fig 5.  Typical Capacitance Vs.

Drain-to-Source Voltage

Fig 6.  Typ. Breadown Voltage

vs. Temperature

1

10

100

1000

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

10000

100000

C

, C

ap

ac

ita

nc

(p

F

)

VGS   = 0V,       f = 1 KHZ

Ciss   = Cgs + Cgd,  C ds SHORTED

Crss   = Cgd 
Coss  = Cds + Cgd

Coss

Crss

Ciss

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ , Temperature ( °C )

500

525

550

575

600

625

V

(B

R

)D

S

S

,  D

ra

in

-t

o-

S

ou

rc

B

re

ak

do

w

V

ol

ta

ge

 (

V

)

Id = 1mA

0.2

0.4

0.6

0.8

1.0

1.2

VSD, Source-to-Drain Voltage (V)

0.1

1

10

100

I S

D

, R

ev

er

se

 D

ra

in

 C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 150°C

VGS = 0V

0

5

10

15

20

25

30

 QG,  Total Gate Charge (nC)

0

2

4

6

8

10

12

14

V

G

S

, G

at

e-

to

-S

ou

rc

V

ol

ta

ge

 (

V

)

VDS= 400V

VDS= 250V

VDS= 100V

ID= 6.0A

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5

Fig 11.  Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9.  Maximum Drain Current Vs.

Case Temperature

Fig 9.  Typical Rdson Vs. Drain Current

1E-006

1E-005

0.0001

0.001

0.01

0.1

t1 , Rectangular Pulse Duration (sec)

0.0001

0.001

0.01

0.1

1

10

T

he

rm

al

 R

es

po

ns

Z

 th

JC

 )

 °

C

/W

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

0

2

4

6

8

10

12

ID , Drain Current (A)

0.8

1.0

1.2

1.4

1.6

1.8

2.0

R

D

S

 (

on

, D

ra

in

-t

o-

S

ou

rc

O

R

es

is

ta

nc

)

VGS = 10V

25

50

75

100

125

150

 TC , Case Temperature (°C)

0

1

2

3

4

5

6

7

I D

,   

D

ra

in

 C

ur

re

nt

 (

A

)

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Fig 13.  Maximum Avalanche Energy

vs. Drain Current

Fig 12.  Maximum Safe Operating Area

Fig 14a.  Gate Charge Test Circuit

Fig 14b.   Gate Charge Waveform

Vds

Vgs

Id

Vgs(th)

Qgs1 Qgs2

Qgd

Qgodr

1K

VCC

DUT

0

L

S

Fig 13b.  Unclamped Inductive Waveforms

Fig 13a.  Unclamped Inductive Test Circuit

tp

V

(BR)DSS

I

AS

RG

IAS

0.01

Ω

tp

D.U.T

L

VDS

+

- VDD

DRIVER

A

15V

20V

25

50

75

100

125

150

Starting TJ , Junction Temperature (°C)

0

100

200

300

400

500

600

700

800

E

A

S

 , 

S

in

gl

P

ul

se

 A

va

la

nc

he

 E

ne

rg

(m

J)

ID

TOP          0.59A
                 1.02A
BOTTOM   3.0A

1

10

100

1000

VDS, Drain-toSource Voltage (V)

0.1

1

10

100

I D

,  

D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

Tc = 25°C

Tj = 150°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA 

LIMITED BY R DS(on)

100μsec

DC

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7

Fig 16. 

Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET

®

 Power MOSFETs

Circuit Layout Considerations

   •  Low Stray Inductance

   •  Ground Plane

   •  Low Leakage Inductance

      Current Transformer

P.W.

Period

di/dt

Diode Recovery

dv/dt

Ripple 

≤ 5%

Body Diode  Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

V

GS

=10V

V

DD

I

SD

Driver Gate Drive

D.U.T. I

SD

Waveform

D.U.T. V

DS

Waveform

Inductor Curent

D = 

P.W.

Period

*

 V

GS

 = 5V for Logic Level Devices

*

+

-

+

+

+

-

-

-

ƒ

„

‚

R

G

V

DD

•  dv/dt controlled by R

G

•  Driver same type as D.U.T.

•  I

SD

 controlled by Duty Factor "D"

•  D.U.T. - Device Under Test

D.U.T



Fig 15a.  Switching Time Test Circuit

Fig 15b.  Switching Time Waveforms

V

GS

V

DS

90%

10%

t

d(on)

t

d(off)

t

r

t

f

V

DS

Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1

R

D

V

GS

R

G

D.U.T.

10V

+

- V

DD

V

GS

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8

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D-Pak (TO-252AA) Part Marking Information

D-Pak (TO-252AA) Package Outline

Dimensions  are  shown  in  millimeters  (inches)

INT ERNATIONAL

ASSEMBLED ON WW 16, 2001
IN THE ASSEMBLY LINE "A"

OR

Note: "P" in assembly line position

EXAMPLE:

LOT CODE 1234

THIS IS AN IRFR120
WITH ASSEMBLY

indicates "Lead-Free"

PRODUCT  (OPTIONAL)

P =  DESIGNATES LEAD-FREE

A =  ASSEMBLY SITE CODE

PART NUMBER

WEEK 16

DATE CODE
YEAR 1 =  2001

RECTIFIER

INTERNATIONAL

LOGO

LOT CODE

ASSEMBLY

34

12

IRFR120

116A

LINE A

34

RECTIFIER

LOGO

IRFR120

12

ASSEMBLY

LOT CODE

YEAR 1 =  2001

DATE CODE

PART NUMBER

WEEK 16

"P" in ass embly line position indicates

"Lead-Free" qualification to the consumer-level

P =  DESIGNATES LEAD-FREE

PRODUCT  QUALIFIED TO  THE

CONSUMER LEVEL (OPTIONAL)

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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9

Data and specifications subject to change without notice.

 This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 101N.Sepulveda Blvd, El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.12/2012

D-Pak (TO-252AA) Tape & Reel Information

Dimensions  are  shown  in  millimeters  (inches)

TR

16.3 ( .641 )
15.7 ( .619 )

8.1 ( .318 )
7.9 ( .312 )

12.1 ( .476 )
11.9 ( .469 )

FEED DIRECTION

FEED DIRECTION

16.3 ( .641 )
15.7 ( .619 )

TRR

TRL

NOTES :
1.  CONTROLLING DIMENSION : MILLIMETER.
2.  ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3.  OUTLINE CONFORMS TO EIA-481 & EIA-541.

NOTES :
1. OUTLINE CONFORMS TO EIA-481.

16 mm

  13 INCH

Maker
Infineon Technologies