IRFR4105ZPbF
IRFU4105ZPbF
HEXFET
®
Power MOSFET
V
DSS
= 55V
R
DS(on)
= 24.5m
Ω
I
D
= 30A
09/27/10
www.irf.com
1
This HEXFET
®
Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating. These features
combine to make this design an extremely efficient
and reliable device for use in a wide variety of
applications.
S
D
G
Description
l
Advanced Process Technology
l
Ultra Low On-Resistance
l
175°C Operating Temperature
l
Fast Switching
l
Repetitive Avalanche Allowed up to Tjmax
l
Lead-Free
Features
D-Pak
IRFR4105ZPbF
I-Pak
IRFU4105ZPbF
HEXFET
®
is a registered trademark of International Rectifier.
Absolute Maximum Ratings
Parameter
Units
I
D
@ T
C
= 25°C Continuous Drain Current, V
GS
@ 10V
(Silicon Limited)
I
D
@ T
C
= 100°C Continuous Drain Current, V
GS
@ 10V
A
I
DM
Pulsed Drain Current
c
P
D
@T
C
= 25°C Power Dissipation
W
Linear Derating Factor
W/°C
V
GS
Gate-to-Source Voltage
V
E
AS (Thermally limited)
Single Pulse Avalanche Energy
d
mJ
E
AS
(Tested )
Single Pulse Avalanche Energy Tested Value
h
I
AR
Avalanche Current
c
A
E
AR
Repetitive Avalanche Energy
g
mJ
T
J
Operating Junction and
T
STG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
Thermal Resistance
Parameter
Typ.
Max.
Units
R
θJC
Junction-to-Case
–––
3.12
R
θJA
Junction-to-Ambient (PCB mount)
i
–––
40
°C/W
R
θJA
Junction-to-Ambient –––
110
46
29
See Fig.12a, 12b, 15, 16
48
0.32
± 20
Max.
30
21
120
-55 to + 175
300 (1.6mm from case )
10 lbf
yin (1.1Nym)
PD - 95374B
IRFR/U4105ZPbF
2
www.irf.com
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage
55
–––
–––
V
∆V
(BR)DSS
/
∆T
J
Breakdown Voltage Temp. Coefficient
–––
0.053
–––
V/°C
R
DS(on)
Static Drain-to-Source On-Resistance
–––
19
24.5
m
Ω
V
GS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
gfs
Forward Transconductance
16
–––
–––
S
I
DSS
Drain-to-Source Leakage Current
–––
–––
20
µA
–––
–––
250
I
GSS
Gate-to-Source Forward Leakage
–––
–––
200
nA
Gate-to-Source Reverse Leakage
–––
–––
-200
Q
g
Total Gate Charge
–––
18
27
Q
gs
Gate-to-Source Charge
–––
5.3
–––
nC
Q
gd
Gate-to-Drain ("Miller") Charge
–––
7.0
–––
t
d(on)
Turn-On Delay Time
–––
10
–––
t
r
Rise Time
–––
40
–––
t
d(off)
Turn-Off Delay Time
–––
26
–––
ns
t
f
Fall Time
–––
24
–––
L
D
Internal Drain Inductance
–––
4.5
–––
Between lead,
nH
6mm (0.25in.)
L
S
Internal Source Inductance
–––
7.5
–––
from package
and center of die contact
C
iss
Input Capacitance
–––
740
–––
C
oss
Output Capacitance
–––
140
–––
C
rss
Reverse Transfer Capacitance
–––
74
–––
pF
C
oss
Output Capacitance
–––
450
–––
C
oss
Output Capacitance
–––
110
–––
C
oss
eff.
Effective Output Capacitance
–––
180
–––
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
–––
–––
30
(Body Diode)
A
I
SM
Pulsed Source Current
–––
–––
120
(Body Diode)
c
V
SD
Diode Forward Voltage
–––
–––
1.3
V
t
rr
Reverse Recovery Time
–––
19
29
ns
Q
rr
Reverse Recovery Charge
–––
14
21
nC
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
V
DS
= 15V, I
D
= 18A
I
D
= 18A
V
DS
= 44V
Conditions
V
GS
= 10V
e
V
GS
= 0V
V
DS
= 25V
ƒ = 1.0MHz
V
GS
= 20V
V
GS
= -20V
MOSFET symbol
showing the
integral reverse
p-n junction diode.
T
J
= 25°C, I
S
= 18A, V
GS
= 0V
e
T
J
= 25°C, I
F
= 18A, V
DD
= 28V
di/dt = 100A/µs
e
Conditions
V
GS
= 0V, I
D
= 250µA
Reference to 25°C, I
D
= 1mA
V
GS
= 10V, I
D
= 18A
e
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 55V, V
GS
= 0V
V
DS
= 55V, V
GS
= 0V, T
J
= 125°C
V
GS
= 0V, V
DS
= 1.0V, ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 44V, ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 44V
f
V
GS
= 10V
e
V
DD
= 28V
I
D
= 18A
R
G
= 24.5
Ω
S
D
G
IRFR/U4105ZPbF
www.irf.com
3
0
1
10
100
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
60µs PULSE WIDTH
Tj = 25°C
4.5V
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance
Vs. Drain Current
V
GS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
0
1
10
100
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
60µs PULSE WIDTH
Tj = 175°C
4.5V
V
GS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4
5
6
7
8
9
10
VGS, Gate-to-Source Voltage (V)
0
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
Α
)
VDS = 25V
60µs PULSE WIDTH
TJ = 25°C
TJ = 175°C
0
10
20
30
40
ID, Drain-to-Source Current (A)
0
5
10
15
20
25
30
G
fs
, F
or
w
ar
d
T
ra
ns
co
nd
uc
ta
nc
e
(S
)
TJ = 25°C
TJ = 175°C
VDS = 8.0V
380µs PULSE WIDTH
IRFR/U4105ZPbF
4
www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
0
200
400
600
800
1000
1200
C
, C
ap
ac
ita
nc
e
(p
F
)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0
5
10
15
20
25
30
QG Total Gate Charge (nC)
0
4
8
12
16
20
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 44V
VDS= 28V
VDS= 11V
ID= 18A
FOR TEST CIRCUIT
SEE FIGURE 13
0.0
0.5
1.0
1.5
2.0
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
1
10
100
1000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
IRFR/U4105ZPbF
www.irf.com
5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Normalized On-Resistance
Vs. Temperature
25
50
75
100
125
150
175
TJ , Junction Temperature (°C)
0
5
10
15
20
25
30
I D
,
D
ra
in
C
ur
re
nt
(
A
)
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 18A
VGS = 10V
1E-006
1E-005
0.0001
0.001
0.01
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
he
rm
al
R
es
po
ns
e
(
Z
th
JC
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W)
τi (sec)
1.100 0.000174
1.601 0.000552
0.418 0.007193
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
τ
τ
C
Ci i
/Ri
Ci=
τi/Ri
IRFR/U4105ZPbF
6
www.irf.com
Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
µF
50K
Ω
.2
µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage Vs. Temperature
RG
IAS
0.01
Ω
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
V
GS
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
0
20
40
60
80
100
120
E
A
S
, S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
I D
TOP
2.0A
3.5A
BOTTOM
18A
-75 -50 -25
0
25
50
75 100 125 150 175
TJ , Temperature ( °C )
2.0
2.5
3.0
3.5
4.0
4.5
V
G
S
(t
h)
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 250µA
IRFR/U4105ZPbF
www.irf.com
7
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/ Z
thJC
I
av
=
2
DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
0.1
1
10
100
A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
∆ Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
5
10
15
20
25
30
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 18A
IRFR/U4105ZPbF
8
www.irf.com
Fig 17.
Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
V
DS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
IRFR/U4105ZPbF
www.irf.com
9
D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
INTERNATIONAL
ASSEMBLED ON WW 16, 2001
IN THE ASSEMBLY LINE "A"
OR
Note: "P" in assembly line position
EXAMPLE:
LOT CODE 1234
THIS IS AN IRFR120
WITH ASSEMBLY
indicates "Lead-Free"
PRODUCT (OPTIONAL)
P = DESIGNATES LEAD-FREE
A = ASSEMBLY SITE CODE
PART NUMBER
WEEK 16
DATE CODE
YEAR 1 = 2001
RECTIFIER
INTERNATIONAL
LOGO
LOT CODE
ASSEMBLY
34
12
IRFR120
116A
LINE A
34
RECTIFIER
LOGO
IRFR120
12
ASSEMBLY
LOT CODE
YEAR 1 = 2001
DATE CODE
PART NUMBER
WEEK 16
"P" in assembly line position indicates
"Lead-Free" qualification to the consumer-level
P = DESIGNATES LEAD-FREE
PRODUCT QUALIFIED TO THE
CONSUMER LEVEL (OPTIONAL)
Notes:
1. For an Automotive Qualified version of this part please see
http://www.irf.com/product-info/datasheets/data/
auirfr4105z.pdf
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRFR/U4105ZPbF
10
www.irf.com
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
78
LINE A
LOGO
INTERNATIONAL
RECTIFIER
OR
PRODUCT (OPTIONAL)
P = DESIGNATES LEAD-FREE
A = ASSEMBLY SITE CODE
IRFU120
PART NUMBER
WEEK 19
DATE CODE
YEAR 1 = 2001
RECTIFIER
INTERNATIONAL
LOGO
ASS EMBLY
LOT CODE
IRFU120
56
DATE CODE
PART NUMBER
LOT CODE
ASSEMBLY
56
78
YEAR 1 = 2001
WEEK 19
119A
indicates Lead-Free"
AS SEMBLED ON WW 19, 2001
IN THE ASS EMBLY LINE "A"
Note: "P" in assembly line position
EXAMPLE:
WITH AS SEMBLY
THIS IS AN IRFU120
LOT CODE 5678
Notes:
1. For an Automotive Qualified version of this part please see
http://www.irf.com/product-info/datasheets/data/
auirfr4105z.pdf
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRFR4105ZPbF
IRFU4105ZPbF
HEXFET
®
Power MOSFET
V
DSS
= 55V
R
DS(on)
= 24.5m
Ω
I
D
= 30A
09/27/10
www.irf.com
1
This HEXFET
®
Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating. These features
combine to make this design an extremely efficient
and reliable device for use in a wide variety of
applications.
S
D
G
Description
l
Advanced Process Technology
l
Ultra Low On-Resistance
l
175°C Operating Temperature
l
Fast Switching
l
Repetitive Avalanche Allowed up to Tjmax
l
Lead-Free
Features
D-Pak
IRFR4105ZPbF
I-Pak
IRFU4105ZPbF
HEXFET
®
is a registered trademark of International Rectifier.
Absolute Maximum Ratings
Parameter
Units
I
D
@ T
C
= 25°C Continuous Drain Current, V
GS
@ 10V
(Silicon Limited)
I
D
@ T
C
= 100°C Continuous Drain Current, V
GS
@ 10V
A
I
DM
Pulsed Drain Current
c
P
D
@T
C
= 25°C Power Dissipation
W
Linear Derating Factor
W/°C
V
GS
Gate-to-Source Voltage
V
E
AS (Thermally limited)
Single Pulse Avalanche Energy
d
mJ
E
AS
(Tested )
Single Pulse Avalanche Energy Tested Value
h
I
AR
Avalanche Current
c
A
E
AR
Repetitive Avalanche Energy
g
mJ
T
J
Operating Junction and
T
STG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
Thermal Resistance
Parameter
Typ.
Max.
Units
R
θJC
Junction-to-Case
–––
3.12
R
θJA
Junction-to-Ambient (PCB mount)
i
–––
40
°C/W
R
θJA
Junction-to-Ambient –––
110
46
29
See Fig.12a, 12b, 15, 16
48
0.32
± 20
Max.
30
21
120
-55 to + 175
300 (1.6mm from case )
10 lbf
yin (1.1Nym)
PD - 95374B
IRFR/U4105ZPbF
2
www.irf.com
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage
55
–––
–––
V
∆V
(BR)DSS
/
∆T
J
Breakdown Voltage Temp. Coefficient
–––
0.053
–––
V/°C
R
DS(on)
Static Drain-to-Source On-Resistance
–––
19
24.5
m
Ω
V
GS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
gfs
Forward Transconductance
16
–––
–––
S
I
DSS
Drain-to-Source Leakage Current
–––
–––
20
µA
–––
–––
250
I
GSS
Gate-to-Source Forward Leakage
–––
–––
200
nA
Gate-to-Source Reverse Leakage
–––
–––
-200
Q
g
Total Gate Charge
–––
18
27
Q
gs
Gate-to-Source Charge
–––
5.3
–––
nC
Q
gd
Gate-to-Drain ("Miller") Charge
–––
7.0
–––
t
d(on)
Turn-On Delay Time
–––
10
–––
t
r
Rise Time
–––
40
–––
t
d(off)
Turn-Off Delay Time
–––
26
–––
ns
t
f
Fall Time
–––
24
–––
L
D
Internal Drain Inductance
–––
4.5
–––
Between lead,
nH
6mm (0.25in.)
L
S
Internal Source Inductance
–––
7.5
–––
from package
and center of die contact
C
iss
Input Capacitance
–––
740
–––
C
oss
Output Capacitance
–––
140
–––
C
rss
Reverse Transfer Capacitance
–––
74
–––
pF
C
oss
Output Capacitance
–––
450
–––
C
oss
Output Capacitance
–––
110
–––
C
oss
eff.
Effective Output Capacitance
–––
180
–––
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
–––
–––
30
(Body Diode)
A
I
SM
Pulsed Source Current
–––
–––
120
(Body Diode)
c
V
SD
Diode Forward Voltage
–––
–––
1.3
V
t
rr
Reverse Recovery Time
–––
19
29
ns
Q
rr
Reverse Recovery Charge
–––
14
21
nC
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
V
DS
= 15V, I
D
= 18A
I
D
= 18A
V
DS
= 44V
Conditions
V
GS
= 10V
e
V
GS
= 0V
V
DS
= 25V
ƒ = 1.0MHz
V
GS
= 20V
V
GS
= -20V
MOSFET symbol
showing the
integral reverse
p-n junction diode.
T
J
= 25°C, I
S
= 18A, V
GS
= 0V
e
T
J
= 25°C, I
F
= 18A, V
DD
= 28V
di/dt = 100A/µs
e
Conditions
V
GS
= 0V, I
D
= 250µA
Reference to 25°C, I
D
= 1mA
V
GS
= 10V, I
D
= 18A
e
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 55V, V
GS
= 0V
V
DS
= 55V, V
GS
= 0V, T
J
= 125°C
V
GS
= 0V, V
DS
= 1.0V, ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 44V, ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 44V
f
V
GS
= 10V
e
V
DD
= 28V
I
D
= 18A
R
G
= 24.5
Ω
S
D
G
IRFR/U4105ZPbF
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3
0
1
10
100
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
60µs PULSE WIDTH
Tj = 25°C
4.5V
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance
Vs. Drain Current
V
GS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
0
1
10
100
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
60µs PULSE WIDTH
Tj = 175°C
4.5V
V
GS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4
5
6
7
8
9
10
VGS, Gate-to-Source Voltage (V)
0
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
Α
)
VDS = 25V
60µs PULSE WIDTH
TJ = 25°C
TJ = 175°C
0
10
20
30
40
ID, Drain-to-Source Current (A)
0
5
10
15
20
25
30
G
fs
, F
or
w
ar
d
T
ra
ns
co
nd
uc
ta
nc
e
(S
)
TJ = 25°C
TJ = 175°C
VDS = 8.0V
380µs PULSE WIDTH
IRFR/U4105ZPbF
4
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
0
200
400
600
800
1000
1200
C
, C
ap
ac
ita
nc
e
(p
F
)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0
5
10
15
20
25
30
QG Total Gate Charge (nC)
0
4
8
12
16
20
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 44V
VDS= 28V
VDS= 11V
ID= 18A
FOR TEST CIRCUIT
SEE FIGURE 13
0.0
0.5
1.0
1.5
2.0
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
1
10
100
1000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
IRFR/U4105ZPbF
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Normalized On-Resistance
Vs. Temperature
25
50
75
100
125
150
175
TJ , Junction Temperature (°C)
0
5
10
15
20
25
30
I D
,
D
ra
in
C
ur
re
nt
(
A
)
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 18A
VGS = 10V
1E-006
1E-005
0.0001
0.001
0.01
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
he
rm
al
R
es
po
ns
e
(
Z
th
JC
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W)
τi (sec)
1.100 0.000174
1.601 0.000552
0.418 0.007193
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
τ
τ
C
Ci i
/Ri
Ci=
τi/Ri
IRFR/U4105ZPbF
6
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Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
µF
50K
Ω
.2
µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage Vs. Temperature
RG
IAS
0.01
Ω
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
V
GS
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
0
20
40
60
80
100
120
E
A
S
, S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
I D
TOP
2.0A
3.5A
BOTTOM
18A
-75 -50 -25
0
25
50
75 100 125 150 175
TJ , Temperature ( °C )
2.0
2.5
3.0
3.5
4.0
4.5
V
G
S
(t
h)
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 250µA
IRFR/U4105ZPbF
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7
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/ Z
thJC
I
av
=
2
DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
0.1
1
10
100
A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
∆ Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
5
10
15
20
25
30
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 18A
IRFR/U4105ZPbF
8
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Fig 17.
Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
V
DS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
IRFR/U4105ZPbF
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9
D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
INTERNATIONAL
ASSEMBLED ON WW 16, 2001
IN THE ASSEMBLY LINE "A"
OR
Note: "P" in assembly line position
EXAMPLE:
LOT CODE 1234
THIS IS AN IRFR120
WITH ASSEMBLY
indicates "Lead-Free"
PRODUCT (OPTIONAL)
P = DESIGNATES LEAD-FREE
A = ASSEMBLY SITE CODE
PART NUMBER
WEEK 16
DATE CODE
YEAR 1 = 2001
RECTIFIER
INTERNATIONAL
LOGO
LOT CODE
ASSEMBLY
34
12
IRFR120
116A
LINE A
34
RECTIFIER
LOGO
IRFR120
12
ASSEMBLY
LOT CODE
YEAR 1 = 2001
DATE CODE
PART NUMBER
WEEK 16
"P" in assembly line position indicates
"Lead-Free" qualification to the consumer-level
P = DESIGNATES LEAD-FREE
PRODUCT QUALIFIED TO THE
CONSUMER LEVEL (OPTIONAL)
Notes:
1. For an Automotive Qualified version of this part please see
http://www.irf.com/product-info/datasheets/data/
auirfr4105z.pdf
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRFR/U4105ZPbF
10
www.irf.com
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
78
LINE A
LOGO
INTERNATIONAL
RECTIFIER
OR
PRODUCT (OPTIONAL)
P = DESIGNATES LEAD-FREE
A = ASSEMBLY SITE CODE
IRFU120
PART NUMBER
WEEK 19
DATE CODE
YEAR 1 = 2001
RECTIFIER
INTERNATIONAL
LOGO
ASS EMBLY
LOT CODE
IRFU120
56
DATE CODE
PART NUMBER
LOT CODE
ASSEMBLY
56
78
YEAR 1 = 2001
WEEK 19
119A
indicates Lead-Free"
AS SEMBLED ON WW 19, 2001
IN THE ASS EMBLY LINE "A"
Note: "P" in assembly line position
EXAMPLE:
WITH AS SEMBLY
THIS IS AN IRFU120
LOT CODE 5678
Notes:
1. For an Automotive Qualified version of this part please see
http://www.irf.com/product-info/datasheets/data/
auirfr4105z.pdf
2. For the most current drawing please refer to IR website at http://www.irf.com/package/