IRFR_U4104PbF Product Data Sheet

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IRFR4104PbF
IRFU4104PbF

HEXFET

®

 Power MOSFET

V

DSS

 = 40V

R

DS(on)

 = 5.5m

I

D

 = 42A

09/21/10

www.irf.com

1

This HEXFET

®

 Power MOSFET utilizes the latest

processing techniques to achieve extremely low on-
resistance per silicon area. Additional features of this
design  are a 175°C junction operating temperature,
fast switching speed and improved repetitive avalanche
rating . These features combine to make this design
an extremely efficient and reliable device for use in a
wide variety of applications.

S

D

G

Description

l

Advanced Process Technology

l

Ultra Low On-Resistance

l

175°C Operating Temperature

l

Fast Switching

l

Repetitive Avalanche Allowed up to Tjmax

l

Lead-Free

Features

D-Pak

IRFR4104PbF

I-Pak

IRFU4104PbF

HEXFET

®

 is a registered trademark of International Rectifier.

Absolute Maximum Ratings

Parameter

Units

I

D

 @ T

C

 = 25°C Continuous Drain Current, V

GS

 @ 10V 

(Silicon Limited)

I

D

 @ T

C

 = 100°C Continuous Drain Current, V

GS

 @ 10V 

A

I

D

 @ T

C

 = 25°C Continuous Drain Current, V

GS

 @ 10V 

(Package Limited)

I

DM

Pulsed Drain Current 

c

P

D

 @T

C

 = 25°C Power Dissipation  

W

Linear Derating Factor  

W/°C

V

GS

Gate-to-Source Voltage

V

E

AS (Thermally limited) 

Single Pulse Avalanche Energy

d

mJ

E

AS 

(Tested ) 

Single Pulse Avalanche Energy Tested Value 

h

I

AR

Avalanche Current

c

A

E

AR

Repetitive Avalanche Energy 

g

mJ

T

Operating Junction and

T

STG

Storage Temperature Range

°C

Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw

Thermal Resistance

Parameter

Typ.

Max.

Units

R

θJC 

Junction-to-Case

–––

1.05

R

θJA 

Junction-to-Ambient (PCB mount) 

i

–––

40

°C/W

R

θJA 

Junction-to-Ambient –––

110

310

145

See Fig.12a, 12b, 15, 16

140

0.95

 ± 20

Max.

119

84

480

42

-55  to + 175

300 (1.6mm from case )

10 lbf

yin (1.1Nym)

PD - 95425B

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2

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Electrical Characteristics @ T

J

 = 25°C (unless otherwise specified)

Parameter

Min. Typ. Max. Units

V

(BR)DSS

Drain-to-Source Breakdown Voltage

40

–––

–––

V

∆V

(BR)DSS

/

∆T

Breakdown Voltage Temp. Coefficient

–––

0.032

–––

V/°C

R

DS(on)

Static Drain-to-Source On-Resistance

–––

4.3

5.5

m

V

GS(th)

Gate Threshold Voltage

2.0

–––

4.0

V

gfs

Forward Transconductance

58

–––

–––

S

I

DSS

Drain-to-Source Leakage Current

–––

–––

20

µA

–––

–––

250

I

GSS

Gate-to-Source Forward Leakage

–––

–––

200

nA

Gate-to-Source Reverse Leakage

–––

–––

-200

Q

g

Total Gate Charge

–––

59

89

Q

gs

Gate-to-Source Charge

–––

19

–––

nC

Q

gd

Gate-to-Drain ("Miller") Charge

–––

24

–––

t

d(on)

Turn-On Delay Time

–––

17

–––

t

r

Rise Time

–––

69

–––

t

d(off)

Turn-Off Delay Time

–––

37

–––

ns

t

f

Fall Time

–––

36

–––

L

D

Internal Drain Inductance

–––

4.5

–––

Between lead, 

nH

6mm (0.25in.)

L

S

Internal Source Inductance

–––

7.5

–––

from package

and center of die contact

C

iss

Input Capacitance

–––

2950

–––

C

oss

Output Capacitance

–––

660

–––

C

rss

Reverse Transfer Capacitance

–––

370

–––

pF

C

oss

Output Capacitance

–––

2130

–––

C

oss

Output Capacitance

–––

590

–––

C

oss

 eff.

Effective Output Capacitance

–––

850

–––

Source-Drain Ratings and Characteristics

        Parameter

Min. Typ. Max. Units

I

S

Continuous Source Current 

–––

–––

42

(Body Diode)

A

I

SM

Pulsed Source Current

–––

–––

480

(Body Diode)

c

V

SD

Diode Forward Voltage

–––

–––

1.3

V

t

rr

Reverse Recovery Time

–––

28

42

ns

Q

rr

Reverse Recovery Charge

–––

24

36

nC

t

on

Forward Turn-On Time

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

V

GS

 = 0V,  V

DS

 = 1.0V,  ƒ = 1.0MHz

V

GS

 = 0V,  V

DS

 = 32V,  ƒ = 1.0MHz

V

GS

 = 0V, V

DS

 = 0V to 32V 

f

V

GS

 = 10V 

e

V

DD

 = 20V

I

D

 = 42A

R

G

 = 6.8 

T

J

 = 25°C, I

S

 = 42A, V

GS

 = 0V 

e

T

J

 = 25°C, I

F

 = 42A, V

DD

 = 20V

di/dt = 100A/µs 

e

Conditions

V

GS

 = 0V, I

D

 = 250µA

Reference to 25°C, I

D

 = 1mA 

V

GS

 = 10V, I

D

 = 42A 

e

V

DS

 = V

GS

, I

D

 = 250µA

V

DS

 = 40V, V

GS

 = 0V

V

DS

 = 40V, V

GS

 = 0V, T

J

 = 125°C

MOSFET symbol

showing  the
integral reverse

p-n junction diode.

V

DS

 = 10V, I

D

 = 42A

I

D

 = 42A

V

DS

 = 32V

Conditions

V

GS

 = 10V 

e

V

GS

 = 0V

V

DS

 = 25V

ƒ = 1.0MHz

V

GS

 = 20V

V

GS

 = -20V

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3

Fig 2.  Typical Output Characteristics

Fig 1.  Typical Output Characteristics

Fig 3.  Typical Transfer Characteristics

Fig 4.  Typical Forward Transconductance

Vs. Drain Current

0

1

10

100

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

60µs PULSE WIDTH

Tj = 25°C

4.5V

            V

GS

 TOP          15V

                   10V

                8.0V

                   7.0V

                   6.0V

                   5.5V

                   5.0V

BOTTOM    4.5V

0

1

10

100

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

60µs PULSE WIDTH

Tj = 175°C

4.5V

            V

GS

 TOP          15V

                   10V

                8.0V

                   7.0V

                   6.0V

                   5.5V

                   5.0V

BOTTOM   4.5V

4

6

8

10

VGS, Gate-to-Source Voltage (V)

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

Α

)

VDS = 20V

60µs PULSE WIDTH

TJ = 25°C

TJ = 175°C

0

20

40

60

80

100

ID, Drain-to-Source Current (A)

0

20

40

60

80

100

120

G

fs

, F

or

w

ar

T

ra

ns

co

nd

uc

ta

nc

(S

)

TJ = 25°C

TJ = 175°C

VDS = 10V

380µs PULSE WIDTH

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Fig 8.  Maximum Safe Operating Area

Fig 6.  Typical Gate Charge Vs.

Gate-to-Source Voltage

Fig 5.  Typical Capacitance Vs.

Drain-to-Source Voltage

Fig 7.  Typical Source-Drain Diode

Forward Voltage

0.0

0.5

1.0

1.5

2.0

VSD, Source-toDrain Voltage (V)

0.1

1.0

10.0

100.0

1000.0

I S

D

, R

ev

er

se

 D

ra

in

 C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 175°C

VGS = 0V

1

10

100

VDS, Drain-to-Source Voltage (V)

0

1000

2000

3000

4000

5000

C

, C

ap

ac

ita

nc

(p

F

)

Coss

Crss

Ciss

VGS   = 0V,       f = 1 MHZ

Ciss   = Cgs + Cgd,  C ds SHORTED

Crss   = Cgd 
Coss  = Cds + Cgd

0

20

40

60

80

100

 QG  Total Gate Charge (nC)

0

4

8

12

16

20

V

G

S

, G

at

e-

to

-S

ou

rc

V

ol

ta

ge

 (

V

)

VDS= 32V

VDS= 20V

ID= 42A

0

1

10

100

1000

VDS  , Drain-toSource Voltage (V)

0.1

1

10

100

1000

10000

I D

,  

D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA 

LIMITED BY R DS(on)

100µsec

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5

Fig 11.  Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9.  Maximum Drain Current Vs.

Case Temperature

Fig 10.  Normalized On-Resistance

Vs. Temperature

25

50

75

100

125

150

175

 TC , Case Temperature (°C)

0

20

40

60

80

100

120

I D

 , 

D

ra

in

 C

ur

re

nt

 (

A

)

LIMITED BY PACKAGE

-60 -40 -20 0

20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

R

D

S

(o

n)

 ,

 D

ra

in

-t

o-

S

ou

rc

O

R

es

is

ta

nc

   

   

   

   

   

   

   

 (

N

or

m

al

iz

ed

)

ID = 42A

VGS = 10V

1E-006

1E-005

0.0001

0.001

0.01

0.1

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

1

10

T

he

rm

al

 R

es

po

ns

Z

 th

JC

 )

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

Ri (°C/W)   

 τi (sec)

0.5067      0.000414
0.5428      0.004081

τ

J

τ

J

τ

1

τ

1

τ

2

τ

2

R

1

R

1

R

2

R

2

τ

τ

C

Ci   i

/Ri

Ci= 

τi/Ri

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Q

G

Q

GS

Q

GD

V

G

Charge

D.U.T.

V

DS

I

D

I

G

3mA

V

GS

.3

µF

50K

.2

µF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

+

-

10 V

Fig 13b.  Gate Charge Test Circuit

Fig 13a.  Basic Gate Charge Waveform

Fig 12c.  Maximum Avalanche Energy

Vs. Drain Current

Fig 12b.  Unclamped Inductive Waveforms

Fig 12a.  Unclamped Inductive Test Circuit

tp

V

(BR)DSS

I

AS

Fig 14.  Threshold Voltage Vs. Temperature

RG

IAS

0.01

tp

D.U.T

L

VDS

+

- VDD

DRIVER

A

15V

20V

V

GS

25

50

75

100

125

150

175

Starting TJ, Junction Temperature (°C)

0

100

200

300

400

500

600

E

A

S

, S

in

gl

P

ul

se

 A

va

la

nc

he

 E

ne

rg

(m

J)

                 I D

TOP  

        9.2A

               13A

BOTTOM 

  42A

-75 -50 -25

0

25

50

75 100 125 150 175

TJ , Temperature ( °C )

1.0

2.0

3.0

4.0

V

G

S

(t

h)

 G

at

th

re

sh

ol

V

ol

ta

ge

 (

V

)

ID = 250µA

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7

Fig 15.  Typical Avalanche Current Vs.Pulsewidth

Fig 16.  Maximum Avalanche Energy

Vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:

  Purely a thermal phenomenon and failure occurs at a

    temperature far in excess of T

jmax

. This is validated for

    every part type.
2. Safe operation in Avalanche is allowed as long asT

jmax

 is

  not exceeded.

3. Equation below based on circuit and waveforms shown in

  Figures 12a, 12b.

4. P

D (ave) 

= Average power dissipation per single

    avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
    voltage increase during avalanche).
6. I

av 

= Allowable avalanche current.

7. 

∆T

 = 

Allowable rise in junction temperature, not to exceed

    T

jmax 

(assumed as 25°C in Figure 15, 16).

  t

av = 

Average time in avalanche.

  D = Duty cycle in avalanche =  t

av 

·f

  Z

thJC

(D, t

av

) = Transient thermal resistance, see figure 11)

P

D (ave)

 = 1/2 ( 1.3·BV·I

av

) =

 DT/ Z

thJC

I

av 

=

 

2

DT/ [1.3·BV·Z

th

]

E

AS (AR)

 = P

D (ave)

·t

av

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

tav (sec)

0.1

1

10

100

1000

A

va

la

nc

he

 C

ur

re

nt

 (

A

)

0.05

Duty Cycle = Single Pulse

0.10

Allowed avalanche Current vs 
avalanche pulsewidth, tav 
assuming 

∆ Tj = 25°C due to 

avalanche losses. Note: In no 
case should Tj be allowed to 
exceed Tjmax

0.01

25

50

75

100

125

150

175

Starting TJ , Junction Temperature (°C)

0

40

80

120

160

E

A

R

 , 

A

va

la

nc

he

 E

ne

rg

(m

J)

TOP          Single Pulse                
BOTTOM   1% Duty Cycle
ID = 42A

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Fig 17. 

Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET

®

 Power MOSFETs

Circuit Layout Considerations

   •  Low Stray Inductance

   •  Ground Plane

   •  Low Leakage Inductance

      Current Transformer

P.W.

Period

di/dt

Diode Recovery

dv/dt

Ripple 

≤ 5%

Body Diode  Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

V

GS

=10V

V

DD

I

SD

Driver Gate Drive

D.U.T. I

SD

Waveform

D.U.T. V

DS

Waveform

Inductor Curent

D = 

P.W.

Period

*

 V

GS

 = 5V for Logic Level Devices

*

+

-

+

+

+

-

-

-

ƒ

„

‚

R

G

V

DD

•  dv/dt controlled by R

G

•  Driver same type as D.U.T.

•  I

SD

 controlled by Duty Factor "D"

•  D.U.T. - Device Under Test

D.U.T



V

DS

90%

10%
V

GS

t

d(on)

t

r

t

d(off)

t

f

V

DS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

R

D

V

GS

R

G

D.U.T.

10V

+

-

V

DD

Fig 18a.  Switching Time Test Circuit

Fig 18b.  Switching Time Waveforms

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D-Pak (TO-252AA) Part Marking Information

D-Pak (TO-252AA) Package Outline

Dimensions  are  shown  in  millimeters  (inches)

INT ERNATIONAL

ASSEMBLED ON WW 16, 2001
IN THE AS SEMBLY LINE "A"

OR

Note: "P" in assembly line position

EXAMPLE:

LOT  CODE 1234

T HIS  IS  AN IRFR120
WITH AS SEMBLY

indicates  "Lead-Free"

PRODUCT  (OPTIONAL)

P =  DESIGNATES  LEAD-FREE

A =  ASS EMBLY SITE CODE

PART NUMBER

WEEK 16

DAT E CODE
YEAR 1 =  2001

RECTIFIER

INTERNAT IONAL

LOGO

LOT CODE

AS SEMBLY

34

12

IRFR120

116A

LINE A

34

RECTIFIER

LOGO

IRFR120

12

AS SEMBLY

LOT CODE

YEAR 1 =  2001

DAT E CODE

PART  NUMBER

WEEK 16

"P" in ass embly line pos ition indicates

"Lead-Free" qualification to the consumer-level

P =  DESIGNATES  LEAD-FREE

PRODUCT  QUALIFIED TO T HE

CONS UMER LEVEL (OPTIONAL)

Notes:

1. For an Automotive Qualified version of this part please see 

http://www.irf.com/product-info/datasheets/

     data/auirfr4104.pdf

2. For the most current drawing please refer to IR website at http://www.irf.com/package/

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I-Pak (TO-251AA) Package Outline

Dimensions  are  shown  in  millimeters  (inches)

I-Pak (TO-251AA) Part Marking Information

78

LINE A

LOGO

INT ERNATIONAL

RECTIFIER

OR

PRODUCT (OPTIONAL)

P =  DESIGNATES LEAD-FREE

A =  ASSEMBLY  SITE CODE

IRFU120

PART NUMBER

WEEK 19

DAT E CODE
YEAR 1 =  2001

RECTIFIER

INTERNATIONAL

LOGO

ASSEMBLY
LOT CODE

IRFU120

56

DATE CODE

PART NUMBER

LOT  CODE

ASSEMBLY

56

78

YEAR 1 =  2001
WEEK 19

119A

indicates Lead-Free"

ASSEMBLED ON WW 19, 2001
IN THE ASS EMBLY LINE "A"

Note: "P" in assembly line position

EXAMPLE:

WITH ASS EMBLY

THIS IS AN IRFU120

LOT CODE 5678

Notes:

1. For an Automotive Qualified version of this part please see 

http://www.irf.com/product-info/datasheets/

     data/auirfr4104.pdf

2. For the most current drawing please refer to IR website at http://www.irf.com/package/

Maker
Infineon Technologies