IRFR3707ZPbF
IRFU3707ZPbF
V
DSS
30V
R
DS(on)
max
9.5m
Qg
9.6nC
1
2016-5-31
Absolute Maximum Ratings
Symbol Parameter
Max.
Units
V
DS
Drain -to-Source Voltage
30
V
V
GS
Gate-to-Source Voltage
± 20
V
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
56
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V
39
A
I
DM
Pulsed Drain Current 220
P
D
@T
C
= 25°C
Maximum Power Dissipation
50
W
P
D
@T
C
= 100°C
Maximum Power Dissipation
25
W
Linear Derating Factor
0.33
W/°C
T
J
Operating Junction and
-55 to + 175
T
STG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds (1.6mm from case)
300
D- Pak
IRFR3707ZPbF
G D S
Gate Drain Source
Applications
High Frequency Synchronous Buck
Converters for Computer Processor Power
High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
G
I- Pak
IRFU3707ZPbF
HEXFET
®
Power MOSFET
Base part number
Package Type
Standard Pack
Form
Quantity
IRFU3707ZPbF
I-Pak
Tube
75
IRFU3707ZPbF
IRFR3707ZPbF
D-Pak
Tube
75
IRFR3707ZPbF
Tape and Reel Left
3000
IRFR3707ZTRLPbF
Orderable Part Number
S
G
D
D
S
D
Benefits
Very
Low
R
DS(on)
at 4.5V V
GS
Ultra - Low Gate Impedance
Fully Characterized Avalanche Voltage and Current
Lead-Free
Thermal Resistance
Symbol Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case
–––
3.0
°C/W
R
JA
Junction-to-Ambient ( PCB Mount) –––
50
R
JA
Junction-to-Ambient
–––
110
Notes through are on page 2.
IRFR/U3707ZPbF
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2016-5-31
Notes:
Repetitive rating; pulse width limited by max. junction temperature
starting T
J
= 25°C, L = 0.58mH, R
G
= 25
, I
AS
= 12A.
Pulse width
400µs; duty cycle 2%.
Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994.
Static @ T
J
= 25°C (unless otherwise specified)
Parameter Min.
Typ.
Max.
Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
30
–––
–––
V V
GS
= 0V, I
D
= 250µA
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
––– 0.023 ––– V/°C Reference to 25°C, I
D
= 1mA
R
DS(on)
Static Drain-to-Source On-Resistance
––– 7.5 9.5
m
V
GS
= 10V, I
D
= 15A
––– 10 12.5
V
GS
= 4.5V, I
D
= 12A
V
GS(th)
Gate Threshold Voltage
1.35 1.80 2.25
V
V
DS
= V
GS
, I
D
= 25µA
V
GS(th)
/
T
J
Gate Threshold Voltage Temp. Coefficient
–––
-5.0
––– mV/°C
I
DSS
Drain-to-Source Leakage Current
––– ––– 1.0
µA
V
DS
= 24V, V
GS
= 0V
––– ––– 150
V
DS
= 24V,V
GS
= 0V,T
J
=125°C
I
GSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
V
GS
= 20V
Gate-to-Source Reverse Leakage
–––
-100
V
GS
= -20V
gfs
Forward Trans conductance
71
–––
–––
S V
DS
= 15V, I
D
= 12A
Q
g
Total Gate Charge
–––
9.6
14
nC
Q
gs1
Pre-Vth Gate-to-Source Charge
–––
2.6
–––
V
DS
= 15V
Q
gs2
Post-Vth Gate-to-Source Charge
––– 0.90 –––
V
GS
= 4.5V
Q
gd
Gate-to-Drain Charge
–––
3.5
–––
I
D
= 12A
Q
godr
Gate Charge Overdrive
–––
2.6
–––
See Fig. 16
Q
sw
Switch Charge (Q
gs2
+ Q
gd
) –––
4.4
–––
Q
oss
Output Charge
–––
5.8
–––
nC V
DS
= 15V, V
GS
= 0V
t
d(on)
Turn-On Delay Time
–––
8.0
–––
ns
V
DD
= 16V,V
GS
= 4.5V
t
r
Rise Time
–––
11
–––
I
D
= 12A
t
d(off)
Turn-Off Delay Time
–––
12
–––
Clamped Inductive Load
t
f
Fall Time
–––
3.3
–––
C
iss
Input Capacitance
––– 1150 –––
pF
V
GS
= 0V
C
oss
Output Capacitance
–––
260
–––
V
DS
= 15V
C
rss
Reverse Transfer Capacitance
–––
120
–––
ƒ = 1.0MHz
Avalanche Characteristics
E
AS
Single Pulse Avalanche Energy 42
mJ
I
AR
Avalanche Current 12
A
E
AR
Repetitive Avalanche Energy 5.0
mJ
Parameter
Max.
Units
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
––– ––– 56
A
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
––– ––– 220
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
–––
–––
1.0
V T
J
= 25°C,I
S
= 12A,V
GS
= 0V
t
rr
Reverse Recovery Time
–––
25
38
ns T
J
= 25°C ,I
F
= 12A, V
DS
= 15V
Q
rr
Reverse Recovery Charge
–––
17
26
nC di/dt = 100A/µs
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
IRFR/U3707ZPbF
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2016-5-31
Fig. 2 Typical Output Characteristics
Fig. 3
Typical Transfer Characteristics
Fig. 4 Normalized On-Resistance
vs. Temperature
Fig. 1 Typical Output Characteristics
0.1
1
10
VDS, Drain-to-Source Voltage (V)
0.001
0.01
0.1
1
10
100
1000
10000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
2.2V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP 10V
6.0V
4.5V
4.0V
3.3V
2.8V
2.5V
BOTTOM
2.2V
0.1
1
10
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
2.2V
20µs PULSE WIDTH
Tj = 175°C
VGS
TOP 10V
6.0V
4.5V
4.0V
3.3V
2.8V
2.5V
BOTTOM
2.2V
0
2
4
6
8
VGS, Gate-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
)
TJ = 25°C
TJ = 175°C
VDS = 10V
20µs PULSE WIDTH
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 30A
VGS = 10V
IRFR/U3707ZPbF
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2016-5-31
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
C
, C
ap
ac
ita
nc
e(
pF
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0
2
4
6
8
10
12
QG Total Gate Charge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 24V
VDS= 15V
ID= 12A
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
VSD, Source-to-Drain Voltage (V)
0.10
1.00
10.00
100.00
1000.00
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
0
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
Tc = 25°C
Tj = 175°C
Single Pulse
IRFR/U3707ZPbF
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2016-5-31
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10. Threshold Voltage vs. Temperature
25
50
75
100
125
150
175
TC , Case Temperature (°C)
0
10
20
30
40
50
60
I D
,
D
ra
in
C
ur
re
nt
(
A
)
Limited By Package
-75 -50 -25
0
25 50 75 100 125 150 175 200
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
V
G
S
(t
h)
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 250µA
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
he
rm
al
Re
sp
on
se
(
Z
th
JC
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W)
i (sec)
1.698
0.000845
0.481
0.016503
0.823
0.000128
J
J
1
1
2
2
3
3
R
1
R
1
R
2
R
2
R
3
R
3
C
C
Ci=
iRi
Ci=
iRi
IRFR/U3707ZPbF
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2016-5-31
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive Waveforms
R G
IAS
0.01
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
tp
V
(BR)DSS
I
AS
Fig 13b. Gate Charge Test Circuit
Fig 13a. Gate Charge Waveform
Fig 14a. Switching Time Test Circuit
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
120
140
160
180
200
E
A
S
,
S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
ID
TOP 3.7A
5.6A
BOTTOM 12A
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 14b. Switching Time Waveforms
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
V
DD
V
DS
L
D
D.U.T
+
-
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
IRFR/U3707ZPbF
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2016-5-31
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
IRFR/U3707ZPbF
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2016-5-31
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Special attention has been given to the power losses in
the switching elements of the circuit - Q1 and Q2. Power
losses in the high side switch Q1, also called the Control
FET, are impacted by the R
ds(on)
of the MOSFET, but
these conduction losses are only about one half of the
total losses.
Power losses in the control switch Q1 are given by;
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
This can be expanded and approximated by;
This simplified loss equation includes the terms Q
gs2
and
Q
oss
which are new to Power MOSFET data sheets.
Q
gs2
is a subelement of traditional gate-source charge
that is included in all MOSFET data sheets. The importance of
splitting this gate-source charge into two sub elements,
Q
gs1
and Q
gs2
, can be seen from Fig 16.
Q
gs2
indicates the charge that must be supplied by the
gate driver between the time that the threshold voltage
has been reached and the time the drain current rises to
Id max at which time the drain voltage begins to change.
Minimizing Q
gs2
is a critical factor in reducing switching
losses in Q1.
Q
oss
is the charge that must be supplied to the output
capacitance of the MOSFET during every switching cycle.
Figure A shows how Q
oss
is formed by the parallel combination
of the voltage dependent (non-linear) capacitance’s C
ds
and C
dg
when multiplied by the power supply input buss
voltage.
P
loss
I
rms
2
R
ds(on)
I
Q
gd
i
g
V
in
f
I
Q
gs2
i
g
V
in
f
Q
g
V
g
f
Q
oss
2
V
in
f
Synchronous FET
The power loss equation for Q2 is approximated by;
*dissipated primarily in Q1
For the synchronous MOSFET Q2, R
ds(on)
is an important
characteristic; however, once again the importance of
gate charge must not be overlooked since it impacts
three critical areas. Under light load the MOSFET must
still be turned on and off by the control I
C
so the gate
drive losses become much more significant. Secondly,
the output charge Q
oss
and reverse recovery charge Q
rr
both generate losses that are transferred to Q1 and in-
crease the dissipation in that device. Thirdly, gate charge
will impact the MOSFETs’ susceptibility to C
dv/dt
turn on.
The drain of Q2 is connected to the switching node of the
converter and therefore sees transitions between ground
and Vin. As Q1 turns on and off there is a rate of change
of drain voltage dV/dt which is capacitive coupled to the
gate of Q2 and can induce a voltage spike on the gate
that is sufficient to turn the MOSFET on, resulting in
shoot-through current . The ratio of Q
gd
/Q
gs1
must be min-
imized to reduce the potential for C
dv/dt
turn on.
Figure A: Q
oss
Characteristic
P
loss
P
conduction
P
drive
P
output
*
P
loss
I
rms
2
R
ds(on)
Q
g
V
g
f
Q
oss
2
V
in
f
Q
rr
V
in
f
IRFR/U3707ZPbF
9
2016-5-31
Note: For the most current drawing please refer to Infineon’s web site
www.infineon.com
D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches))
INTERNATIONAL
ASSEMBLED ON WW 16, 2001
IN THE ASSEMBLY LINE "A"
OR
Note: "P" in assembly line position
EXAMPLE:
LOT CODE 1234
THIS IS AN IRFR120
WITH ASSEMBLY
indicates "Lead-Free"
PRODUCT (OPTIONAL)
P = DESIGNATES LEAD-FREE
A = ASSEMBLY SITE CODE
PART NUMBER
WEEK 16
DATE CODE
YEAR 1 = 2001
RECTIFIER
INTERNATIONAL
LOGO
LOT CODE
ASSEMBLY
34
12
IRFR120
116A
LINE A
34
RECTIFIER
LOGO
IRFR120
12
ASSEMBLY
LOT CODE
YEAR 1 = 2001
DATE CODE
PART NUMBER
WEEK 16
"P" in assembly line position indicates
"Lead-Free" qualification to the consumer-level
P = DESIGNATES LEAD-FREE
PRODUCT QUALIFIED TO THE
CONSUMER LEVEL (OPTIONAL)
IRFR/U3707ZPbF
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2016-5-31
I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
78
LINE A
LOGO
INTERNATIONAL
RECTIFIER
OR
PRODUCT (OPTIONAL)
P = DESIGNATES LEAD-FREE
A = ASSEMBLY SITE CODE
IRFU120
PART NUMBER
WEEK 19
DATE CODE
YEAR 1 = 2001
RECTIFIER
INTERNATIONAL
LOGO
ASSEMBLY
LOT CODE
IRFU120
56
DATE CODE
PART NUMBER
LOT CODE
ASSEMBLY
56
78
YEAR 1 = 2001
WEEK 19
119A
indicates Lead-Free"
ASSEMBLED ON WW 19, 2001
IN THE ASSEMBLY LINE "A"
Note: "P" in assembly line position
EXAMPLE:
WITH ASSEMBLY
THIS IS AN IRFU120
LOT CODE 5678
Note: For the most current drawing please refer to Infineon’s web site
www.infineon.com