IRFP4868PbF
1
2017-06-21
Applications
High Efficiency Synchronous Rectification in SMPS
Uninterruptible Power Supply
High Speed Power Switching
Hard Switched and High Frequency Circuits
Benefits
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free
Gate Drain Source
G D S
V
DSS
300V
R
DS(on)
typ.
25.5m
max.
32m
I
D
70A
Base Part Number
Package Type
Standard Pack
Orderable Part Number
Form Quantity
IRFP4868PbF
TO-247AC
Tube
25 IRFP4868PbF
Absolute Maximum Ratings
Symbol Parameter
Max.
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
70
A
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V
49
I
DM
Pulsed Drain Current 280
P
D
@T
C
= 25°C
Maximum Power Dissipation
517
W
Linear Derating Factor
3.4
W/°C
V
GS
Gate-to-Source Voltage
± 20
V
T
J
Operating Junction and
-55 to + 175
°C
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
Mounting torque, 6-32 or M3 screw
10lbf
in (1.1N
m)
Avalanche Characteristics
E
AS (Thermally limited)
Single Pulse Avalanche Energy 1093
mJ
I
AR
Avalanche Current
See Fig. 14, 15, 22a, 22b
A
E
AR
Repetitive Avalanche Energy mJ
Thermal Resistance
Symbol Parameter Typ.
Max.
Units
R
JC
Junction-to-Case
–––
0.29
R
CS
Case-to-Sink, Flat Greased Surface
0.24 –––
R
JA
Junction-to-Ambient
––– 40
°C/W
TO-247AC
D
G
D
S
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Static @ T
J
= 25°C (unless otherwise specified)
Symbol Parameter
Min.
Typ.
Max.
Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
300 ––– –––
V V
GS
= 0V, I
D
= 250µA
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
––– 0.29 ––– V/°C Reference to 25°C, I
D
= 5mA
R
DS(on)
Static Drain-to-Source On-Resistance
––– 25.5
32
m
V
GS
= 10V, I
D
= 42A
V
GS(th)
Gate Threshold Voltage
3.0
–––
5.0
V V
DS
= V
GS
, I
D
= 250µA
I
DSS
––– ––– 20
µA
V
DS
= 300V, V
GS
= 0V
––– ––– 250
V
DS
= 300V, V
GS
= 0V, T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
––– ––– 100
nA
V
GS
= 20V
Gate-to-Source Reverse Leakage
––– ––– -100
V
GS
= -20V
R
G
Internal Gate Resistance
–––
1.1
–––
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol Parameter
Min.
Typ.
Max.
Units
Conditions
gfs Forward
Transconductance
80
–––
–––
S
V
DS
= 50V, I
D
= 42A
Q
g
Total Gate Charge
––– 180 270
nC
I
D
= 42A
Q
gs
Gate-to-Source Charge
–––
60
–––
V
DS
=150V
Q
gd
Gate-to-Drain ("Miller") Charge
––– 57 –––
V
GS
= 10V
Q
sync
Total Gate Charge Sync. (Q
g
- Q
gd
) –––
123
–––
I
D
= 42A, V
DS
=0V, V
GS
= 10V
t
d(on)
Turn-On Delay Time
–––
24
–––
ns
V
DD
= 195V
t
r
Rise Time
–––
16
–––
I
D
= 42A
t
d(off)
Turn-Off Delay Time
–––
62
–––
R
G
= 1.0
t
f
Fall Time
–––
45
–––
V
GS
= 10V
C
iss
Input Capacitance
––– 10774 –––
pF
V
GS
= 0V
C
oss
Output Capacitance
––– 612 –––
V
DS
= 50V
C
rss
Reverse Transfer Capacitance
––– 193 –––
ƒ = 1.0 MHz, See Fig. 5
C
oss
eff. (ER) Effective Output Capacitance
(Energy Related)
––– 406 –––
V
GS
= 0V, V
DS
= 0V to 240V ,
See Fig. 11
C
oss
eff. (TR) Effective Output Capacitance
(Time Related)
––– 710 –––
V
GS
= 0V, V
DS
= 0V to 240V
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
––– ––– 70
A
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
––– ––– 280 A
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
––– –––
1.3
V T
J
= 25°C, I
S
= 42A, V
GS
= 0V
dv/dt Peak
Diode
Recovery
–––
7.3
–––
V/ns
T
J
= 25°C, I
S
= 42A, V
DS
= 300V
t
rr
Reverse Recovery Time
––– 351 –––
ns
T
J
= 25°C
––– 454 –––
T
J
= 125°C
Q
rr
Reverse Recovery Charge
––– 2520 –––
nC
T
J
= 25°C
––– 3686 –––
T
J
= 125°C
I
RRM
Reverse Recovery Current
–––
16
–––
A T
J
= 25°C
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by
L
S
+L
D
)
Drain-to-Source Leakage Current
Notes:
Repetitive rating; pulse width limited by max. Junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 1.2mH
R
G
= 50
, I
AS
= 42A, V
GS
=10V. Part not
recommended for use above this value.
I
SD
≤ 42A, di/dt ≤ 1706A/µs, V
DD
≤ V
(BR)DSS
, T
J
≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives
the same charging time as Coss while V
DS
is
rising from 0 to 80% V
DSS
.
Coss eff. (ER) is a fixed capacitance that gives
the same energy as Coss while V
DS
is rising
from 0 to 80% V
DSS
.
R
is measured at T
J
approximately 90°C.
R
JC
value shown is at time zero.
D
S
G
V
R
= 255V,
I
F
= 42A
di/dt = 100A/µs
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0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
, D
ra
in
-t
o-
S
o
ur
ce
C
ur
re
nt
(
A
)
4.75V
60µs PULSE WIDTH
Tj = 175°C
VGS
TOP
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM
4.75V
Fig 2. Typical Output Characteristics
3
4
5
6
7
8
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VDS = 50V
60µs PULSE WIDTH
Fig 3.
Typical Transfer Characteristics
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
VGS
TOP
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM
4.75V
60µs PULSE WIDTH
Tj = 25°C
4.75V
Fig 1. Typical Output Characteristics
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 70A
VGS = 10V
Fig 4.
Normalized On-Resistance vs. Temperature
0
30
60
90
120 150 180 210 240
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
o
lta
g
e
(V
)
VDS= 240V
VDS= 150V
VDS= 60V
ID= 42A
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C
, C
ap
a
ci
ta
nc
e
(p
F
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
280
290
300
310
320
330
340
350
360
370
V
(B
R
)D
S
S
,
D
ra
in
-t
o-
S
ou
rc
e
B
re
ak
d
ow
n
V
ol
ta
ge
(
V
)
Id = 5mA
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 175°C
Single Pulse
10msec
1msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
DC
Fig 8. Maximum Safe Operating Area
25
50
75
100
125
150
175
TC , Case Temperature (°C)
0
10
20
30
40
50
60
70
I D
,
D
ra
in
C
ur
re
nt
(
A
)
-50
0
50
100 150 200 250 300 350
VDS, Drain-to-Source Voltage (V)
0.0
5.0
10.0
15.0
20.0
E
ne
rg
y
(µ
J)
Fig 9. Maximum Drain Current vs. Case Temperature
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
1000
2000
3000
4000
5000
E
A
S
,
S
in
gl
e
P
ul
se
A
va
la
n
ch
e
E
n
er
gy
(
m
J)
ID
TOP 11A
20A
BOTTOM 42A
Fig 10. Drain-to-Source Breakdown Voltage
0.0
0.5
1.0
1.5
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
Fig 7. Typical Source-to-Drain Diode
Forward Voltage
Fig 12. Maximum Avalanche Energy vs. Drain Current
Fig 11. Typical Coss Stored Energy
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1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
T
he
rma
l R
es
po
ns
e
(
Z
th
JC
)
°
C
/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
0.1
1
10
100
1000
A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs. Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature
far in excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
16a,
16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 14, 15).
t
av
= Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
T/ Z
thJC
I
av
= 2
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
200
400
600
800
1000
1200
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 42A
Fig 15. Maximum Avalanche Energy vs. Temperature
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0
200
400
600
800
1000
diF /dt (A/µs)
10
20
30
40
50
60
70
I R
R
M
(
A
)
IF = 28A
VR = 255V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/µs)
2000
3000
4000
5000
6000
Q
R
R
(
nC
)
IF = 28A
VR = 255V
TJ = 25°C
TJ = 125°C
Fig. 17 Typical Recovery Current vs. di
f
/dt
0
200
400
600
800
1000
diF /dt (A/µs)
2000
3000
4000
5000
6000
7000
8000
Q
R
R
(
nC
)
IF = 42A
VR = 255V
TJ = 25°C
TJ = 125°C
Fig 18. Typical Recovery Current vs. di
f
/dt
Fig 19. Typical Stored Charge vs. di
f
/dt
-75 -50 -25 0
25 50 75 100 125 150 175
TJ , Temperature ( °C )
0.0
1.0
2.0
3.0
4.0
5.0
6.0
V
G
S
(t
h
),
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 250µA
ID = 1.0mA
ID = 1.0A
0
200
400
600
800
1000
diF /dt (A/µs)
10
20
30
40
50
60
70
80
90
I R
R
M
(
A
)
IF = 42A
VR = 255V
TJ = 25°C
TJ = 125°C
Fig. 16 Threshold Voltage vs. Temperature
Fig 20. Typical Stored Charge vs. di
f
/dt
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Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
IRFP4868PbF
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TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
YEAR 1 = 2001
DATE CODE
PART NUMBER
INTERNATIONAL
LOGO
RECTIFIER
ASSEMBLY
56 57
IRFPE30
135H
LINE H
indicates "Lead-Free"
WEEK 35
LOT CODE
IN THE ASSEMBLY LINE "H"
ASSEMBLED ON WW 35, 2001
Notes: This part marking information applies to devices produced after 02/26/2001
Note: "P" in assembly line position
EXAMPLE:
WITH ASSEMBLY
THIS IS AN IRFPE30
LOT CODE 5657
TO-247AC Part Marking Information
Note: For the most current drawing please refer to website at http://www.irf.com/package/
TO-247 package is not recommended for Surface Mount Application.
IRFP4868PbF
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Qualification information
Qualification level
Industrial
(per JEDEC JESD47F)
†
Moisture Sensitivity Level
TO-247AC
N/A
RoHS compliant
Yes
† Applicable version of JEDEC standard at the time of product release.
Published by
Infineon Technologies AG
81726 München, Germany
©
Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (
www.infineon.com
).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
Revision History
Date Comments
06/21/2017
Changed datasheet with Infineon logo-all pages
Corrected Package outline on page 8.
Added disclaimer on last page.