IRFI7536GPbF
V
DSS
60V
R
DS(on)
typ.
2.7m
I
D
86A
R
DS(on)
max.
3.4m
1
2017-04-27
Absolute Maximum Ratings
Symbol Parameter
Max.
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
86
A
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V
73
I
DM
Pulsed Drain Current 820
P
D
@T
C
= 25°C
Maximum Power Dissipation
75
W
Linear Derating Factor
0.5
W/°C
V
GS
Gate-to-Source Voltage
± 20
V
T
J
Operating Junction and
-55 to + 175
T
STG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds (1.6mm from case)
300
Mounting torque, 6-32 or M3 screw
10 lbf•in (1.1N•m)
G D S
Gate Drain Source
Applications
High Efficiency Synchronous Rectification in SMPS
Uninterruptible Power Supply
High Speed Power Switching
Hard Switched and High Frequency Circuits
HEXFET
®
Power MOSFET
TO-220 Full-Pak
Base Part Number
Package Type
Standard Pack
Orderable Part Number
Form Quantity
IRFI7536GPbF
TO-220 Full-Pak
Tube
50 IRFI7536GPbF
Thermal Resistance
Symbol Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case –––
2.87
R
JA
Junction-to-Ambient (PCB Mount)
–––
65
°C/W
G
D
S
Benefits
Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free
Avalanche Characteristics
E
AS
Single Pulse Avalanche Energy (Thermally Limited) 738 mJ
I
AR
Avalanche Current
A
E
AR
Repetitive Avalanche Energy mJ
See Fig. 14, 15, 22a, 22b
IRFI7536PbF
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2017-04-27
Notes:
Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.26mH, R
G
= 50
, I
AS
= 75A, V
GS
=10V. Part not recommended for use above this value.
I
SD
75A, di/dt 890A/µs, V
DD
V
(BR)DSS
, T
J
175°C.
Pulse width
400µs; duty cycle 2%.
C
oss eff.
(TR) is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss eff.
(ER) is a fixed capacitance that gives the same energy as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
R
is measured at T
J
approximately 90°C.
R
JC
value shown is at time zero.
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter Min.
Typ.
Max.
Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
60
–––
–––
V
V
GS
= 0V, I
D
= 250µA
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
–––
29
––– mV/°C Reference to 25°C, I
D
= 1mA
R
DS(on)
Static Drain-to-Source On-Resistance
–––
2.7
3.4
m
V
GS
= 10V, I
D
= 75A
V
GS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
V
DS
= V
GS
, I
D
= 150µA
R
G
Internal
Gate
Resistance
–––
0.79
–––
I
DSS
Drain-to-Source Leakage Current
––– ––– 20
µA
V
DS
= 60 V, V
GS
= 0V
––– ––– 250
V
DS
= 60V,V
GS
= 0V,T
J
=125°C
I
GSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
V
GS
= 20V
Gate-to-Source Reverse Leakage
–––
––– -100
V
GS
= -20V
gfs
Forward Trans conductance
88
–––
–––
S
V
DS
= 25V, I
D
= 75A
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
––– ––– 86
A
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
––– ––– 820
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
–––
–––
1.3
V T
J
= 25°C,I
S
= 75A,V
GS
= 0V
dv/dt
Peak Diode Recovery dv/dt
–––
3.3
––– V/ns T
J
= 25°C, I
S
= 75A, V
DS
= 60V
t
rr
Reverse Recovery Time
––– 43 –––
ns
T
J
= 25°C
53
–––
T
J
= 125°C
Q
rr
Reverse Recovery Charge
––– 58 –––
nC
T
J
= 25°C
––– 65 –––
T
J
= 125°C
I
RRM
Reverse Recovery Current
–––
2.4
–––
A
T
J
= 25°C
Dynamic @ T
J
= 25°C (unless otherwise specified)
Q
g
Total Gate Charge
–––
130 195
nC
I
D
= 75A
Q
gs
Gate-to-Source Charge
–––
31
–––
V
DS
= 30V
Q
gd
Gate-to-Drain Charge
–––
42
–––
V
GS
= 10V
Q
sync
Total Gate Charge Sync. (Qg - Qgd)
–––
88
–––
t
d(on)
Turn-On Delay Time
–––
22
–––
ns
V
DD
= 39V
t
r
Rise Time
–––
77
–––
I
D
= 75A
t
d(off)
Turn-Off Delay Time
–––
55
–––
R
G
= 2.7
t
f
Fall Time
–––
64
–––
V
GS
= 10V
C
iss
Input Capacitance
––– 6600 –––
pF
V
GS
= 0V
C
oss
Output Capacitance
–––
720 –––
V
DS
= 48V
C
rss
Reverse Transfer Capacitance
–––
400 –––
ƒ = 1.0MHz, See Fig. 5
C
oss eff. (ER)
Effective Output Capacitance (Energy Related) ––– 1080 –––
V
GS
=0V,V
DS
= 0V to 48V See Fig.11
C
oss eff. (TR)
Effective Output Capacitance (Time Related)
––– 1400 –––
V
GS
= 0V, V
DS
= 0V to 48V
V
R
= 51V
I
F
=75A
di/dt= 100A/µs
IRFI7536PbF
3
2017-04-27
Fig. 3
Typical Transfer Characteristics
Fig. 4 Normalized On-Resistance vs. Temperature
Fig. 1 Typical Output Characteristics
0.01
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
, D
ra
in
-t
o
-S
ou
rc
e
C
u
rr
en
t
(A
)
VGS
TOP 15V
12V
10V
6.0V
5.0V
4.75V
4.50V
BOTTOM
4.25V
60µs PULSE WIDTH
Tj = 25°C
4.25V
0.01
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
u
rr
en
t (
A
)
4.25V
60µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
12V
10V
6.0V
5.0V
4.75V
4.50V
BOTTOM
4.25V
Fig. 2 Typical Output Characteristics
2
3
4
5
6
7
VGS, Gate-to-Source Voltage (V)
1.0
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(A
)
TJ = 25°C
TJ = 175°C
VDS = 25V
60µs PULSE WIDTH
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 75A
VGS = 10V
1
10
100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C
, C
ap
ac
ita
nc
e
(p
F
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0
20
40
60
80 100 120 140 160 180
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 48V
VDS= 30V
VDS= 12V
ID= 75A
IRFI7536PbF
4
2017-04-27
Fig 8. Maximum Safe Operating Area
Fig. 7. Typical Source-to-Drain Diode Forward Voltage
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VSD, Source-to-Drain Voltage (V)
1.0
10
100
1000
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
10000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
DC
Fig 10. Drain-to-Source Breakdown Voltage
Fig 12. Maximum Avalanche Energy vs. Drain Current
Fig. 11. Typical C
OSS
Stored Energy
25
50
75
100
125
150
175
TC , Case Temperature (°C)
0
20
40
60
80
100
I D
,
D
ra
in
C
ur
re
nt
(
A
)
Fig. 9. Maximum Drain Current vs. Case Temperature
0
10
20
30
40
50
60
70
VDS, Drain-to-Source Voltage (V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
E
ne
rg
y
(µ
J)
-60 -40 -20 0 20 40 60 80 100 120140160 180
TJ , Temperature ( °C )
60
62
64
66
68
70
72
V
(B
R
)D
S
S
, D
ra
in
-t
o-
S
ou
rc
e
B
re
ak
do
w
n
V
ol
ta
ge
(
V
)
ID = 1.0mA
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
500
1000
1500
2000
2500
3000
E
A
S
,
S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
ID
TOP 8.6A
12A
BOTTOM 75A
IRFI7536PbF
5
2017-04-27
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 15.
Maximum Avalanche Energy vs. Temperature
Fig 14. Single Avalanche Event: Pulse Current vs. Pulse Width
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.infineon.com)
1.Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
T = Allowable rise in junction temperature, not to exceed T
jmax
(assumed as 25°C in Figure 14, 15).
t
av
= Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
T/ Z
thJC
I
av
= 2
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)·
t
av
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
10
T
he
rm
al
R
es
po
ns
e
(
Z
th
JC
)
°
C
/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
tav (sec)
0.1
1
10
100
1000
A
va
la
nc
he
C
ur
re
nt
(
A
)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
700
800
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 75A
IRFI7536PbF
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2017-04-27
Fig 20. Typical Stored Charge vs. dif/dt
Fig 19. Typical Stored Charge vs. dif/dt
Fig 18. Typical Recovery Current vs. dif/dt
Fig 17. Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
-75
-25
25
75
125
175
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
G
S
(t
h)
, G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 150µA
ID = 1.0mA
ID = 1.0A
0
200
400
600
800
1000
diF /dt (A/µs)
2
4
6
8
10
12
14
16
I R
R
M
(
A
)
IF = 30A
VR = 51V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/µs)
2
4
6
8
10
12
14
16
I R
R
M
(
A
)
IF = 45A
VR = 51V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/µs)
0
100
200
300
400
500
Q
R
R
(
nC
)
IF = 30A
VR = 51V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/µs)
0
100
200
300
400
500
Q
R
R
(
nC
)
IF = 45A
VR = 51V
TJ = 25°C
TJ = 125°C
IRFI7536PbF
7
2017-04-27
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET
®
Power MOSFETs
Fig 22a. Unclamped Inductive Test Circuit
Fig 23a. Switching Time Test Circuit
Fig 22b. Unclamped Inductive Waveforms
Fig 23b. Switching Time Waveforms
Fig 24b. Gate Charge Waveform
RG
IAS
0.01
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
tp
V
(BR)DSS
I
AS
Fig 24a. Gate Charge Test Circuit
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
IRFI7536PbF
8
2017-04-27
TO-220 Full-Pak Package Outline (Dimensions are shown in millimeters (inches))
TO-220 Full-Pak Part Marking Information
TO-220AB Full-Pak packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to website at
http://www.irf.com/package/
IRFI7536PbF
9
2017-04-27
Revision History
Date Comments
04/27/2017
Changed datasheet with Infineon logo - all pages.
Corrected Package Outline on page 8.
Corrected Qual level from “TSOP-6” to “TO-220 Full-Pak” on page 9.
Added disclaimer on last page.
Qualification Information
Qualification Level
Industrial
(per JEDEC JESD47F)
†
TO-220 Full-Pak
N/A
RoHS Compliant
Yes
Moisture Sensitivity Level
† Applicable version of JEDEC standard at the time of product release.
Trademarks of Infineon Technologies AG
µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™,
CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™,
GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™,
OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID
FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™
Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2016-04-19
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Email:
erratum@infineon.com
Document reference
ifx1
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
In addition, any information given in this
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customer’s applications.
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intended for technically trained staff. It is the
responsibility of customer’s technical
departments to evaluate the suitability of the
product for the intended application and the
completeness of the product information given in
this document with respect to such application.
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(
www.infineon.com
).
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according to the AEC Q100 or AEC Q101 documents
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Except as otherwise explicitly approved by Infineon
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