IRFHM8342TRPbF
HEXFET
®
Power MOSFET
Base part number
Package Type
Standard Pack
Form
Quantity
IRFHM8342PbF
PQFN 3.3mm x 3.3mm
Tape and Reel
4000
IRFHM8342TRPbF
Orderable Part Number
V
DSS
30
V
R
DS(on)
max
(@ V
GS
= 10V)
16
(@ V
GS
= 4.5V)
25
Qg
(typical)
5.0
nC
I
D
(@T
C (Bottom)
= 25°C)
20 A
m
Features
Benefits
Low Charge (typical 5.2 nC)
Low Switching Losses
Low Thermal Resistance to PCB (<6.2°C/W)
Enable better Thermal Dissipation
Low Profile (<0.9 mm)
results in Increased Power Density
Industry-Standard Pinout
Multi-Vendor Compatibility
Compatible with Existing Surface Mount Techniques
Easier Manufacturing
RoHS Compliant, Halogen-Free
Environmentally Friendlier
MSL1, Consumer Qualification
Increased Reliability
Notes through are on page 10
Absolute Maximum Ratings
Parameter Max.
Units
V
GS
Gate-to-Source Voltage
± 20
V
I
D
@ T
A
= 25°C
Continuous Drain Current, V
GS
@ 10V
10
A
I
D
@ T
C(Bottom)
= 25°C
Continuous Drain Current, V
GS
@ 10V
28
I
D
@ T
C(Bottom)
= 100°C
Continuous Drain Current, V
GS
@ 10V
18
I
DM
Pulsed Drain Current 112
P
D
@T
A
= 25°C
Power Dissipation 2.6
W
P
D
@T
C(Bottom)
= 25°C
Power Dissipation
20
Linear Derating Factor
0.020
W/°C
T
J
Operating Junction and
-55 to + 150
°C
T
STG
Storage Temperature Range
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
(Source Bonding Technology Limited)
20
Applications
Control MOSFET for synchronous buck converter
Load Switch
PQFN 3.3 x 3.3 mm
1
2016-2-23
IRFHM8342TRPbF
2
2016-2-23
D
S
G
Static @ T
J
= 25°C (unless otherwise specified)
Parameter Min.
Typ.
Max.
Units
Conditions
BV
DSS
Drain-to-Source Breakdown Voltage
30
–––
–––
V
V
GS
= 0V, I
D
= 250µA
BV
DSS
/
T
J
Breakdown Voltage Temp. Coefficient
–––
20
––– mV/°C Reference to 25°C, I
D
= 1mA
R
DS(on)
Static Drain-to-Source On-Resistance
–––
13
16
m
V
GS
= 10V, I
D
= 17A
––– 20 25
V
GS
= 4.5V, I
D
= 14A
V
GS(th)
Gate Threshold Voltage
1.35
1.8
2.35
V
V
DS
= V
GS
, I
D
= 25µA
V
GS(th)
Gate Threshold Voltage Coefficient
–––
-5.2
––– mV/°C
I
DSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA V
DS
= 24V, V
GS
= 0V
I
GSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
V
GS
= 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
V
GS
= -20V
gfs Forward
Transconductance
19
–––
–––
S
V
DS
= 10V, I
D
= 17A
Q
g
Total Gate Charge
–––
10
–––
nC V
GS
= 10V, V
DS
= 15V, I
D
= 17A
Q
g
Total Gate Charge
–––
5.0
7.5
V
DS
= 15V
Q
gs
Pre-Vth Gate-to-Source Charge
–––
1.8
–––
nC V
GS
= 4.5V
Q
gd
Gate-to-Drain Charge
–––
1.7
–––
I
D
= 17A
Q
godr
Gate Charge Overdrive
–––
1.5
–––
Q
oss
Output Charge
–––
3.3
–––
nC V
DS
= 16V, V
GS
= 0V
R
G
Gate Resistance
–––
2.6
–––
t
d(on)
Turn-On Delay Time
–––
8.1
–––
V
DD
= 15V, V
GS
= 4.5V
t
r
Rise Time
–––
30
–––
ns I
D
= 17A
t
d(off)
Turn-Off Delay Time
–––
7.6
–––
R
G
=1.8
t
f
Fall Time
–––
5.6
–––
C
iss
Input Capacitance
–––
560
–––
V
GS
= 0V
C
oss
Output Capacitance
–––
102
–––
pF V
DS
= 25V
C
rss
Reverse Transfer Capacitance
–––
48
–––
ƒ = 1.0MHz
Parameter Typ.
Max.
Units
R
JC
(Bottom) Junction-to-Case –––
6.2
R
JC
(Top)
Junction-to-Case –––
50
°C/W
R
JA
Junction-to-Ambient –––
49
R
JA
(<10s)
Junction-to-Ambient –––
34
Thermal Resistance
Diode Characteristics
Parameter
Min.
Typ.
Max. Units
Conditions
I
S
Continuous Source Current
––– ––– 20
A
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
––– ––– 112
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
–––
–––
1.0
V
T
J
= 25°C, I
S
= 17A, V
GS
= 0V
t
rr
Reverse Recovery Time
–––
9.4
14
ns
T
J
= 25°C, I
F
= 17A, V
DD
= 15V
Q
rr
Reverse Recovery Charge
–––
5.8
8.7
nC di/dt = 330A/µs
Avalanche Characteristics
Parameter
Typ.
Max.
Units
E
AS
Single Pulse Avalanche Energy
–––
21
mJ
IRFHM8342TRPbF
3
2016-2-23
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
VGS
TOP
10V
5.0V
4.5V
4.0V
3.5V
3.25V
3.0V
BOTTOM
2.75V
60µs PULSE WIDTH
Tj = 25°C
2.75V
Fig 1. Typical Output Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
1
10
100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
C
, C
ap
a
ci
ta
nc
e
(p
F
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0
2
4
6
8
10
12
14
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
o
lta
g
e
(V
)
VDS= 24V
VDS= 15V
VDS= 6.0V
ID= 17A
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
Fig 3. Typical Transfer Characteristics
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
2.75V
60µs PULSE WIDTH
Tj = 150°C
VGS
TOP
10V
5.0V
4.5V
4.0V
3.5V
3.25V
3.0V
BOTTOM
2.75V
Fig 2. Typical Output Characteristics
1.0
2.0
3.0
4.0
5.0
6.0
7.0
VGS, Gate-to-Source Voltage (V)
1.0
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 150°C
VDS = 10V
60µs PULSE WIDTH
-60 -40 -20 0 20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
e
si
st
an
ce
(
N
o
rm
al
iz
ed
)
ID = 17A
VGS = 10V
IRFHM8342TRPbF
4
2016-2-23
Fig 8. Maximum Safe Operating Area
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 150°C
VGS = 0V
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
he
rma
l R
e
sp
o
ns
e
(
Z
th
JC
)
°C
/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Fig 10. Drain-to-Source Breakdown Voltage
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 150°C
Single Pulse
10msec
1msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
DC
25
50
75
100
125
150
TC , Case Temperature (°C)
0
5
10
15
20
25
30
I D
,
D
ra
in
C
ur
re
nt
(
A
)
Limited by package
-75 -50 -25
0
25
50
75 100 125 150
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
3.0
V
G
S
(t
h
),
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 25µA
ID = 250µA
ID = 1.0mA
ID = 1.0A
IRFHM8342TRPbF
5
2016-2-23
Fig 12. On–Resistance vs. Gate Voltage
Fig 13. Maximum Avalanche Energy vs. Drain Current
Fig 14. Single Avalanche Event: Pulse Current vs. Pulse Width
2
4
6
8
10
12
14
16
18
20
VGS, Gate -to -Source Voltage (V)
10
20
30
40
50
R
D
S
(o
n)
,
D
ra
in
-t
o
-
S
ou
rc
e
O
n
R
e
si
st
an
ce
(
m
)
ID = 17A
TJ = 25°C
TJ = 125°C
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
E
A
S
,
S
in
g
le
P
ul
se
A
va
la
n
ch
e
E
ne
rg
y
(m
J)
ID
TOP 2.8A
5.9A
BOTTOM 17A
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
tav (sec)
0.1
1
10
100
A
va
la
nc
he
C
ur
re
nt
(
A
)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 125°C.
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 125°C and
Tstart =25°C (Single Pulse)
IRFHM8342TRPbF
6
2016-2-23
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET
®
Power MOSFETs
Fig 18. Gate Charge Test Circuit
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 19. Gate Charge Waveform
Fig 17a. Switching Time Test Circuit
Fig 17b. Switching Time Waveforms
Fig 16a. Unclamped Inductive Test Circuit
R G
I
AS
0.01
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
tp
V
(BR)DSS
I
AS
Fig 16b. Unclamped Inductive Waveforms
VDD
IRFHM8342TRPbF
7
2016-2-23
The typical application topology for this product is the synchronous buck converter. These converters operate at high
frequencies (typically around 400 kHz). During turn-on and turn-off switching cycles, the high di/dt currents circulating in
the parasitic elements of the circuit induce high voltage ringing which may exceed the device rating and lead to
undesirable effects. One of the major contributors to the increase in parasitics is the PCB power circuit inductance.
This section introduces a simple guideline that mitigates the effect of these parasitics on the performance of the circuit
and provides reliable operation of the devices.
To reduce high frequency switching noise and the effects of Electromagnetic Interference (EMI) when the control
MOSFET (Q1) is turned on, the layout shown in Figure 20 is recommended. The input bypass capacitors, control
MOSFET and output capacitors are placed in a tight loop to minimize parasitic inductance which in turn lowers the
amplitude of the switch node ringing, and minimizes exposure of the MOSFETs to repetitive avalanche conditions.
Fig 20. Placement and Layout Guidelines
Placement and Layout Guidelines
IRFHM8342TRPbF
8
2016-2-23
For more information on board mounting, including footprint and stencil recommendation, please refer to application note
AN-1136:
http://www.irf.com/technical-info/appnotes/an-1136.pdf
For more information on package inspection techniques, please refer to application note AN-1154:
http://www.irf.com/technical-info/appnotes/an-1154.pdf
PQFN 3.3 x 3.3 Outline “C” Package Details
PQFN 3.3 x 3.3 Outline “G” Package Details
5
8
7
6
#1
3
2
4
#1
2
3
4
8
7
6
5
5
8
7
6
1
3
2
4
1
2
3
4
8
7
6
5
IRFHM8342TRPbF
9
2016-2-23
PQFN 3.3 x 3.3 Tape and Reel
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/
Bo
W
P1
Ao
Ko
CODE
TAPE DIMENSIONS
REEL DIMENSIONS
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Dimension design to accommodate the component width
Dimension design to accommodate the component lenght
Dimension design to accommodate the component thickness
Pitch between successive cavity centers
Overall width of the carrier tape
Bo
W
P1
Ao
Ko
DIMENSION (MM)
CODE
MIN
MAX
DIMENSION (INCH)
MIN
MAX
3.50
3.70
.138
.146
1.10
1.30
7.90
8.10
.043
.051
11.80
12.20
.311
.319
12.30
12.50
.465
.480
.484
.492
3.50
3.70
.138
.146
DESCRIPTION
W1
Qty
4000
Reel Diameter
13 Inches
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/
PQFN 3.3 x 3.3 Part Marking
XXXX
?YWW?
XXXXX
INTERNATIONAL
RECTIFIER LOGO
PART NUMBER
MARKING CODE
(Per Marking Spec)
ASSEMBLY
SITE CODE
(Per SCOP 200-002)
DATE CODE
LOT CODE
(Eng Mode - Min last 4 digits of EATI#)
(Prod Mode - 4 digits of SPN code)
PIN 1
IDENTIFIER
IRFHM8342TRPbF
10
2016-2-23
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 0.15mH, R
G
= 50
, I
AS
= 17A.
Pulse width
400µs; duty cycle 2%.
R
is measured at T
J
of approximately 90°C.
When mounted on 1 inch square PCB (FR-4). Please refer to AN-994 for more details:
http://www.irf.com/technical-info/appnotes/an-994.pdf
Calculated continuous current based on maximum allowable junction temperature.
Current is limited to 20A by source bonding technology.
Qualification Information
†
Qualification Level
Moisture Sensitivity Level
PQFN 3.3mm x 3.3mm
MSL1
(per JEDEC J-STD-020D
††)
RoHS Compliant
Yes
Consumer
(per JEDEC JESD47F
††
guidelines)
† Qualification standards can be found at International Rectifier’s web site:
http://www.irf.com/product-info/reliability
†† Applicable version of JEDEC standard at the time of product release.
IRFHM8342TRPbF
HEXFET
®
Power MOSFET
Base part number
Package Type
Standard Pack
Form
Quantity
IRFHM8342PbF
PQFN 3.3mm x 3.3mm
Tape and Reel
4000
IRFHM8342TRPbF
Orderable Part Number
V
DSS
30
V
R
DS(on)
max
(@ V
GS
= 10V)
16
(@ V
GS
= 4.5V)
25
Qg
(typical)
5.0
nC
I
D
(@T
C (Bottom)
= 25°C)
20 A
m
Features
Benefits
Low Charge (typical 5.2 nC)
Low Switching Losses
Low Thermal Resistance to PCB (<6.2°C/W)
Enable better Thermal Dissipation
Low Profile (<0.9 mm)
results in Increased Power Density
Industry-Standard Pinout
Multi-Vendor Compatibility
Compatible with Existing Surface Mount Techniques
Easier Manufacturing
RoHS Compliant, Halogen-Free
Environmentally Friendlier
MSL1, Consumer Qualification
Increased Reliability
Notes through are on page 10
Absolute Maximum Ratings
Parameter Max.
Units
V
GS
Gate-to-Source Voltage
± 20
V
I
D
@ T
A
= 25°C
Continuous Drain Current, V
GS
@ 10V
10
A
I
D
@ T
C(Bottom)
= 25°C
Continuous Drain Current, V
GS
@ 10V
28
I
D
@ T
C(Bottom)
= 100°C
Continuous Drain Current, V
GS
@ 10V
18
I
DM
Pulsed Drain Current 112
P
D
@T
A
= 25°C
Power Dissipation 2.6
W
P
D
@T
C(Bottom)
= 25°C
Power Dissipation
20
Linear Derating Factor
0.020
W/°C
T
J
Operating Junction and
-55 to + 150
°C
T
STG
Storage Temperature Range
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
(Source Bonding Technology Limited)
20
Applications
Control MOSFET for synchronous buck converter
Load Switch
PQFN 3.3 x 3.3 mm
1
2016-2-23
IRFHM8342TRPbF
2
2016-2-23
D
S
G
Static @ T
J
= 25°C (unless otherwise specified)
Parameter Min.
Typ.
Max.
Units
Conditions
BV
DSS
Drain-to-Source Breakdown Voltage
30
–––
–––
V
V
GS
= 0V, I
D
= 250µA
BV
DSS
/
T
J
Breakdown Voltage Temp. Coefficient
–––
20
––– mV/°C Reference to 25°C, I
D
= 1mA
R
DS(on)
Static Drain-to-Source On-Resistance
–––
13
16
m
V
GS
= 10V, I
D
= 17A
––– 20 25
V
GS
= 4.5V, I
D
= 14A
V
GS(th)
Gate Threshold Voltage
1.35
1.8
2.35
V
V
DS
= V
GS
, I
D
= 25µA
V
GS(th)
Gate Threshold Voltage Coefficient
–––
-5.2
––– mV/°C
I
DSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA V
DS
= 24V, V
GS
= 0V
I
GSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
V
GS
= 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
V
GS
= -20V
gfs Forward
Transconductance
19
–––
–––
S
V
DS
= 10V, I
D
= 17A
Q
g
Total Gate Charge
–––
10
–––
nC V
GS
= 10V, V
DS
= 15V, I
D
= 17A
Q
g
Total Gate Charge
–––
5.0
7.5
V
DS
= 15V
Q
gs
Pre-Vth Gate-to-Source Charge
–––
1.8
–––
nC V
GS
= 4.5V
Q
gd
Gate-to-Drain Charge
–––
1.7
–––
I
D
= 17A
Q
godr
Gate Charge Overdrive
–––
1.5
–––
Q
oss
Output Charge
–––
3.3
–––
nC V
DS
= 16V, V
GS
= 0V
R
G
Gate Resistance
–––
2.6
–––
t
d(on)
Turn-On Delay Time
–––
8.1
–––
V
DD
= 15V, V
GS
= 4.5V
t
r
Rise Time
–––
30
–––
ns I
D
= 17A
t
d(off)
Turn-Off Delay Time
–––
7.6
–––
R
G
=1.8
t
f
Fall Time
–––
5.6
–––
C
iss
Input Capacitance
–––
560
–––
V
GS
= 0V
C
oss
Output Capacitance
–––
102
–––
pF V
DS
= 25V
C
rss
Reverse Transfer Capacitance
–––
48
–––
ƒ = 1.0MHz
Parameter Typ.
Max.
Units
R
JC
(Bottom) Junction-to-Case –––
6.2
R
JC
(Top)
Junction-to-Case –––
50
°C/W
R
JA
Junction-to-Ambient –––
49
R
JA
(<10s)
Junction-to-Ambient –––
34
Thermal Resistance
Diode Characteristics
Parameter
Min.
Typ.
Max. Units
Conditions
I
S
Continuous Source Current
––– ––– 20
A
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
––– ––– 112
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
–––
–––
1.0
V
T
J
= 25°C, I
S
= 17A, V
GS
= 0V
t
rr
Reverse Recovery Time
–––
9.4
14
ns
T
J
= 25°C, I
F
= 17A, V
DD
= 15V
Q
rr
Reverse Recovery Charge
–––
5.8
8.7
nC di/dt = 330A/µs
Avalanche Characteristics
Parameter
Typ.
Max.
Units
E
AS
Single Pulse Avalanche Energy
–––
21
mJ
IRFHM8342TRPbF
3
2016-2-23
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
VGS
TOP
10V
5.0V
4.5V
4.0V
3.5V
3.25V
3.0V
BOTTOM
2.75V
60µs PULSE WIDTH
Tj = 25°C
2.75V
Fig 1. Typical Output Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
1
10
100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
C
, C
ap
a
ci
ta
nc
e
(p
F
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0
2
4
6
8
10
12
14
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
o
lta
g
e
(V
)
VDS= 24V
VDS= 15V
VDS= 6.0V
ID= 17A
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
Fig 3. Typical Transfer Characteristics
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
2.75V
60µs PULSE WIDTH
Tj = 150°C
VGS
TOP
10V
5.0V
4.5V
4.0V
3.5V
3.25V
3.0V
BOTTOM
2.75V
Fig 2. Typical Output Characteristics
1.0
2.0
3.0
4.0
5.0
6.0
7.0
VGS, Gate-to-Source Voltage (V)
1.0
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 150°C
VDS = 10V
60µs PULSE WIDTH
-60 -40 -20 0 20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
e
si
st
an
ce
(
N
o
rm
al
iz
ed
)
ID = 17A
VGS = 10V
IRFHM8342TRPbF
4
2016-2-23
Fig 8. Maximum Safe Operating Area
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 150°C
VGS = 0V
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
he
rma
l R
e
sp
o
ns
e
(
Z
th
JC
)
°C
/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Fig 10. Drain-to-Source Breakdown Voltage
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 150°C
Single Pulse
10msec
1msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
DC
25
50
75
100
125
150
TC , Case Temperature (°C)
0
5
10
15
20
25
30
I D
,
D
ra
in
C
ur
re
nt
(
A
)
Limited by package
-75 -50 -25
0
25
50
75 100 125 150
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
3.0
V
G
S
(t
h
),
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 25µA
ID = 250µA
ID = 1.0mA
ID = 1.0A
IRFHM8342TRPbF
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2016-2-23
Fig 12. On–Resistance vs. Gate Voltage
Fig 13. Maximum Avalanche Energy vs. Drain Current
Fig 14. Single Avalanche Event: Pulse Current vs. Pulse Width
2
4
6
8
10
12
14
16
18
20
VGS, Gate -to -Source Voltage (V)
10
20
30
40
50
R
D
S
(o
n)
,
D
ra
in
-t
o
-
S
ou
rc
e
O
n
R
e
si
st
an
ce
(
m
)
ID = 17A
TJ = 25°C
TJ = 125°C
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
E
A
S
,
S
in
g
le
P
ul
se
A
va
la
n
ch
e
E
ne
rg
y
(m
J)
ID
TOP 2.8A
5.9A
BOTTOM 17A
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
tav (sec)
0.1
1
10
100
A
va
la
nc
he
C
ur
re
nt
(
A
)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 125°C.
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 125°C and
Tstart =25°C (Single Pulse)
IRFHM8342TRPbF
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2016-2-23
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET
®
Power MOSFETs
Fig 18. Gate Charge Test Circuit
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 19. Gate Charge Waveform
Fig 17a. Switching Time Test Circuit
Fig 17b. Switching Time Waveforms
Fig 16a. Unclamped Inductive Test Circuit
R G
I
AS
0.01
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
tp
V
(BR)DSS
I
AS
Fig 16b. Unclamped Inductive Waveforms
VDD
IRFHM8342TRPbF
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2016-2-23
The typical application topology for this product is the synchronous buck converter. These converters operate at high
frequencies (typically around 400 kHz). During turn-on and turn-off switching cycles, the high di/dt currents circulating in
the parasitic elements of the circuit induce high voltage ringing which may exceed the device rating and lead to
undesirable effects. One of the major contributors to the increase in parasitics is the PCB power circuit inductance.
This section introduces a simple guideline that mitigates the effect of these parasitics on the performance of the circuit
and provides reliable operation of the devices.
To reduce high frequency switching noise and the effects of Electromagnetic Interference (EMI) when the control
MOSFET (Q1) is turned on, the layout shown in Figure 20 is recommended. The input bypass capacitors, control
MOSFET and output capacitors are placed in a tight loop to minimize parasitic inductance which in turn lowers the
amplitude of the switch node ringing, and minimizes exposure of the MOSFETs to repetitive avalanche conditions.
Fig 20. Placement and Layout Guidelines
Placement and Layout Guidelines
IRFHM8342TRPbF
8
2016-2-23
For more information on board mounting, including footprint and stencil recommendation, please refer to application note
AN-1136:
http://www.irf.com/technical-info/appnotes/an-1136.pdf
For more information on package inspection techniques, please refer to application note AN-1154:
http://www.irf.com/technical-info/appnotes/an-1154.pdf
PQFN 3.3 x 3.3 Outline “C” Package Details
PQFN 3.3 x 3.3 Outline “G” Package Details
5
8
7
6
#1
3
2
4
#1
2
3
4
8
7
6
5
5
8
7
6
1
3
2
4
1
2
3
4
8
7
6
5
IRFHM8342TRPbF
9
2016-2-23
PQFN 3.3 x 3.3 Tape and Reel
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/
Bo
W
P1
Ao
Ko
CODE
TAPE DIMENSIONS
REEL DIMENSIONS
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Dimension design to accommodate the component width
Dimension design to accommodate the component lenght
Dimension design to accommodate the component thickness
Pitch between successive cavity centers
Overall width of the carrier tape
Bo
W
P1
Ao
Ko
DIMENSION (MM)
CODE
MIN
MAX
DIMENSION (INCH)
MIN
MAX
3.50
3.70
.138
.146
1.10
1.30
7.90
8.10
.043
.051
11.80
12.20
.311
.319
12.30
12.50
.465
.480
.484
.492
3.50
3.70
.138
.146
DESCRIPTION
W1
Qty
4000
Reel Diameter
13 Inches
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/
PQFN 3.3 x 3.3 Part Marking
XXXX
?YWW?
XXXXX
INTERNATIONAL
RECTIFIER LOGO
PART NUMBER
MARKING CODE
(Per Marking Spec)
ASSEMBLY
SITE CODE
(Per SCOP 200-002)
DATE CODE
LOT CODE
(Eng Mode - Min last 4 digits of EATI#)
(Prod Mode - 4 digits of SPN code)
PIN 1
IDENTIFIER
IRFHM8342TRPbF
10
2016-2-23
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 0.15mH, R
G
= 50
, I
AS
= 17A.
Pulse width
400µs; duty cycle 2%.
R
is measured at T
J
of approximately 90°C.
When mounted on 1 inch square PCB (FR-4). Please refer to AN-994 for more details:
http://www.irf.com/technical-info/appnotes/an-994.pdf
Calculated continuous current based on maximum allowable junction temperature.
Current is limited to 20A by source bonding technology.
Qualification Information
†
Qualification Level
Moisture Sensitivity Level
PQFN 3.3mm x 3.3mm
MSL1
(per JEDEC J-STD-020D
††)
RoHS Compliant
Yes
Consumer
(per JEDEC JESD47F
††
guidelines)
† Qualification standards can be found at International Rectifier’s web site:
http://www.irf.com/product-info/reliability
†† Applicable version of JEDEC standard at the time of product release.