HEXFET
®
Power MOSFET
Fig 1. Typical On-Resistance vs. Gate Voltage
Fig 2. Maximum Drain Current vs. Case Temperature
Benefits
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
RoHS Compliant containing no Lead, no Bromide,
and no Halogen
Applications
l
Brushed Motor drive applications
l
BLDC Motor drive applications
l
PWM Inverterized topologies
l
Battery powered circuits
l
Half-bridge and full-bridge topologies
l
Electronic ballast applications
l
Synchronous rectifier applications
l
Resonant mode power supplies
l
OR-ing and redundant power switches
l
DC/DC and AC/DC converters
4
6
8
10
12
14
16
18
20
VGS, Gate -to -Source Voltage (V)
1.0
2.0
3.0
4.0
5.0
6.0
R
D
S
(o
n)
,
D
ra
in
-t
o
-S
ou
rc
e
O
n
R
es
is
ta
nc
e
(m
Ω
)
ID = 50A
TJ = 25°C
TJ = 125°C
PQFN 5X6 mm
www.irf.com
© 2015 International Rectifier
Submit Datasheet Feedback
July 7, 2015
1
IRFH7440PbF
Strong
IR
FET
V
DSS
40V
R
DS(on)
typ.
1.8m
Ω
max.
2.4m
Ω
I
D (Silicon Limited)
159A
c
I
D (Package Limited)
85A
25
50
75
100
125
150
TC , Case Temperature (°C)
0
50
100
150
200
I D
,
D
ra
in
C
ur
re
nt
(
A
)
Limited By Package
Orderable Part Number
Note
Form
Quantity
IRFH7440PBF
PQFN 5mm x 6mm
Tape and Reel
4000
IRFH7440TRPBF
PQFN 5mm x 6mm
Tape and Reel
400
IRFH7440TR2PBF
EOL notice #259
Base Part Number
Package Type
Standard Pack
IRFH7440PbF
www.irf.com
© 2015 International Rectifier
Submit Datasheet Feedback
July 7, 2015
2
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Current is limited to 85A by source bond technology.
Note that current limitations arising from heating of the
device leads may occur with some lead mounting arrangements.
(Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.097mH
R
G
= 50
Ω, I
AS
= 50A, V
GS
=10V.
I
SD
≤ 50A, di/dt ≤ 1126A/μs, V
DD
≤ V
(BR)DSS
, T
J
≤ 150°C.
Pulse width
≤ 400μs; duty cycle ≤ 2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1 inch square 2 oz copper pad on 1.5 x 1.5 in. board of
FR-4 material.
R
θ
is measured at T
J
approximately 90°C.
Limited by T
Jmax
, starting T
J
= 25°C, L = 1mH, R
G
= 50
Ω, I
AS
= 22A,
V
GS
=10V.
Absolute Maximum Ratings
Symbol
Parameter
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Package Limited)
I
DM
Pulsed Drain Current
d
P
D
@T
C
= 25°C
Maximum Power Dissipation
W
Linear Derating Factor
W/°C
V
GS
Gate-to-Source Voltage
V
dv/dt
Peak Diode Recovery
f
V/ns
T
J
Operating Junction and
T
STG
Storage Temperature Range
Avalanche Characteristics
E
AS (Thermally limited)
Single Pulse Avalanche Energy
e
mJ
E
AS (Thermally limited)
Single Pulse Avalanche Energy
l
I
AR
Avalanche Current
d
A
E
AR
Repetitive Avalanche Energy
d
mJ
Thermal Resistance
Symbol
Parameter
Typ.
Max.
Units
R
θJC
(Bottom)
Junction-to-Case
k
–––
1.2
R
θJC
(Top)
Junction-to-Case
k
–––
31
R
θJA
Junction-to-Ambient
j
–––
35
R
θJA
(<10s)
Junction-to-Ambient
j
–––
22
°C/W
A
°C
121
See Fig. 14, 15, 22a, 22b
104
3.0
Max.
159
c
101
c
624
85
232
-55 to + 150
± 20
0.83
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage
40
–––
–––
V
ΔV
(BR)DSS
/ΔT
J
Breakdown Voltage Temp. Coefficient
–––
0.031
–––
V/°C
R
DS(on)
Static Drain-to-Source On-Resistance
–––
1.8
2.4
mΩ
–––
2.7
–––
mΩ
V
GS(th)
Gate Threshold Voltage
2.2
–––
3.9
V
I
DSS
Drain-to-Source Leakage Current
–––
–––
1.0
μA
–––
–––
150
I
GSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
Gate-to-Source Reverse Leakage
–––
–––
-100
R
G
Internal Gate Resistance
–––
2.6
–––
Ω
Conditions
V
GS
= 0V, I
D
= 250μA
Reference to 25°C, I
D
= 1.0mA
d
V
GS
= 10V, I
D
= 50A
g
V
DS
= V
GS
, I
D
= 100μA
V
GS
= 20V
V
GS
= -20V
V
DS
= 40V, V
GS
= 0V
V
DS
= 40V, V
GS
= 0V, T
J
= 125°C
V
GS
= 6.0V, I
D
= 25A
g
IRFH7440PbF
www.irf.com
© 2015 International Rectifier
Submit Datasheet Feedback
July 7, 2015
3
S
D
G
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Units
gfs
Forward Transconductance
149
–––
–––
S
Q
g
Total Gate Charge
–––
92
138
nC
Q
gs
Gate-to-Source Charge
–––
22
–––
Q
gd
Gate-to-Drain ("Miller") Charge
–––
29
–––
Q
sync
Total Gate Charge Sync. (Q
g
- Q
gd
)
–––
63
–––
t
d(on)
Turn-On Delay Time
–––
12
–––
ns
t
r
Rise Time
–––
45
–––
t
d(off)
Turn-Off Delay Time
–––
53
–––
t
f
Fall Time
–––
42
–––
C
iss
Input Capacitance
–––
4574
–––
pF
C
oss
Output Capacitance
–––
700
–––
C
rss
Reverse Transfer Capacitance
–––
466
–––
C
oss
eff. (ER)
Effective Output Capacitance (Energy Related)
–––
863
–––
C
oss
eff. (TR)
Effective Output Capacitance (Time Related)
–––
1229
–––
Diode Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Units
I
S
Continuous Source Current
–––
–––
85
c
A
(Body Diode)
I
SM
Pulsed Source Current
–––
–––
745
A
(Body Diode)
d
V
SD
Diode Forward Voltage
–––
0.9
1.3
V
t
rr
Reverse Recovery Time
–––
25
–––
ns
T
J
= 25°C
V
R
= 34V,
–––
27
–––
T
J
= 125°C
I
F
= 50A
Q
rr
Reverse Recovery Charge
–––
16
–––
nC
T
J
= 25°C
di/dt = 100A/μs
g
–––
17
–––
T
J
= 125°C
I
RRM
Reverse Recovery Current
–––
1.2
–––
A
T
J
= 25°C
I
D
= 30A
R
G
= 2.7Ω
V
GS
= 10V
g
V
DD
= 20V
Conditions
V
DS
= 10V, I
D
= 50A
V
DS
=20V
I
D
= 50A
T
J
= 25°C, I
S
= 50A, V
GS
= 0V
g
integral reverse
p-n junction diode.
MOSFET symbol
showing the
Conditions
V
GS
= 10V
g
V
GS
= 0V
V
DS
= 25V
ƒ = 1.0 MHz
V
GS
= 0V, V
DS
= 0V to 32V
i
V
GS
= 0V, V
DS
= 0V to 32V
h
IRFH7440PbF
www.irf.com
© 2015 International Rectifier
Submit Datasheet Feedback
July 7, 2015
4
Fig 3. Typical Output Characteristics
Fig 5. Typical Transfer Characteristics
Fig 6. Normalized On-Resistance vs. Temperature
Fig 4. Typical Output Characteristics
Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
≤60μs PULSE WIDTH
Tj = 25°C
4.5V
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
4.5V
≤60μs PULSE WIDTH
Tj = 150°C
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
3
4
5
6
7
8
9
VGS, Gate-to-Source Voltage (V)
1.0
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 150°C
VDS = 10V
≤60μs PULSE WIDTH
-60 -40 -20 0 20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 50A
VGS = 10V
1
10
100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C
, C
ap
ac
ita
nc
e
(p
F
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0
20
40
60
80
100
120
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 32V
VDS= 20V
ID= 50A
IRFH7440PbF
www.irf.com
© 2015 International Rectifier
Submit Datasheet Feedback
July 7, 2015
5
Fig 10. Maximum Safe Operating Area
Fig 11. Drain-to-Source Breakdown Voltage
Fig 9. Typical Source-Drain Diode
Forward Voltage
Fig 12. Typical C
OSS
Stored Energy
Fig 13. Typical On-Resistance vs. Drain Current
-60 -40 -20 0 20 40 60 80 100 120 140 160
TJ , Temperature ( °C )
40
42
44
46
48
50
V
(B
R
)D
S
S
, D
ra
in
-t
o-
S
ou
rc
e
B
re
ak
do
w
n
V
ol
ta
ge
(
V
)
Id = 1.0mA
-5
0
5
10
15
20
25
30
35
40
VDS, Drain-to-Source Voltage (V)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
E
ne
rg
y
(μ
J)
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
10000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 150°C
Single Pulse
10msec
1msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100μsec
DC
Limited by
package
0.0
0.5
1.0
1.5
2.0
2.5
VSD, Source-to-Drain Voltage (V)
1.0
10
100
1000
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 150°C
VGS = 0V
0
100
200
300
400
500
ID, Drain Current (A)
0
10
20
30
40
R
D
S
(o
n)
,
D
ra
in
-t
o
-S
ou
rc
e
O
n
R
es
is
ta
nc
e
(m
Ω
)
VGS = 5.0V
VGS = 6.0V
VGS = 7.0V
VGS = 8.0V
VGS =10V
IRFH7440PbF
www.irf.com
© 2015 International Rectifier
Submit Datasheet Feedback
July 7, 2015
6
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 15. Typical Avalanche Current vs.Pulsewidth
Fig 16. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
ΔT
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/ Z
thJC
I
av
=
2
DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
he
rm
al
R
es
po
ns
e
(
Z
th
JC
)
°
C
/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
120
140
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 50A
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
0.1
1
10
100
A
va
la
nc
he
C
ur
re
nt
(
A
)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔΤ j = 25°C and
Tstart = 125°C.
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔTj = 125°C and
Tstart =25°C (Single Pulse)
IRFH7440PbF
www.irf.com
© 2015 International Rectifier
Submit Datasheet Feedback
July 7, 2015
7
Fig. 18 - Typical Recovery Current vs. di
f
/dt
Fig 17. Threshold Voltage vs. Temperature
Fig. 20 - Typical Stored Charge vs. di
f
/dt
Fig. 19 - Typical Recovery Current vs. di
f
/dt
Fig. 21 - Typical Stored Charge vs. di
f
/dt
-75 -50 -25
0
25
50
75 100 125 150
TJ , Temperature ( °C )
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V
G
S
(t
h)
, G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 100μA
ID = 1.0mA
ID = 1.0A
0
200
400
600
800
1000
diF /dt (A/μs)
0
2
4
6
8
10
I R
R
M
(
A
)
IF = 30A
VR = 34V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/μs)
0
50
100
150
200
Q
R
R
(
nC
)
IF = 50A
VR = 34V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/μs)
0
50
100
150
200
Q
R
R
(
nC
)
IF = 30A
VR = 34V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/μs)
0
2
4
6
8
10
I R
R
M
(
A
)
IF = 50A
VR = 34V
TJ = 25°C
TJ = 125°C
IRFH7440PbF
www.irf.com
© 2015 International Rectifier
Submit Datasheet Feedback
July 7, 2015
8
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
RG
IAS
0.01
Ω
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
V
GS
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 22.
Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
μF
50K
Ω
.2
μF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
V
DS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
V
GS
IRFH7440PbF
www.irf.com
© 2015 International Rectifier
Submit Datasheet Feedback
July 7, 2015
9
Note: For the most current drawing please refer to IR website at:
http://www.irf.com/package/
For more information on board mounting, including footprint and stencil recommendation, please refer to application note
AN-1136:
http://www.irf.com/technical-info/appnotes/an-1136.pdf
For more information on package inspection techniques, please refer to application note AN-1154:
http://www.irf.com/technical-info/appnotes/an-1154.pdf
PQFN 5x6 Outline "E" Package Details
PQFN 5x6 Outline "G" Package Details
IRFH7440PbF
www.irf.com
© 2015 International Rectifier
Submit Datasheet Feedback
July 7, 2015
10
PQFN 5x6 Tape and Reel
Note: For the most current drawing please refer to IR website at:
http://www.irf.com/package/
Bo
W
P 1
Ao
Ko
CODE
TAPE DIMENSIONS
REEL DIMENSIONS
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Dimension design to accommodate the component width
Dimension design to accommodate the component lenght
Dimension design to accommodate the component thickness
Pitch between successive cavity centers
Overall width of the carrier tape
DESCRIPTION
Type
Package
5 X 6 PQFN
Note: All dimension are nominal
Diameter
Reel
QTY
Width
Reel
(mm)
Ao
(mm)
Bo
(mm)
Ko
(mm)
P1
(mm)
W
Quadrant
Pin 1
(Inch)
W1
(mm)
13
4000
12.4
6.300
5.300
1.20
8.00
12
Q1
PQFN 5x6 Part Marking
XXXX
XYWWX
XXXXX
INTERNATIONAL
RECTIFIER LOGO
PART NUMBER
(“4 or 5 digits”)
MARKING CODE
(Per Marking Spec)
ASSEMBLY
SITE CODE
(Per SCOP 200-002)
DATE CODE
PIN 1
IDENTIFIER
LOT CODE
(Eng Mode - Min last 4 digits of EATI#)
(Prod Mode - 4 digits of SPN code)