IRFH7110PbF Product Datasheet

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HEXFET

®

 Power MOSFET

Notes

  through 

‡

 are on page 9

Features and Benefits

PQFN 5X6 mm

Applications

•  

Secondary Side Synchronous Rectification

•  

Inverters for DC Motors

• 

 

DC-DC Brick Applications

• 

 

Boost Converters

Features

Benefits

Low RDSon (< 13.5mW)

Lower Conduction Losses

Low Thermal Resistance to PCB (< 1.2°C/W)

Enables better thermal dissipation

Low Profile (<0.9 mm)        

results in Increased Power Density

Industry-Standard Pinout    

Multi-Vendor Compatibility

Compatible with Existing Surface Mount Techniques                          

Easier Manufacturing

RoHS Compliant Containing no Lead, no Bromide and no Halogen    

Environmentally Friendlier

MSL1, Industrial Qualification  

Increased Reliability

V

DS                          

100

V

V

gs  max      

 ± 20

V

R

DS(on) max 

(@V

GS

 = 10V)

13.5

m

Ω

Q

G (typical)

58

nC

R

G (typical)

0.6

Ω

I

(@T

c(Bottom)

 = 25°C)

50i

A

Absolute Maximum Ratings

Parameter

Units

V

DS

Drain-to-Source Voltage

V

GS

Gate-to-Source Voltage

I

D

 @ T

A

 = 25°C

Continuous Drain Current, V

GS

 @ 10V

I

D

 @ T

A

 = 70°C

Continuous Drain Current, V

GS

 @ 10V

I

D

 @ T

C(Bottom)

 = 25°C

Continuous Drain Current, V

GS

 @ 10V

I

D

 @ T

C(Bottom)

 = 100°C

Continuous Drain Current, V

GS

 @ 10V 

I

D

 @ T

C

 = 25°C

Continuous Drain Current, V

GS

 @ 10V (Package Limited)

I

DM

Pulsed Drain Current 

c

P

D

 @T

A

 = 25°C

Power Dissipation 

g

P

D

 @T

C(Bottom)

 = 25°C

Power Dissipation 

g

Linear Derating Factor 

g

W/°C

T

Operating Junction and

T

STG

Storage Temperature Range

-55  to + 150

3.6

0.029

104

Max.

11

37

h

240

 ± 20

100

8.6

58

hi

50

i

V

W

A

°C

IRFH7110PbF

1

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Form

Quantity

IRFH7110TRPBF

PQFN 5mm x 6mm

Tape and Reel

4000

IRFH7110TR2PBF

PQFN 5mm x 6mm

Tape and Reel

400

EOL notice # 259

Orderable part number

Package Type

Standard Pack

Note

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IRFH7110PbF

S

D

G

Thermal Resistance

Parameter

Typ.

Max.

Units

R

θJC

 (Bottom)

Junction-to-Case 

f

–––

1.2

R

θJC

 (Top)

Junction-to-Case 

f

–––

32

°C/W

R

θJA 

Junction-to-Ambient 

fg

–––

35

R

θJA

 (<10s)

Junction-to-Ambient 

g

–––

22

Static @ T

J

 = 25°C (unless otherwise specified)

Parameter

Min. Typ. Max. Units

BV

DSS

Drain-to-Source Breakdown Voltage

100

–––

–––

V

ΔΒV

DSS

/

ΔT

Breakdown Voltage Temp. Coefficient

–––

0.09

–––

V/°C

R

DS(on)

Static Drain-to-Source On-Resistance

–––

10.6

13.5

m

Ω

V

GS(th)

Gate Threshold Voltage

2.0

3.0

4.0

V

ΔV

GS(th)

Gate Threshold Voltage Coefficient

–––

-9.0

–––

mV/°C

I

DSS

Drain-to-Source Leakage Current

–––

–––

20

–––

–––

250

I

GSS

Gate-to-Source Forward Leakage

–––

–––

100

Gate-to-Source Reverse Leakage

–––

–––

-100

gfs

Forward Transconductance

74

–––

–––

S

Q

g

Total Gate Charge 

–––

58

87

Q

gs1

Pre-Vth Gate-to-Source Charge

–––

11

–––

Q

gs2

Post-Vth Gate-to-Source Charge

–––

3.6

–––

Q

gd

Gate-to-Drain Charge

–––

16

–––

Q

godr

Gate Charge Overdrive

–––

27.4

–––

Q

sw

Switch Charge (Q

gs2

 + Q

gd

)

–––

19.6

–––

Q

oss

Output Charge

–––

17

–––

nC

R

G

Gate Resistance

–––

0.6

–––

Ω

t

d(on)

Turn-On Delay Time

–––

11

–––

t

r

Rise Time

–––

23

–––

t

d(off)

Turn-Off Delay Time

–––

22

–––

t

f

Fall Time

–––

18

–––

C

iss

Input Capacitance

–––

3240

–––

C

oss

Output Capacitance

–––

300

–––

C

rss

Reverse Transfer Capacitance

–––

140

–––

Avalanche Characteristics

Parameter

Units

E

AS

Single Pulse Avalanche Energy 

d

mJ

I

AR

Avalanche Current 

c

A

Diode Characteristics

        Parameter

Min. Typ. Max. Units

I

S

Continuous Source Current 
(Body Diode)

I

SM

Pulsed Source Current
(Body Diode)

c

V

SD

Diode Forward Voltage

–––

–––

1.3

V

t

rr

Reverse Recovery Time

–––

27

41

ns

Q

rr

Reverse Recovery Charge

–––

140

210

nC

t

on

Forward Turn-On Time

Time is dominated by parasitic Inductance

MOSFET symbol

nA

ns

A

pF

nC

V

DS

 = 50V

–––

V

GS

 = 20V

V

GS

 = -20V

Conditions

V

GS

 = 0V, I

D

 = 250μA

Reference to 25°C, I

D

 = 1.0mA 

V

GS

 = 10V, I

D

 = 35A 

e

–––

–––

240

–––

–––

50

i

Conditions

Max.

110

35

ƒ = 1.0MHz

T

J

 = 25°C, I

F

 = 35A, V

DD

 = 50V

di/dt = 500A/μs 

e

T

J

 = 25°C, I

S

 = 35A, V

GS

 = 0V 

e

showing  the
integral reverse
p-n junction diode.

Typ.

–––

R

G

=1.8

Ω

V

DS

 = 50V, I

D

 = 35A

I

D

 = 35A

I

D

 = 35A

V

GS

 = 0V

V

DS

 = 25V

V

DS

 = 16V, V

GS

 = 0V

V

DD

 = 50V, V

GS

 = 10V

V

DS

 = V

GS

, I

D

 = 100μA

μA

V

GS

 = 10V 

V

DS

 = 100V, V

GS

 = 0V, T

J

 = 125°C

V

DS

 = 100V, V

GS

 = 0V

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IRFH7110PbF

Fig 4.  Normalized On-Resistance vs. Temperature

Fig 2.  Typical Output Characteristics

Fig 1.  Typical Output Characteristics

Fig 3.  Typical Transfer Characteristics

Fig 6.  Typical Gate Charge vs. Gate-to-Source Voltage

Fig 5.  Typical Capacitance vs. Drain-to-Source Voltage

-60 -40 -20

0

20 40 60 80 100 120 140 160

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

2.5

R

D

S

(o

n)

 , 

D

ra

in

-t

o-

S

ou

rc

O

R

es

is

ta

nc

   

   

   

   

   

   

   

 (

N

or

m

al

iz

ed

)

ID = 35A

VGS = 10V

1

10

100

VDS, Drain-to-Source Voltage (V)

10

100

1000

10000

100000

C

, C

ap

ac

ita

nc

(p

F

)

Coss

Crss

Ciss

VGS   = 0V,       f = 1 MHZ

Ciss   = Cgs + Cgd,  Cds SHORTED
Crss   = Cgd 
Coss  = Cds + Cgd

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.1

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

≤ 60μs PULSE WIDTH

Tj = 25°C

4.0V

VGS

TOP          

10V

6.0V

5.5V

5.0V

4.8V

4.5V

4.3V

BOTTOM

4.0V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

≤ 60μs PULSE WIDTH

Tj = 150°C

4.0V

VGS

TOP          

10V

6.0V

5.5V

5.0V

4.8V

4.5V

4.3V

BOTTOM

4.0V

2.0

3.0

4.0

5.0

6.0

7.0

VGS, Gate-to-Source Voltage (V)

0.1

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

VDS = 50V
≤ 60μs PULSE WIDTH

TJ = 25°C

TJ = 150°C

0

20

40

60

80

 QG  Total Gate Charge (nC)

0

4

8

12

16

V

G

S

, G

at

e-

to

-S

ou

rc

V

ol

ta

ge

 (

V

)

VDS= 80V

VDS= 50V

VDS= 20V

ID= 35A

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IRFH7110PbF

Fig 11.  Maximum Effective Transient Thermal Impedance, Junction-to-Case (Bottom)

Fig 8.  Maximum Safe Operating Area

Fig 9.  Maximum Drain Current vs.

Case (Bottom) Temperature

Fig 7.  Typical Source-Drain Diode Forward Voltage

Fig 10.  Threshold Voltage vs. Temperature

0.2

0.4

0.6

0.8

1.0

1.2

VSD, Source-to-Drain Voltage (V)

0.1

1

10

100

1000

I S

D

, R

ev

er

se

 D

ra

in

 C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 150°C

VGS = 0V

25

50

75

100

125

150

 TC,  Case Temperature (°C)

0

10

20

30

40

50

60

I D

,  

D

ra

in

 C

ur

re

nt

 (

A

)

LIMITED BY PACKAGE

-75

-50

-25

0

25

50

75

100 125 150

TJ , Temperature ( °C )

1.5

2.0

2.5

3.0

3.5

4.0

4.5

V

G

S

(t

h)

 G

at

th

re

sh

ol

V

ol

ta

ge

 (

V

)

ID = 100μA

ID = 250μA

ID = 1.0mA

ID = 1.0A

1E-006

1E-005

0.0001

0.001

0.01

0.1

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

1

10

T

he

rm

al

 R

es

po

ns

Z  

th

JC

 )

 °

C

/W

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

0.1

1

10

100

1000

VDS, Drain-to-Source Voltage (V)

0.1

1

10

100

1000

I D

,  

D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

Tc = 25°C

Tj = 150°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA 
LIMITED BY RDS(on)

100μsec

DC

L

imited by Package

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IRFH7110PbF

Fig 13.  Maximum Avalanche Energy vs. Drain Current

Fig 12. On-Resistance vs. Gate Voltage

Fig 14b.  Unclamped Inductive Waveforms

Fig 14a.  Unclamped Inductive Test Circuit

tp

V

(BR)DSS

I

AS

RG

IAS

0.01

Ω

tp

D.U.T

L

VDS

+

- VDD

DRIVER

A

15V

20V

Fig 15a.  Switching Time Test Circuit

Fig 15b.  Switching Time Waveforms

V

GS

V

DS

90%

10%

t

d(on)

t

d(off)

t

r

t

f

V

DS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1

R

D

V

GS

R

G

D.U.T.

10V

+

-

V

DD

V

GS

4

8

12

16

20

VGS, Gate-to-Source Voltage (V)

0

10

20

30

40

R

D

S

(o

n)

,  

D

ra

in

-t

-S

ou

rc

O

R

es

is

ta

nc

(m

Ω

)

TJ = 25°C

TJ = 125°C

ID = 35A

25

50

75

100

125

150

Starting TJ, Junction Temperature (°C)

0

100

200

300

400

500

E

A

S

S

in

gl

P

ul

se

 A

va

la

nc

he

 E

ne

rg

(m

J)

                 I D

TOP  

       4.7A

               9.6A

BOTTOM 

  35A

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IRFH7110PbF

Fig 16. 

Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET

®

 Power MOSFETs

Fig 17.  Gate Charge Test Circuit

Fig 18.   Gate Charge Waveform

Vds

Vgs

Id

Vgs(th)

Qgs1 Qgs2

Qgd

Qgodr

Circuit Layout Considerations

   •  Low Stray Inductance

   •  Ground Plane

   •  Low Leakage Inductance

      Current Transformer

P.W.

Period

di/dt

Diode Recovery

dv/dt

Ripple 

≤ 5%

Body Diode  Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

V

GS

=10V

V

DD

I

SD

Driver Gate Drive

D.U.T. I

SD

Waveform

D.U.T. V

DS

Waveform

Inductor Curent

D = 

P.W.

Period

*

 V

GS

 = 5V for Logic Level Devices

*

+

-

+

+

+

-

-

-

ƒ

„

‚

R

G

V

DD

•  dv/dt controlled by R

G

•  Driver same type as D.U.T.

•  I

SD

 controlled by Duty Factor "D"

•  D.U.T. - Device Under Test

D.U.T



1K

VCC

DUT

0

L

S

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IRFH7110PbF

PQFN 5x6 Outline "E" Package Details

Note: For the most current drawing please refer to IR website at:

 http://www.irf.com/package/

For more information on board mounting, including footprint and stencil recommendation, please refer to application note AN-1136: 

http://www.irf.com/technical-info/appnotes/an-1136.pdf

For more information on package inspection techniques, please refer to application note AN-1154:

http://www.irf.com/technical-info/appnotes/an-1154.pdf

PQFN 5x6 Outline "G" Package Details

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IRFH7110PbF

PQFN 5x6 Outline Tape and Reel

Note: For the most current drawing please refer to IR website at:

 http://www.irf.com/package/

Bo

W

P 1

Ao

Ko

CODE

TAPE DIMENSIONS

REEL DIMENSIONS

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE 

Dimension design to accommodate the component width
Dimension design to accommodate the component lenght
Dimension design to accommodate the component thickness

Pitch between successive cavity centers

Overall width of the carrier tape

DESCRIPTION

Type

Package

5 X 6 PQFN

Note:  All dimension are nominal

Diameter

Reel

QTY

Width

Reel

(mm)

Ao

(mm)

Bo

(mm)

Ko

(mm)

P1

(mm)

W

Quadrant

Pin 1

(Inch)

W1

(mm)

13

4000

12.4

6.300

5.300

1.20

8.00

12

Q1

XXXX

XYWWX

XXXXX

INTERNATIONAL

RECTIFIER LOGO

PART NUMBER

(“4 or 5 digits”)

MARKING CODE

(Per Marking Spec)

ASSEMBLY
SITE CODE

(Per SCOP 200-002)

DATE CODE

PIN 1

IDENTIFIER

LOT CODE

(Eng Mode - Min last 4 digits of EATI#)

(Prod Mode - 4 digits of SPN code)

PQFN 5x6 Outline Part Marking

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IRFH7110PbF

†

        Qualification standards can be found at International Rectifier’s web site

          http://www.irf.com/product-info/reliability

††

      Higher qualification ratings may be available should the user have such requirements.

            Please contact your International Rectifier sales representative for further information:

           http://www.irf.com/whoto-call/salesrep/

†††

 

 Applicable version of JEDEC standard at the time of product release.

Notes:



 Repetitive rating;  pulse width limited by max. junction temperature.

‚

  Starting T

= 25°C, L = 0.174mH, R

= 50

Ω, I

AS 

= 35A.

ƒ

 Pulse width ≤ 400μs; duty cycle ≤ 2%.

„

 R

θ 

is measured at 

T

J

 of approximately 90°C.

…

 

When mounted on 1 inch square  2 oz copper pad on 1.5x1.5 in. board of FR-4 material.

†

 Calculated continuous current based on maximum allowable junction temperature.

‡ Package is limited to 50A by die-source to lead-frame bonding technology

MS L1

(per JEDE C J-S T D-020D

††† 

)

RoHS compliant

Yes

PQFN 5mm x 6mm

Qualification information

Moisture Sensitivity Level

Qualification level

Industrial

††

(per JE DE C JE S D47F

 ††† 

guidelines )

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA

To contact International Rectifier, please visit 

http://www.irf.com/whoto-call/

Revision History

Date

Comment

• Updated ordering information to reflect the End-Of-life (EOL) of the mini-reel option  (EOL notice #259)
• Updated Package outline on page 7.
• Updated Tape and Reel on page 8.
• Updated data sheet based on corporate template.
• Corrected typo test condition for GFS from "25V" to "50V" on page 2.

• Updated package outline for “option E” and  added package outline for “option G” on page 7 

• Updated "IFX" logo on page 1 & 9.
• Updated tape and reel on page 8.

5/13/2014

6/2/2015

Maker
Infineon Technologies