Benefits
l
Improved Gate, Avalanche and Dynamic dv/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead Free
l
RoHS Compliant, Halogen-Free
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
A
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
I
DM
Pulsed Drain Current
d
P
D
@T
C
= 25°C
Maximum Power Dissipation
W
Linear Derating Factor
W/°C
V
GS
Gate-to-Source Voltage
V
dv/dt
Peak Diode Recovery
f
V/ns
T
J
Operating Junction and
°C
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
E
AS (Thermally limited)
Single Pulse Avalanche Energy
e
mJ
I
AR
Avalanche Current
d
A
E
AR
Repetitive Avalanche Energy
g
mJ
Thermal Resistance
Symbol
Parameter
Typ.
Max.
Units
R
θJC
Junction-to-Case
k
–––
0.402
R
θCS
Case-to-Sink, Flat Greased Surface
0.50
–––
°C/W
R
θJA
Junction-to-Ambient
j
–––
62
300
Max.
180
c
130
c
670
120
190
See Fig. 14, 15, 22a, 22b
370
5.3
-55 to + 175
± 20
2.5
10lb
xin (1.1Nxm)
IRFB4110PbF
S
D
G
TO-220AB
D
S
D
G
Form
Quantity
IRFB4110PbF
TO-220
Tube
50
IRFB4110PbF
Base Part Number
Package Type
Standard Pack
Orderable Part Number
1
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V
DSS
100V
R
DS(on)
typ.
3.7m
Ω
max.
4.5m
Ω
I
D (Silicon Limited)
180A c
I
D (Package Limited)
120A
IRFB4110PbF
2
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Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.033mH
R
G
= 25
Ω, I
AS
= 108A, V
GS
=10V. Part not recommended for use
above this value.
S
D
G
I
SD
≤ 75A, di/dt ≤ 630A/µs, V
DD
≤ V
(BR)DSS
, T
J
≤ 175°C.
Pulse width
≤ 400µs; duty cycle ≤ 2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage
100
–––
–––
V
∆V
(BR)DSS
/
∆T
J
Breakdown Voltage Temp. Coefficient
––– 0.108 –––
V/°C
R
DS(on)
Static Drain-to-Source On-Resistance
–––
3.7
4.5
m
Ω
V
GS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
I
DSS
Drain-to-Source Leakage Current
–––
–––
20
µA
–––
–––
250
I
GSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
Gate-to-Source Reverse Leakage
–––
–––
-100
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
gfs
Forward Transconductance
160
–––
–––
S
Q
g
Total Gate Charge
–––
150
210
nC
Q
gs
Gate-to-Source Charge
–––
35
–––
Q
gd
Gate-to-Drain ("Miller") Charge
–––
43
–––
R
G
Gate Resistance
–––
1.3
–––
Ω
t
d(on)
Turn-On Delay Time
–––
25
–––
ns
t
r
Rise Time
–––
67
–––
t
d(off)
Turn-Off Delay Time
–––
78
–––
t
f
Fall Time
–––
88
–––
C
iss
Input Capacitance
–––
9620
–––
pF
C
oss
Output Capacitance
–––
670
–––
C
rss
Reverse Transfer Capacitance
–––
250
–––
C
oss
eff. (ER) Effective Output Capacitance (Energy Related)i ––– 820 –––
C
oss
eff. (TR) Effective Output Capacitance (Time Related)h
–––
950
–––
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
–––
––– 170c
A
(Body Diode)
I
SM
Pulsed Source Current
–––
–––
670
(Body Diode)
di
V
SD
Diode Forward Voltage
–––
–––
1.3
V
t
rr
Reverse Recovery Time
–––
50
75
ns
T
J
= 25°C
V
R
= 85V,
–––
60
90
T
J
= 125°C
I
F
= 75A
Q
rr
Reverse Recovery Charge
–––
94
140
nC T
J
= 25°C
di/dt = 100A/µs
g
–––
140
210
T
J
= 125°C
I
RRM
Reverse Recovery Current
–––
3.5
–––
A
T
J
= 25°C
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
I
D
= 75A
R
G
= 2.6
Ω
V
GS
= 10V
g
V
DD
= 65V
T
J
= 25°C, I
S
= 75A, V
GS
= 0V
g
integral reverse
p-n junction diode.
Conditions
V
GS
= 0V, I
D
= 250µA
Reference to 25°C, I
D
= 5mAd
V
GS
= 10V, I
D
= 75A g
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 100V, V
GS
= 0V
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
MOSFET symbol
showing the
V
DS
= 50V
Conditions
V
GS
= 10V
g
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 80V
j
V
GS
= 0V, V
DS
= 0V to 80V
h
Conditions
V
DS
= 50V, I
D
= 75A
I
D
= 75A
V
GS
= 20V
V
GS
= -20V
IRFB4110PbF
3
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
VGS
TOP
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM
4.5V
≤60µs PULSE WIDTH
Tj = 25°C
4.5V
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
4.5V
≤60µs PULSE WIDTH
Tj = 175°C
VGS
TOP
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM
4.5V
1
2
3
4
5
6
7
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VDS = 25V
≤60µs PULSE WIDTH
1
10
100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C
, C
ap
ac
ita
nc
e
(p
F
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
3.0
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 75A
VGS = 10V
0
50
100
150
200
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 80V
VDS= 50V
ID= 75A
IRFB4110PbF
4
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Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 11. Typical C
OSS
Stored Energy
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
0.0
0.5
1.0
1.5
2.0
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
90
95
100
105
110
115
120
125
V
(B
R
)D
S
S
, D
ra
in
-t
o-
S
ou
rc
e
B
re
ak
do
w
n
V
ol
ta
ge
(
V
)
Id = 5mA
0
20
40
60
80
100
120
VDS, Drain-to-Source Voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
E
ne
rg
y
(µ
J)
25
50
75
100
125
150
175
TC , Case Temperature (°C)
0
20
40
60
80
100
120
140
160
180
I D
,
D
ra
in
C
ur
re
nt
(
A
)
Limited By Package
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
700
800
E A
S
,
S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
ID
TOP 17A
27A
BOTTOM 108A
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
10000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
DC
IRFB4110PbF
5
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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/ Z
thJC
I
av
=
2
DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
T
he
rm
al
R
es
po
ns
e
(
Z
th
JC
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W)
τ
i (sec)
0.09876251
0.000111
0.2066697
0.001743
0.09510464
0.012269
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
τ
C
τ
C
Ci=
τi/Ri
Ci=
τi/R i
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
50
100
150
200
250
E A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 108A
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
0.1
1
10
100
1000
A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τj = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Tj = 150°C and
Tstart =25°C (Single Pulse)
IRFB4110PbF
6
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Fig. 17 - Typical Recovery Current vs. di
f
/dt
Fig 16. Threshold Voltage vs. Temperature
Fig. 19 - Typical Stored Charge vs. di
f
/dt
Fig. 18 - Typical Recovery Current vs. di
f
/dt
Fig. 20 - Typical Stored Charge vs. di
f
/dt
-75 -50 -25 0 25 50 75 100 125 150 175 200
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
G
S
(t
h)
, G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 250µA
ID = 1.0mA
ID = 1.0A
0
200
400
600
800
1000
diF /dt (A/µs)
0
5
10
15
20
25
I R
R
(
A
)
IF = 30A
VR = 85V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/µs)
0
5
10
15
20
25
I R
R
(
A
)
IF = 45A
VR = 85V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/µs)
80
160
240
320
400
480
560
Q
R
R
(
nC
)
IF = 30A
VR = 85V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/µs)
80
160
240
320
400
480
560
Q
R
R
(
nC
)
IF = 45A
VR = 85V
TJ = 25°C
TJ = 125°C
IRFB4110PbF
7
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Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
V
DD
V
DS
L
D
D.U.T
+
-
Fig 21b. Unclamped Inductive Waveforms
Fig 21a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
RG
IAS
0.01
Ω
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
V
GS
Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 20.
Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
1K
VCC
DUT
0
L
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
IRFB4110PbF
8
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TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at:
http://www.irf.com/package/
IRFB4110
IRFB4110
PYWW?
LC LC
PART NUMBER
DATE CODE
P = LEAD-FREE
Y = LAST DIGIT OF YEAR
WW = WORK WEEK
? = ASSEMBLY SITE CODE
INTERNATIONAL
RECTIFIER LOGO
ASSEMBLY
LOT CODE
OR
YWWP
LC LC
PART NUMBER
DATE CODE
Y = LAST DIGIT OF YEAR
WW = WORK WEEK
P = LEAD-FREE
INTERNATIONAL
RECTIFIER LOGO
ASSEMBLY
LOT CODE
IRFB4110PbF
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IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit
http://www.irf.com/whoto-call/
Qualification standards can be found at International Rectifiers web site:
http://www.irf.com/product-info/reliability/
Applicable version of JEDEC standard at the time of product release.
Moisture Sensitivity Level
TO-220
N/A
RoHS compliant
Qualification information
†
Industrial
†
(per JEDEC JESD47F
††
guidelines)
Yes
Qualification level
Revision History
Date
Comment
• Updated data sheet with new IR corporate template.
• Updated package outline & part marking on page 8.
• Added bullet point in the Benefits "RoHS Compliant, Halogen -Free" on page 1.
• Updated typo on the Fig.19 and Fig.20, unit of Y-axis from "A" to "nC" on page 6.
4/28/2014
Benefits
l
Improved Gate, Avalanche and Dynamic dv/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead Free
l
RoHS Compliant, Halogen-Free
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
A
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
I
DM
Pulsed Drain Current
d
P
D
@T
C
= 25°C
Maximum Power Dissipation
W
Linear Derating Factor
W/°C
V
GS
Gate-to-Source Voltage
V
dv/dt
Peak Diode Recovery
f
V/ns
T
J
Operating Junction and
°C
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
E
AS (Thermally limited)
Single Pulse Avalanche Energy
e
mJ
I
AR
Avalanche Current
d
A
E
AR
Repetitive Avalanche Energy
g
mJ
Thermal Resistance
Symbol
Parameter
Typ.
Max.
Units
R
θJC
Junction-to-Case
k
–––
0.402
R
θCS
Case-to-Sink, Flat Greased Surface
0.50
–––
°C/W
R
θJA
Junction-to-Ambient
j
–––
62
300
Max.
180
c
130
c
670
120
190
See Fig. 14, 15, 22a, 22b
370
5.3
-55 to + 175
± 20
2.5
10lb
xin (1.1Nxm)
IRFB4110PbF
S
D
G
TO-220AB
D
S
D
G
Form
Quantity
IRFB4110PbF
TO-220
Tube
50
IRFB4110PbF
Base Part Number
Package Type
Standard Pack
Orderable Part Number
1
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V
DSS
100V
R
DS(on)
typ.
3.7m
Ω
max.
4.5m
Ω
I
D (Silicon Limited)
180A c
I
D (Package Limited)
120A
IRFB4110PbF
2
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Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.033mH
R
G
= 25
Ω, I
AS
= 108A, V
GS
=10V. Part not recommended for use
above this value.
S
D
G
I
SD
≤ 75A, di/dt ≤ 630A/µs, V
DD
≤ V
(BR)DSS
, T
J
≤ 175°C.
Pulse width
≤ 400µs; duty cycle ≤ 2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage
100
–––
–––
V
∆V
(BR)DSS
/
∆T
J
Breakdown Voltage Temp. Coefficient
––– 0.108 –––
V/°C
R
DS(on)
Static Drain-to-Source On-Resistance
–––
3.7
4.5
m
Ω
V
GS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
I
DSS
Drain-to-Source Leakage Current
–––
–––
20
µA
–––
–––
250
I
GSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
Gate-to-Source Reverse Leakage
–––
–––
-100
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
gfs
Forward Transconductance
160
–––
–––
S
Q
g
Total Gate Charge
–––
150
210
nC
Q
gs
Gate-to-Source Charge
–––
35
–––
Q
gd
Gate-to-Drain ("Miller") Charge
–––
43
–––
R
G
Gate Resistance
–––
1.3
–––
Ω
t
d(on)
Turn-On Delay Time
–––
25
–––
ns
t
r
Rise Time
–––
67
–––
t
d(off)
Turn-Off Delay Time
–––
78
–––
t
f
Fall Time
–––
88
–––
C
iss
Input Capacitance
–––
9620
–––
pF
C
oss
Output Capacitance
–––
670
–––
C
rss
Reverse Transfer Capacitance
–––
250
–––
C
oss
eff. (ER) Effective Output Capacitance (Energy Related)i ––– 820 –––
C
oss
eff. (TR) Effective Output Capacitance (Time Related)h
–––
950
–––
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
–––
––– 170c
A
(Body Diode)
I
SM
Pulsed Source Current
–––
–––
670
(Body Diode)
di
V
SD
Diode Forward Voltage
–––
–––
1.3
V
t
rr
Reverse Recovery Time
–––
50
75
ns
T
J
= 25°C
V
R
= 85V,
–––
60
90
T
J
= 125°C
I
F
= 75A
Q
rr
Reverse Recovery Charge
–––
94
140
nC T
J
= 25°C
di/dt = 100A/µs
g
–––
140
210
T
J
= 125°C
I
RRM
Reverse Recovery Current
–––
3.5
–––
A
T
J
= 25°C
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
I
D
= 75A
R
G
= 2.6
Ω
V
GS
= 10V
g
V
DD
= 65V
T
J
= 25°C, I
S
= 75A, V
GS
= 0V
g
integral reverse
p-n junction diode.
Conditions
V
GS
= 0V, I
D
= 250µA
Reference to 25°C, I
D
= 5mAd
V
GS
= 10V, I
D
= 75A g
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 100V, V
GS
= 0V
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
MOSFET symbol
showing the
V
DS
= 50V
Conditions
V
GS
= 10V
g
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 80V
j
V
GS
= 0V, V
DS
= 0V to 80V
h
Conditions
V
DS
= 50V, I
D
= 75A
I
D
= 75A
V
GS
= 20V
V
GS
= -20V
IRFB4110PbF
3
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
VGS
TOP
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM
4.5V
≤60µs PULSE WIDTH
Tj = 25°C
4.5V
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
4.5V
≤60µs PULSE WIDTH
Tj = 175°C
VGS
TOP
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM
4.5V
1
2
3
4
5
6
7
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VDS = 25V
≤60µs PULSE WIDTH
1
10
100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C
, C
ap
ac
ita
nc
e
(p
F
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
3.0
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 75A
VGS = 10V
0
50
100
150
200
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 80V
VDS= 50V
ID= 75A
IRFB4110PbF
4
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Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 11. Typical C
OSS
Stored Energy
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
0.0
0.5
1.0
1.5
2.0
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
90
95
100
105
110
115
120
125
V
(B
R
)D
S
S
, D
ra
in
-t
o-
S
ou
rc
e
B
re
ak
do
w
n
V
ol
ta
ge
(
V
)
Id = 5mA
0
20
40
60
80
100
120
VDS, Drain-to-Source Voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
E
ne
rg
y
(µ
J)
25
50
75
100
125
150
175
TC , Case Temperature (°C)
0
20
40
60
80
100
120
140
160
180
I D
,
D
ra
in
C
ur
re
nt
(
A
)
Limited By Package
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
700
800
E A
S
,
S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
ID
TOP 17A
27A
BOTTOM 108A
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
10000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
DC
IRFB4110PbF
5
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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/ Z
thJC
I
av
=
2
DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
T
he
rm
al
R
es
po
ns
e
(
Z
th
JC
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W)
τ
i (sec)
0.09876251
0.000111
0.2066697
0.001743
0.09510464
0.012269
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
τ
C
τ
C
Ci=
τi/Ri
Ci=
τi/R i
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
50
100
150
200
250
E A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 108A
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
0.1
1
10
100
1000
A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τj = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Tj = 150°C and
Tstart =25°C (Single Pulse)
IRFB4110PbF
6
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Fig. 17 - Typical Recovery Current vs. di
f
/dt
Fig 16. Threshold Voltage vs. Temperature
Fig. 19 - Typical Stored Charge vs. di
f
/dt
Fig. 18 - Typical Recovery Current vs. di
f
/dt
Fig. 20 - Typical Stored Charge vs. di
f
/dt
-75 -50 -25 0 25 50 75 100 125 150 175 200
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
G
S
(t
h)
, G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 250µA
ID = 1.0mA
ID = 1.0A
0
200
400
600
800
1000
diF /dt (A/µs)
0
5
10
15
20
25
I R
R
(
A
)
IF = 30A
VR = 85V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/µs)
0
5
10
15
20
25
I R
R
(
A
)
IF = 45A
VR = 85V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/µs)
80
160
240
320
400
480
560
Q
R
R
(
nC
)
IF = 30A
VR = 85V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/µs)
80
160
240
320
400
480
560
Q
R
R
(
nC
)
IF = 45A
VR = 85V
TJ = 25°C
TJ = 125°C
IRFB4110PbF
7
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Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
V
DD
V
DS
L
D
D.U.T
+
-
Fig 21b. Unclamped Inductive Waveforms
Fig 21a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
RG
IAS
0.01
Ω
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
V
GS
Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 20.
Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
1K
VCC
DUT
0
L
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
IRFB4110PbF
8
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TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at:
http://www.irf.com/package/
IRFB4110
IRFB4110
PYWW?
LC LC
PART NUMBER
DATE CODE
P = LEAD-FREE
Y = LAST DIGIT OF YEAR
WW = WORK WEEK
? = ASSEMBLY SITE CODE
INTERNATIONAL
RECTIFIER LOGO
ASSEMBLY
LOT CODE
OR
YWWP
LC LC
PART NUMBER
DATE CODE
Y = LAST DIGIT OF YEAR
WW = WORK WEEK
P = LEAD-FREE
INTERNATIONAL
RECTIFIER LOGO
ASSEMBLY
LOT CODE
IRFB4110PbF
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IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit
http://www.irf.com/whoto-call/
Qualification standards can be found at International Rectifiers web site:
http://www.irf.com/product-info/reliability/
Applicable version of JEDEC standard at the time of product release.
Moisture Sensitivity Level
TO-220
N/A
RoHS compliant
Qualification information
†
Industrial
†
(per JEDEC JESD47F
††
guidelines)
Yes
Qualification level
Revision History
Date
Comment
• Updated data sheet with new IR corporate template.
• Updated package outline & part marking on page 8.
• Added bullet point in the Benefits "RoHS Compliant, Halogen -Free" on page 1.
• Updated typo on the Fig.19 and Fig.20, unit of Y-axis from "A" to "nC" on page 6.
4/28/2014