IRF7946PbF Product Datasheet

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DirectFET

®

 Power MOSFET

Fig 1.   Typical On-Resistance vs. Gate Voltage

Fig 2.  Maximum Drain Current vs. Case Temperature

Benefits

l

Improved  Gate, Avalanche and Dynamic dV/dt
Ruggedness

l

Fully Characterized Capacitance and Avalanche

     SOA

l

Enhanced body diode dV/dt and dI/dt Capability

RoHS Compliant Containing no Lead, no Bromide

and no Halogen

Applications

Brushed Motor drive applications

BLDC Motor drive applications

Battery powered circuits

Half-bridge and full-bridge topologies

Synchronous rectifier applications

Resonant mode power supplies

OR-ing and redundant power switches

DC/DC and AC/DC converters

DC/AC Inverters

DirectFET

™ ISOMETRIC

MX

25

50

75

100

125

150

 TC , Case Temperature (°C)

0

50

100

150

200

I D

,   

D

ra

in

 C

ur

re

nt

 (

A

)

Limited By Package

D

D

G

S

S

V

DSS

40V

R

DS(on)

   typ.

1.1mΩ

              max.

1.4m

Ω

I

D (Silicon Limited)

198A

c

I

D (Package Limited)

90A 

4

6

8

10

12

14

16

18

20

VGS, Gate -to -Source Voltage  (V)

0.0

2.0

4.0

6.0

R

D

S

(o

n)

,  

D

ra

in

-t

-S

ou

rc

O

R

es

is

ta

nc

(m

Ω

)

ID = 90A

TJ = 25°C

TJ = 125°C

Strong

IR

FET™

IRF7946PbF

  

     

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Form

Quantity

IRF7946TRPbF

DirectFET MX

Tape and Reel

4800

IRF7946TRPbF

Complete Part Number

Base part number

Package Type

Standard Pack

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IRF7946PbF

Notes:



 Mounted on minimum footprint full size board with metalized

    back and with small clip heatsink.

Ž

 Used double sided cooling , mounting pad with large heatsink.



  T

C

 measured with thermocouple mounted to top (Drain) of part.

Œ

 

 

Surface mounted on 1 in. square Cu

     (still air).



 Mounted to a PCB with

small clip heatsink (still air)

 



 

Mounted on minimum

footprint full size board with
metalized back and with small
clip heatsink (still air)

Absolute Maximum Ratings

Symbol

Parameter

Units

I

D

 @ T

C

 = 25°C

Continuous Drain Current, V

GS

 @ 10V (Silicon Limited)

I

D

 @ T

C

 = 100°C

Continuous Drain Current, V

GS

 @ 10V (Silicon Limited)

I

DM

Pulsed Drain Current 

d

P

D

 @T

C

 = 25°C

Maximum Power Dissipation  

W

Linear Derating Factor

W/°C

V

GS

Gate-to-Source Voltage

V

T

Operating Junction and

T

STG

Storage Temperature Range

Avalanche Characteristics
E

AS (Thermally limited) 

Single Pulse Avalanche Energy 

e

mJ

E

AS (Thermally limited) 

Single Pulse Avalanche Energy  

l

I

AR

Avalanche Current

d

A

E

AR

Repetitive Avalanche Energy 

d

mJ

Thermal Resistance

Symbol

Parameter

Typ.

Max.

Units

R

θJA 

Junction-to-Ambient 

n

–––

45

R

θJA 

Junction-to-Ambient 

p

12.5

–––

R

θJA 

Junction-to-Ambient 

o

20

–––

°C/W

R

θJC 

Junction-to-Case 

qk

–––

1.3

R

θJA-PCB 

Junction-to-PCB Mounted

1.0

–––

96

Max.

198

c

125

c

793

200

-55  to + 150

A

°C

85

See Fig. 14, 15, 22a, 22b

 ± 20

0.77

Static @ T

J

 = 25°C (unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Units

V

(BR)DSS

Drain-to-Source Breakdown Voltage

40

–––

–––

V

ΔV

(BR)DSS

/

ΔT

Breakdown Voltage Temp. Coefficient

–––

0.03

–––

V/°C

R

DS(on)

Static Drain-to-Source On-Resistance

–––

1.1

1.4

m

Ω

1.7

–––

m

Ω

V

GS(th)

Gate Threshold Voltage

2.2

3.0

3.9

V

I

DSS

Drain-to-Source Leakage Current

–––

–––

1.0

μA

–––

–––

150

I

GSS

Gate-to-Source Forward Leakage

–––

–––

100

nA

Gate-to-Source Reverse Leakage

–––

–––

-100

R

G

Internal Gate Resistance

–––

0.67

–––

Ω

V

GS

 = 20V

V

GS

 = -20V

V

DS

 = 40V, V

GS

 = 0V

V

DS

 = 40V, V

GS

 = 0V, T

J

 = 125°C

V

GS

 = 6.0V, I

D

 = 72A 

g

Conditions

V

GS

 = 0V, I

D

 = 250μA

Reference to 25°C, I

D

 = 1.0mA

d

V

GS

 = 10V, I

D

 = 90A 

g

V

DS

 = V

GS

, I

D

 = 150μA

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IRF7946PbF

S

D

G

Notes:



 Calculated continuous current based on maximum allowable

   junction temperature. Package limit is 90A.

‚

 Repetitive rating;  pulse width limited by max. junction

temperature.

ƒ

 Limited by T

Jmax

, starting T

= 25°C, L = 0.021mH

     R

= 50

Ω, I

AS 

= 90A, V

GS

 =10V.

„

I

SD 

≤ 90A, di/dt ≤ 1135A/μs, V

DD 

≤ V

(BR)DSS

, T

≤ 150°C.

…

 Pulse width ≤ 400μs; duty cycle ≤ 2%.

†

 C

oss

 eff. (TR) is a fixed capacitance that gives the same charging time

     as C

oss 

while V

DS 

is rising from 0 to 80% V

DSS

.

‡ 

C

oss

 eff. (ER) is a fixed capacitance that gives the same energy as

     C

oss 

while V

DS 

is rising from 0 to 80% V

DSS

.

ˆ

 When mounted on 1" square PCB (FR-4 or G-10 Material).  For recom

   mended footprint and soldering techniques refer to application note #AN-994.

‰

 R

θ 

is measured at T

J

 approximately 90°C.

Š

 Limited by T

Jmax 

starting

 

T

= 25°C, L= 1mH, R

= 50

Ω, I

AS 

= 20A, V

GS

 =10V

Dynamic @ T

J

 = 25°C (unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Units

gfs

Forward Transconductance

91

–––

–––

S

Q

g

Total Gate Charge

–––

141

212

nC

Q

gs

Gate-to-Source Charge

–––

36

–––

Q

gd

Gate-to-Drain ("Miller") Charge

–––

44

–––

Q

sync

Total Gate Charge Sync. (Q

g

 - Q

gd

)

–––

97

–––

t

d(on)

Turn-On Delay Time

–––

20

–––

ns

t

r

Rise Time

–––

49

–––

t

d(off)

Turn-Off Delay Time

–––

54

–––

t

f

Fall Time

–––

41

–––

C

iss

Input Capacitance

–––

6852

–––

pF

C

oss

Output Capacitance

–––

1046

–––

C

rss

Reverse Transfer Capacitance

–––

735

–––

C

oss

 eff. (ER)

Effective Output Capacitance (Energy Related)  

–––

1307

–––

C

oss

 eff. (TR)

Effective Output Capacitance (Time Related)

–––

1465

–––

Diode Characteristics

Symbol

        Parameter

Min.

Typ.

Max.

Units

I

S

Continuous Source Current 

–––

–––

96

c

A

(Body Diode)

I

SM

Pulsed Source Current

–––

–––

793

A

(Body Diode)d

V

SD

Diode Forward Voltage

–––

0.75

1.2

V

dv/dt

Peak Diode Recovery f

–––

1.6

–––

V/ns

t

rr

Reverse Recovery Time

–––

49

–––

ns

T

J

 = 25°C

V

R

 = 34V,

–––

50

–––

T

J

 = 125°C

I

F

 = 90A

Q

rr

Reverse Recovery Charge

–––

74

–––

nC

T

J

 = 25°C

di/dt = 100A/μs g

–––

73

–––

T

J

 = 125°C

I

RRM

Reverse Recovery Current

–––

2.6

–––

A

T

J

 = 25°C

T

J

 = 175°C, I

S

 = 90A, V

DS

 = 40V

I

D

 = 30A

R

G

 = 2.7

Ω

V

GS

 = 10V g

V

DD

 = 20V

T

J

 = 25°C, I

S

 = 90A, V

GS

 = 0V g

integral reverse

p-n junction diode.

MOSFET symbol

showing  the

Conditions

Conditions

V

DS

 = 10V, I

D

 = 90A

V

DS

 =20V

ƒ = 1.0 MHz

I

D

 = 90A, V

DS

 =0V, V

GS

 = 10V

V

GS

 = 0V, V

DS

 = 0V to 32V i

V

GS

 = 0V, V

DS

 = 0V to 32V h

I

D

 = 90A

V

GS

 = 10V g

V

GS

 = 0V

V

DS

 = 25V

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Fig 3.  Typical Output Characteristics

Fig 5.  Typical Transfer Characteristics

Fig 6.  Normalized On-Resistance vs. Temperature

Fig 4.  Typical Output Characteristics

Fig 8.  Typical Gate Charge vs. Gate-to-Source Voltage

Fig 7.  Typical Capacitance vs. Drain-to-Source Voltage

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

VGS

TOP          

15V

10V

8.0V

7.0V

6.0V
5.5V

5.0V

BOTTOM

4.5V

≤60μs PULSE WIDTH

Tj = 25°C

4.5V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

4.5V

≤60μs PULSE WIDTH

Tj = 150°C

VGS

TOP          

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM

4.5V

2

3

4

5

6

7

8

VGS, Gate-to-Source Voltage (V)

1.0

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 150°C

VDS = 10V
≤60μs PULSE WIDTH

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ , Junction Temperature (°C)

0.6

0.8

0.8

1.0

1.0

1.2

1.2

1.4

1.4

1.6

1.6

1.8

0.6

0.8

1.0

1.2

1.4

1.6

R

D

S

(o

n)

 ,

 D

ra

in

-t

o-

S

ou

rc

O

R

es

is

ta

nc

   

   

   

   

   

   

   

 (

N

or

m

al

iz

ed

)

ID = 90A

VGS = 10V

1

10

100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

100000

C

, C

ap

ac

ita

nc

(p

F

)

VGS   = 0V,       f = 1 MHZ

Ciss   = Cgs + Cgd,  C ds SHORTED
Crss   = Cgd 

Coss  = Cds + Cgd

Coss

Crss

Ciss

0

20

40

60

80 100 120 140 160 180

 QG,  Total Gate Charge (nC)

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

V

G

S

, G

at

e-

to

-S

ou

rc

V

ol

ta

ge

 (

V

)

VDS= 32V

VDS= 20V

ID= 90A

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IRF7946PbF

Fig 10.  Maximum Safe Operating Area

Fig 11.  Drain-to-Source Breakdown Voltage

Fig 9.  Typical Source-Drain Diode

Forward Voltage

Fig 12.  Typical C

OSS

 Stored Energy

Fig 13.   Typical On-Resistance vs. Drain Current

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

VSD, Source-to-Drain Voltage (V)

1.0

10

100

1000

I S

D

, R

ev

er

se

 D

ra

in

 C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 150°C

VGS = 0V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.01

0.1

1

10

100

1000

10000

I D

,  

D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

Tc = 25°C

Tj = 150°C

Single Pulse

10msec

1msec

OPERATION IN THIS AREA 
LIMITED BY R DS(on)

100μsec

DC

Limited by 

Package

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ , Temperature ( °C )

40

41

42

43

44

45

46

47

48

V

(B

R

)D

S

S

,  D

ra

in

-t

o-

S

ou

rc

B

re

ak

do

w

V

ol

ta

ge

 (

V

)

Id = 1.0mA

0

5

10

15

20

25

30

35

40

45

VDS, Drain-to-Source Voltage (V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

E

ne

rg

J)

VDS= 0V to 32V

0

200

400

600

800

1000

ID, Drain Current (A)

0.0

2.0

4.0

6.0

8.0

10.0

R

D

S

(o

n)

,  

D

ra

in

-t

-S

ou

rc

O

R

es

is

ta

nc

(m

Ω

)

VGS = 5.5V

VGS = 6.0V

VGS = 7.0V

VGS = 8.0V

VGS =10V

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Fig 14.  Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 15.  Typical Avalanche Current vs.Pulsewidth

Fig 16.  Maximum Avalanche Energy vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T

jmax

. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT

jmax

 is not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P

D (ave) 

= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

during avalanche).

6. I

av 

= Allowable avalanche current.

7. 

ΔT

 = 

Allowable rise in junction temperature, not to exceed

 

T

jmax 

(assumed as

25°C in Figure 14, 15).
t

av = 

Average time in avalanche.

D = Duty cycle in avalanche =  t

av 

·f

Z

thJC

(D, t

av

) = Transient thermal resistance, see Figures 13)

P

D (ave)

 = 1/2 ( 1.3·BV·I

av

) =

 DT/ Z

thJC

I

av 

=

 

2

DT/ [1.3·BV·Z

th

]

E

AS (AR)

 = P

D (ave)

·t

av

1E-006

1E-005

0.0001

0.001

0.01

0.1

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

1

10

T

he

rm

al

 R

es

po

ns

Z

 th

JC

 )

 °

C

/W

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

0.1

1

10

100

1000

A

va

la

nc

he

 C

ur

re

nt

 (

A

)

Allowed avalanche Current vs avalanche 
pulsewidth, tav, assuming 

ΔΤ j = 25°C and 

Tstart = 125°C.

Allowed avalanche Current vs avalanche 
pulsewidth, tav, assuming 

ΔTj = 125°C and 

Tstart =25°C (Single Pulse)

25

50

75

100

125

150

Starting TJ , Junction Temperature (°C)

0

10

20

30

40

50

60

70

80

90

E

A

R

 , 

A

va

la

nc

he

 E

ne

rg

(m

J)

TOP          Single Pulse                
BOTTOM   1.0% Duty Cycle
ID = 90A

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IRF7946PbF

Fig. 18 - Typical Recovery Current vs. di

f

/dt

Fig 17.  Threshold Voltage vs. Temperature

Fig. 20 - Typical Stored Charge vs. di

f

/dt

Fig. 19 - Typical Recovery Current vs. di

f

/dt

Fig. 21 - Typical Stored Charge vs. di

f

/dt

-75 -50 -25

0

25

50

75 100 125 150

TJ , Temperature ( °C )

1.0

1.5

2.0

2.5

3.0

3.5

4.0

V

G

S

(t

h)

,  G

at

th

re

sh

ol

V

ol

ta

ge

 (

V

)

ID = 150μA

ID = 1.0mA

ID = 1.0A

0

200

400

600

800

1000

diF /dt (A/μs)

0

2

4

6

8

10

12

14

16

I R

R

M

 (

A

)

IF = 54A
VR = 34V
TJ = 25°C
TJ = 125°C

0

200

400

600

800

1000

diF /dt (A/μs)

0

2

4

6

8

10

12

14

16

I R

R

M

 (

A

)

IF = 90A
VR = 34V
TJ = 25°C
TJ = 125°C

0

200

400

600

800

1000

diF /dt (A/μs)

50

100

150

200

250

300

350

Q

R

R

 (

nC

)

IF = 54A
VR = 34V
TJ = 25°C
TJ = 125°C

0

200

400

600

800

1000

diF /dt (A/μs)

50

100

150

200

250

300

350

400

Q

R

R

 (

nC

)

IF = 90A
VR = 34V
TJ = 25°C
TJ = 125°C

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IRF7946PbF

Fig 23a.  Switching Time Test Circuit

Fig 23b.  Switching Time Waveforms

Fig 22b.  Unclamped Inductive Waveforms

Fig 22a.  Unclamped Inductive Test Circuit

tp

V

(BR)DSS

I

AS

RG

IAS

0.01

Ω

tp

D.U.T

L

VDS

+

- VDD

DRIVER

A

15V

20V

V

GS

Fig 24a.  Gate Charge Test Circuit

Fig 24b.   Gate Charge Waveform

Vds

Vgs

Id

Vgs(th)

Qgs1 Qgs2

Qgd

Qgodr

Fig 22. 

Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET

®

 Power MOSFETs

Circuit Layout Considerations

   •  Low Stray Inductance

   •  Ground Plane

   •  Low Leakage Inductance

      Current Transformer

P.W.

Period

di/dt

Diode Recovery

dv/dt

Ripple 

≤ 5%

Body Diode  Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

V

GS

=10V

V

DD

I

SD

Driver Gate Drive

D.U.T. I

SD

Waveform

D.U.T. V

DS

Waveform

Inductor Curent

D = 

P.W.

Period

*

 V

GS

 = 5V for Logic Level Devices

*

+

-

+

+

+

-

-

-

ƒ

„

‚

R

G

V

DD

•  dv/dt controlled by R

G

•  Driver same type as D.U.T.

•  I

SD

 controlled by Duty Factor "D"

•  D.U.T. - Device Under Test

D.U.T



Inductor Current

D.U.T.

V

DS

I

D

I

G

3mA

V

GS

.3

μF

50K

Ω

.2

μF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

+

-

V

DS

90%

10%
V

GS

t

d(on)

t

r

t

d(off)

t

f

V

DS

Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

R

D

V

GS

R

G

D.U.T.

10V

+

-

V

DD

V

GS

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            November 25, 2014

IRF7946PbF

DirectFET

®

 

 Board Footprint, MX Outline

(Medium Size Can, X-Designation).

Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and  substrate designs.

G

S

G=GATE

D=DRAIN

S=SOURCE

S

D

D

D

D

Note: For the most current drawing please refer to IR website at: 

http://www.irf.com/package/

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Submit  Datasheet Feedback            

            November 25, 2014

IRF7946PbF

DirectFET

®

 

 Part Marking

DirectFET

®

 

 

 Outline Dimension, MX Outline

(Medium Size Can, X-Designation).

Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes

all recommendations for stencil and  substrate designs.

GATE MARKING

PART NUMBER

LOGO

BATCH NUMBER

DATE CODE

Line above the last character of

the date code indicates "Lead-Free"

CODE

A
B
C
D
E

F

G

H

J

K

L

M

P

0.017

0.028

0.007

0.040
0.095

0.156

0.028

0.018
0.028

MAX

0.250

0.38

0.59

0.08

0.88
2.28

3.85

0.68

0.35
0.68

MIN

6.25
4.80

0.42

0.70

0.17

1.02
2.42

3.95

0.72

0.45
0.72

MAX

6.35
5.05

0.015

0.023

0.003

0.090

0.035

0.152

0.027

0.027

0.014

MIN

0.189

0.246

METRIC

IMPERIAL

DIMENSIONS

1.38

1.42

0.80

0.84

0.056

0.054

0.033

0.031

R

0.03

0.08

0.001

0.003

Dimensions are shown in

millimeters (inches)

0.199

Note: For the most current drawing please refer to IR website at: 

http://www.irf.com/package/

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background image

DirectFET

®

 Power MOSFET

Fig 1.   Typical On-Resistance vs. Gate Voltage

Fig 2.  Maximum Drain Current vs. Case Temperature

Benefits

l

Improved  Gate, Avalanche and Dynamic dV/dt
Ruggedness

l

Fully Characterized Capacitance and Avalanche

     SOA

l

Enhanced body diode dV/dt and dI/dt Capability

RoHS Compliant Containing no Lead, no Bromide

and no Halogen

Applications

Brushed Motor drive applications

BLDC Motor drive applications

Battery powered circuits

Half-bridge and full-bridge topologies

Synchronous rectifier applications

Resonant mode power supplies

OR-ing and redundant power switches

DC/DC and AC/DC converters

DC/AC Inverters

DirectFET

™ ISOMETRIC

MX

25

50

75

100

125

150

 TC , Case Temperature (°C)

0

50

100

150

200

I D

,   

D

ra

in

 C

ur

re

nt

 (

A

)

Limited By Package

D

D

G

S

S

V

DSS

40V

R

DS(on)

   typ.

1.1mΩ

              max.

1.4m

Ω

I

D (Silicon Limited)

198A

c

I

D (Package Limited)

90A 

4

6

8

10

12

14

16

18

20

VGS, Gate -to -Source Voltage  (V)

0.0

2.0

4.0

6.0

R

D

S

(o

n)

,  

D

ra

in

-t

-S

ou

rc

O

R

es

is

ta

nc

(m

Ω

)

ID = 90A

TJ = 25°C

TJ = 125°C

Strong

IR

FET™

IRF7946PbF

  

     

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             November 25, 2014

Form

Quantity

IRF7946TRPbF

DirectFET MX

Tape and Reel

4800

IRF7946TRPbF

Complete Part Number

Base part number

Package Type

Standard Pack

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IRF7946PbF

Notes:



 Mounted on minimum footprint full size board with metalized

    back and with small clip heatsink.

Ž

 Used double sided cooling , mounting pad with large heatsink.



  T

C

 measured with thermocouple mounted to top (Drain) of part.

Œ

 

 

Surface mounted on 1 in. square Cu

     (still air).



 Mounted to a PCB with

small clip heatsink (still air)

 



 

Mounted on minimum

footprint full size board with
metalized back and with small
clip heatsink (still air)

Absolute Maximum Ratings

Symbol

Parameter

Units

I

D

 @ T

C

 = 25°C

Continuous Drain Current, V

GS

 @ 10V (Silicon Limited)

I

D

 @ T

C

 = 100°C

Continuous Drain Current, V

GS

 @ 10V (Silicon Limited)

I

DM

Pulsed Drain Current 

d

P

D

 @T

C

 = 25°C

Maximum Power Dissipation  

W

Linear Derating Factor

W/°C

V

GS

Gate-to-Source Voltage

V

T

Operating Junction and

T

STG

Storage Temperature Range

Avalanche Characteristics
E

AS (Thermally limited) 

Single Pulse Avalanche Energy 

e

mJ

E

AS (Thermally limited) 

Single Pulse Avalanche Energy  

l

I

AR

Avalanche Current

d

A

E

AR

Repetitive Avalanche Energy 

d

mJ

Thermal Resistance

Symbol

Parameter

Typ.

Max.

Units

R

θJA 

Junction-to-Ambient 

n

–––

45

R

θJA 

Junction-to-Ambient 

p

12.5

–––

R

θJA 

Junction-to-Ambient 

o

20

–––

°C/W

R

θJC 

Junction-to-Case 

qk

–––

1.3

R

θJA-PCB 

Junction-to-PCB Mounted

1.0

–––

96

Max.

198

c

125

c

793

200

-55  to + 150

A

°C

85

See Fig. 14, 15, 22a, 22b

 ± 20

0.77

Static @ T

J

 = 25°C (unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Units

V

(BR)DSS

Drain-to-Source Breakdown Voltage

40

–––

–––

V

ΔV

(BR)DSS

/

ΔT

Breakdown Voltage Temp. Coefficient

–––

0.03

–––

V/°C

R

DS(on)

Static Drain-to-Source On-Resistance

–––

1.1

1.4

m

Ω

1.7

–––

m

Ω

V

GS(th)

Gate Threshold Voltage

2.2

3.0

3.9

V

I

DSS

Drain-to-Source Leakage Current

–––

–––

1.0

μA

–––

–––

150

I

GSS

Gate-to-Source Forward Leakage

–––

–––

100

nA

Gate-to-Source Reverse Leakage

–––

–––

-100

R

G

Internal Gate Resistance

–––

0.67

–––

Ω

V

GS

 = 20V

V

GS

 = -20V

V

DS

 = 40V, V

GS

 = 0V

V

DS

 = 40V, V

GS

 = 0V, T

J

 = 125°C

V

GS

 = 6.0V, I

D

 = 72A 

g

Conditions

V

GS

 = 0V, I

D

 = 250μA

Reference to 25°C, I

D

 = 1.0mA

d

V

GS

 = 10V, I

D

 = 90A 

g

V

DS

 = V

GS

, I

D

 = 150μA

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IRF7946PbF

S

D

G

Notes:



 Calculated continuous current based on maximum allowable

   junction temperature. Package limit is 90A.

‚

 Repetitive rating;  pulse width limited by max. junction

temperature.

ƒ

 Limited by T

Jmax

, starting T

= 25°C, L = 0.021mH

     R

= 50

Ω, I

AS 

= 90A, V

GS

 =10V.

„

I

SD 

≤ 90A, di/dt ≤ 1135A/μs, V

DD 

≤ V

(BR)DSS

, T

≤ 150°C.

…

 Pulse width ≤ 400μs; duty cycle ≤ 2%.

†

 C

oss

 eff. (TR) is a fixed capacitance that gives the same charging time

     as C

oss 

while V

DS 

is rising from 0 to 80% V

DSS

.

‡ 

C

oss

 eff. (ER) is a fixed capacitance that gives the same energy as

     C

oss 

while V

DS 

is rising from 0 to 80% V

DSS

.

ˆ

 When mounted on 1" square PCB (FR-4 or G-10 Material).  For recom

   mended footprint and soldering techniques refer to application note #AN-994.

‰

 R

θ 

is measured at T

J

 approximately 90°C.

Š

 Limited by T

Jmax 

starting

 

T

= 25°C, L= 1mH, R

= 50

Ω, I

AS 

= 20A, V

GS

 =10V

Dynamic @ T

J

 = 25°C (unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Units

gfs

Forward Transconductance

91

–––

–––

S

Q

g

Total Gate Charge

–––

141

212

nC

Q

gs

Gate-to-Source Charge

–––

36

–––

Q

gd

Gate-to-Drain ("Miller") Charge

–––

44

–––

Q

sync

Total Gate Charge Sync. (Q

g

 - Q

gd

)

–––

97

–––

t

d(on)

Turn-On Delay Time

–––

20

–––

ns

t

r

Rise Time

–––

49

–––

t

d(off)

Turn-Off Delay Time

–––

54

–––

t

f

Fall Time

–––

41

–––

C

iss

Input Capacitance

–––

6852

–––

pF

C

oss

Output Capacitance

–––

1046

–––

C

rss

Reverse Transfer Capacitance

–––

735

–––

C

oss

 eff. (ER)

Effective Output Capacitance (Energy Related)  

–––

1307

–––

C

oss

 eff. (TR)

Effective Output Capacitance (Time Related)

–––

1465

–––

Diode Characteristics

Symbol

        Parameter

Min.

Typ.

Max.

Units

I

S

Continuous Source Current 

–––

–––

96

c

A

(Body Diode)

I

SM

Pulsed Source Current

–––

–––

793

A

(Body Diode)d

V

SD

Diode Forward Voltage

–––

0.75

1.2

V

dv/dt

Peak Diode Recovery f

–––

1.6

–––

V/ns

t

rr

Reverse Recovery Time

–––

49

–––

ns

T

J

 = 25°C

V

R

 = 34V,

–––

50

–––

T

J

 = 125°C

I

F

 = 90A

Q

rr

Reverse Recovery Charge

–––

74

–––

nC

T

J

 = 25°C

di/dt = 100A/μs g

–––

73

–––

T

J

 = 125°C

I

RRM

Reverse Recovery Current

–––

2.6

–––

A

T

J

 = 25°C

T

J

 = 175°C, I

S

 = 90A, V

DS

 = 40V

I

D

 = 30A

R

G

 = 2.7

Ω

V

GS

 = 10V g

V

DD

 = 20V

T

J

 = 25°C, I

S

 = 90A, V

GS

 = 0V g

integral reverse

p-n junction diode.

MOSFET symbol

showing  the

Conditions

Conditions

V

DS

 = 10V, I

D

 = 90A

V

DS

 =20V

ƒ = 1.0 MHz

I

D

 = 90A, V

DS

 =0V, V

GS

 = 10V

V

GS

 = 0V, V

DS

 = 0V to 32V i

V

GS

 = 0V, V

DS

 = 0V to 32V h

I

D

 = 90A

V

GS

 = 10V g

V

GS

 = 0V

V

DS

 = 25V

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IRF7946PbF

Fig 3.  Typical Output Characteristics

Fig 5.  Typical Transfer Characteristics

Fig 6.  Normalized On-Resistance vs. Temperature

Fig 4.  Typical Output Characteristics

Fig 8.  Typical Gate Charge vs. Gate-to-Source Voltage

Fig 7.  Typical Capacitance vs. Drain-to-Source Voltage

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

VGS

TOP          

15V

10V

8.0V

7.0V

6.0V
5.5V

5.0V

BOTTOM

4.5V

≤60μs PULSE WIDTH

Tj = 25°C

4.5V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

4.5V

≤60μs PULSE WIDTH

Tj = 150°C

VGS

TOP          

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM

4.5V

2

3

4

5

6

7

8

VGS, Gate-to-Source Voltage (V)

1.0

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 150°C

VDS = 10V
≤60μs PULSE WIDTH

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ , Junction Temperature (°C)

0.6

0.8

0.8

1.0

1.0

1.2

1.2

1.4

1.4

1.6

1.6

1.8

0.6

0.8

1.0

1.2

1.4

1.6

R

D

S

(o

n)

 ,

 D

ra

in

-t

o-

S

ou

rc

O

R

es

is

ta

nc

   

   

   

   

   

   

   

 (

N

or

m

al

iz

ed

)

ID = 90A

VGS = 10V

1

10

100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

100000

C

, C

ap

ac

ita

nc

(p

F

)

VGS   = 0V,       f = 1 MHZ

Ciss   = Cgs + Cgd,  C ds SHORTED
Crss   = Cgd 

Coss  = Cds + Cgd

Coss

Crss

Ciss

0

20

40

60

80 100 120 140 160 180

 QG,  Total Gate Charge (nC)

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

V

G

S

, G

at

e-

to

-S

ou

rc

V

ol

ta

ge

 (

V

)

VDS= 32V

VDS= 20V

ID= 90A

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IRF7946PbF

Fig 10.  Maximum Safe Operating Area

Fig 11.  Drain-to-Source Breakdown Voltage

Fig 9.  Typical Source-Drain Diode

Forward Voltage

Fig 12.  Typical C

OSS

 Stored Energy

Fig 13.   Typical On-Resistance vs. Drain Current

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

VSD, Source-to-Drain Voltage (V)

1.0

10

100

1000

I S

D

, R

ev

er

se

 D

ra

in

 C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 150°C

VGS = 0V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.01

0.1

1

10

100

1000

10000

I D

,  

D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

Tc = 25°C

Tj = 150°C

Single Pulse

10msec

1msec

OPERATION IN THIS AREA 
LIMITED BY R DS(on)

100μsec

DC

Limited by 

Package

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ , Temperature ( °C )

40

41

42

43

44

45

46

47

48

V

(B

R

)D

S

S

,  D

ra

in

-t

o-

S

ou

rc

B

re

ak

do

w

V

ol

ta

ge

 (

V

)

Id = 1.0mA

0

5

10

15

20

25

30

35

40

45

VDS, Drain-to-Source Voltage (V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

E

ne

rg

J)

VDS= 0V to 32V

0

200

400

600

800

1000

ID, Drain Current (A)

0.0

2.0

4.0

6.0

8.0

10.0

R

D

S

(o

n)

,  

D

ra

in

-t

-S

ou

rc

O

R

es

is

ta

nc

(m

Ω

)

VGS = 5.5V

VGS = 6.0V

VGS = 7.0V

VGS = 8.0V

VGS =10V

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IRF7946PbF

Fig 14.  Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 15.  Typical Avalanche Current vs.Pulsewidth

Fig 16.  Maximum Avalanche Energy vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T

jmax

. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT

jmax

 is not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P

D (ave) 

= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

during avalanche).

6. I

av 

= Allowable avalanche current.

7. 

ΔT

 = 

Allowable rise in junction temperature, not to exceed

 

T

jmax 

(assumed as

25°C in Figure 14, 15).
t

av = 

Average time in avalanche.

D = Duty cycle in avalanche =  t

av 

·f

Z

thJC

(D, t

av

) = Transient thermal resistance, see Figures 13)

P

D (ave)

 = 1/2 ( 1.3·BV·I

av

) =

 DT/ Z

thJC

I

av 

=

 

2

DT/ [1.3·BV·Z

th

]

E

AS (AR)

 = P

D (ave)

·t

av

1E-006

1E-005

0.0001

0.001

0.01

0.1

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

1

10

T

he

rm

al

 R

es

po

ns

Z

 th

JC

 )

 °

C

/W

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

0.1

1

10

100

1000

A

va

la

nc

he

 C

ur

re

nt

 (

A

)

Allowed avalanche Current vs avalanche 
pulsewidth, tav, assuming 

ΔΤ j = 25°C and 

Tstart = 125°C.

Allowed avalanche Current vs avalanche 
pulsewidth, tav, assuming 

ΔTj = 125°C and 

Tstart =25°C (Single Pulse)

25

50

75

100

125

150

Starting TJ , Junction Temperature (°C)

0

10

20

30

40

50

60

70

80

90

E

A

R

 , 

A

va

la

nc

he

 E

ne

rg

(m

J)

TOP          Single Pulse                
BOTTOM   1.0% Duty Cycle
ID = 90A

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IRF7946PbF

Fig. 18 - Typical Recovery Current vs. di

f

/dt

Fig 17.  Threshold Voltage vs. Temperature

Fig. 20 - Typical Stored Charge vs. di

f

/dt

Fig. 19 - Typical Recovery Current vs. di

f

/dt

Fig. 21 - Typical Stored Charge vs. di

f

/dt

-75 -50 -25

0

25

50

75 100 125 150

TJ , Temperature ( °C )

1.0

1.5

2.0

2.5

3.0

3.5

4.0

V

G

S

(t

h)

,  G

at

th

re

sh

ol

V

ol

ta

ge

 (

V

)

ID = 150μA

ID = 1.0mA

ID = 1.0A

0

200

400

600

800

1000

diF /dt (A/μs)

0

2

4

6

8

10

12

14

16

I R

R

M

 (

A

)

IF = 54A
VR = 34V
TJ = 25°C
TJ = 125°C

0

200

400

600

800

1000

diF /dt (A/μs)

0

2

4

6

8

10

12

14

16

I R

R

M

 (

A

)

IF = 90A
VR = 34V
TJ = 25°C
TJ = 125°C

0

200

400

600

800

1000

diF /dt (A/μs)

50

100

150

200

250

300

350

Q

R

R

 (

nC

)

IF = 54A
VR = 34V
TJ = 25°C
TJ = 125°C

0

200

400

600

800

1000

diF /dt (A/μs)

50

100

150

200

250

300

350

400

Q

R

R

 (

nC

)

IF = 90A
VR = 34V
TJ = 25°C
TJ = 125°C

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IRF7946PbF

Fig 23a.  Switching Time Test Circuit

Fig 23b.  Switching Time Waveforms

Fig 22b.  Unclamped Inductive Waveforms

Fig 22a.  Unclamped Inductive Test Circuit

tp

V

(BR)DSS

I

AS

RG

IAS

0.01

Ω

tp

D.U.T

L

VDS

+

- VDD

DRIVER

A

15V

20V

V

GS

Fig 24a.  Gate Charge Test Circuit

Fig 24b.   Gate Charge Waveform

Vds

Vgs

Id

Vgs(th)

Qgs1 Qgs2

Qgd

Qgodr

Fig 22. 

Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET

®

 Power MOSFETs

Circuit Layout Considerations

   •  Low Stray Inductance

   •  Ground Plane

   •  Low Leakage Inductance

      Current Transformer

P.W.

Period

di/dt

Diode Recovery

dv/dt

Ripple 

≤ 5%

Body Diode  Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

V

GS

=10V

V

DD

I

SD

Driver Gate Drive

D.U.T. I

SD

Waveform

D.U.T. V

DS

Waveform

Inductor Curent

D = 

P.W.

Period

*

 V

GS

 = 5V for Logic Level Devices

*

+

-

+

+

+

-

-

-

ƒ

„

‚

R

G

V

DD

•  dv/dt controlled by R

G

•  Driver same type as D.U.T.

•  I

SD

 controlled by Duty Factor "D"

•  D.U.T. - Device Under Test

D.U.T



Inductor Current

D.U.T.

V

DS

I

D

I

G

3mA

V

GS

.3

μF

50K

Ω

.2

μF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

+

-

V

DS

90%

10%
V

GS

t

d(on)

t

r

t

d(off)

t

f

V

DS

Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

R

D

V

GS

R

G

D.U.T.

10V

+

-

V

DD

V

GS

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            November 25, 2014

IRF7946PbF

DirectFET

®

 

 Board Footprint, MX Outline

(Medium Size Can, X-Designation).

Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and  substrate designs.

G

S

G=GATE

D=DRAIN

S=SOURCE

S

D

D

D

D

Note: For the most current drawing please refer to IR website at: 

http://www.irf.com/package/

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2014 International Rectifier     

      

Submit  Datasheet Feedback            

            November 25, 2014

IRF7946PbF

DirectFET

®

 

 Part Marking

DirectFET

®

 

 

 Outline Dimension, MX Outline

(Medium Size Can, X-Designation).

Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes

all recommendations for stencil and  substrate designs.

GATE MARKING

PART NUMBER

LOGO

BATCH NUMBER

DATE CODE

Line above the last character of

the date code indicates "Lead-Free"

CODE

A
B
C
D
E

F

G

H

J

K

L

M

P

0.017

0.028

0.007

0.040
0.095

0.156

0.028

0.018
0.028

MAX

0.250

0.38

0.59

0.08

0.88
2.28

3.85

0.68

0.35
0.68

MIN

6.25
4.80

0.42

0.70

0.17

1.02
2.42

3.95

0.72

0.45
0.72

MAX

6.35
5.05

0.015

0.023

0.003

0.090

0.035

0.152

0.027

0.027

0.014

MIN

0.189

0.246

METRIC

IMPERIAL

DIMENSIONS

1.38

1.42

0.80

0.84

0.056

0.054

0.033

0.031

R

0.03

0.08

0.001

0.003

Dimensions are shown in

millimeters (inches)

0.199

Note: For the most current drawing please refer to IR website at: 

http://www.irf.com/package/

Maker
Infineon Technologies