HEXFET
®
Power MOSFET
Notes
through
are on page 10
Top View
8
1
2
3
4
5
6
7
D
D
D
D
G
S
A
S
S
A
SO-8
Absolute Maximum Ratings
Parameter
Units
V
DS
Drain-to-Source Voltage
V
V
GS
Gate-to-Source Voltage
I
D
@ T
A
= 25°C
Continuous Drain Current, V
GS
@ 10V
I
D
@ T
A
= 70°C
Continuous Drain Current, V
GS
@ 10V
A
I
DM
Pulsed Drain Current
c
P
D
@T
A
= 25°C
Power Dissipation
f
W
P
D
@T
A
= 70°C
Power Dissipation
f
Linear Derating Factor
W/°C
T
J
Operating Junction and
°C
T
STG
Storage Temperature Range
Thermal Resistance
Parameter
Typ.
Max.
Units
R
θJL
Junction-to-Drain Lead
g
–––
20
°C/W
R
θJA
Junction-to-Ambient
fg
–––
50
-55 to + 155
2.5
0.02
1.6
Max.
13.6
11
100
± 20
30
Applications
l
High Frequency Point-of-Load Synchronous Buck Converter for Applications in Networking &
Computing Systems.
IRF7821PbF-1
Form
Quantity
Tube/Bulk
95
IRF7821PbF-1
Tape and Reel
4000
IRF7821TRPbF-1
Package Type
Standard Pack
Orderable Part Number
IRF7821PbF-1
SO-8
Base Part Number
Features
Benefits
Industry-standard pinout SO-8 Package
⇒
Multi-Vendor Compatibility
Compatible with Existing Surface Mount Techniques
Easier Manufacturing
RoHS Compliant, Halogen-Free
Environmentally Friendlier
MSL1, Industrial qualification
Increased Reliability
V
DS
30
V
R
DS(on) max
(@V
GS
= 10V)
9.1
Q
g (typical)
9.3
nC
I
D
(@T
A
= 25°C)
13.6
A
mΩ
1
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Static @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BV
DSS
Drain-to-Source Breakdown Voltage
30
–––
–––
V
ΔΒV
DSS
/
ΔT
J
Breakdown Voltage Temp. Coefficient
–––
0.025
–––
V/°C
R
DS(on)
Static Drain-to-Source On-Resistance
–––
7.0
9.1
m
Ω
–––
9.5
12.5
V
GS(th)
Gate Threshold Voltage
1.0
–––
–––
V
ΔV
GS(th)
Gate Threshold Voltage Coefficient
–––
- 4.9
––– mV/°C
I
DSS
Drain-to-Source Leakage Current
–––
–––
1.0
μA
–––
–––
150
I
GSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
Gate-to-Source Reverse Leakage
–––
–––
-100
gfs
Forward Transconductance
22
–––
–––
S
Q
g
Total Gate Charge
–––
9.3
14
Q
gs1
Pre-Vth Gate-to-Source Charge
–––
2.5
–––
Q
gs2
Post-Vth Gate-to-Source Charge
–––
0.8
–––
nC
Q
gd
Gate-to-Drain Charge
–––
2.9
–––
Q
godr
Gate Charge Overdrive
–––
3.1
–––
See Fig. 16
Q
sw
Switch Charge (Q
gs2
+ Q
gd
)
–––
3.7
–––
Q
oss
Output Charge
–––
6.1
–––
nC
t
d(on)
Turn-On Delay Time
–––
6.3
–––
t
r
Rise Time
–––
2.7
–––
t
d(off)
Turn-Off Delay Time
–––
9.7
–––
ns
t
f
Fall Time
–––
7.3
–––
C
iss
Input Capacitance
–––
1010
–––
C
oss
Output Capacitance
–––
360
–––
pF
C
rss
Reverse Transfer Capacitance
–––
110
–––
Avalanche Characteristics
Parameter
Units
E
AS
Single Pulse Avalanche Energy
dh
mJ
I
AR
Avalanche Current
c
A
Diode Characteristics
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
–––
–––
3.1
(Body Diode)
A
I
SM
Pulsed Source Current
–––
–––
100
(Body Diode)
ch
V
SD
Diode Forward Voltage
–––
–––
1.0
V
t
rr
Reverse Recovery Time
–––
28
42
ns
Q
rr
Reverse Recovery Charge
–––
23
35
nC
–––
I
D
= 10A
V
GS
= 0V
V
DS
= 15V
V
GS
= 4.5V, I
D
= 10A
e
V
GS
= 4.5V
Typ.
–––
V
DS
= V
GS
, I
D
= 250μA
Clamped Inductive Load
V
DS
= 15V, I
D
= 10A
V
DS
= 24V, V
GS
= 0V, T
J
= 125°C
T
J
= 25°C, I
F
= 10A, V
DD
= 20V
di/dt = 100A/μs
e
T
J
= 25°C, I
S
= 10A, V
GS
= 0V
e
showing the
integral reverse
p-n junction diode.
MOSFET symbol
V
DS
= 10V, V
GS
= 0V
V
DD
= 15V, V
GS
= 4.5V
e
I
D
= 10A
V
DS
= 15V
V
GS
= 20V
V
GS
= -20V
V
DS
= 24V, V
GS
= 0V
Conditions
V
GS
= 0V, I
D
= 250μA
Reference to 25°C, I
D
= 1mA
V
GS
= 10V, I
D
= 13A
e
Conditions
Max.
44
10
ƒ = 1.0MHz
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
2.0
3.0
4.0
5.0
6.0
VGS, Gate-to-Source Voltage (V)
0.1
1.0
10.0
100.0
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
Α
)
TJ = 25°C
TJ = 150°C
VDS = 15V
20μs PULSE WIDTH
-60 -40 -20
0
20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 13A
VGS = 10V
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
2.5V
20μs PULSE WIDTH
Tj = 25°C
VGS
TOP 10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
2.5V
20μs PULSE WIDTH
Tj = 150°C
VGS
TOP 10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
C
, C
ap
ac
ita
nc
e
(p
F
)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0
5
10
15
20
QG Total Gate Charge (nC)
0
2
4
6
8
10
12
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 24V
VDS= 15V
ID= 10A
0.0
0.5
1.0
1.5
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 150°C
VGS = 0V
0.1
1.0
10.0
100.0
1000.0
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 150°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100μsec
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Threshold Voltage Vs. Temperature
-75
-50
-25
0
25
50
75
100 125 150
TJ , Temperature ( °C )
1.0
1.4
1.8
2.2
2.6
V
G
S
(t
h)
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 250μA
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
0.01
0.1
1
10
100
T
he
rm
al
R
es
po
ns
e
(
Z
th
JA
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
25
50
75
100
125
150
TJ , Junction Temperature (°C)
0
2
4
6
8
10
12
14
I D
,
D
ra
in
C
ur
re
nt
(
A
)
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Fig 13b. Unclamped Inductive Waveforms
Fig 13a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 13c. Maximum Avalanche Energy
Vs. Drain Current
RG
IAS
0.01
Ω
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
V
GS
25
50
75
100
125
150
Starting TJ, Junction Temperature (°C)
0
20
40
60
80
100
E
A
S
, S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
I D
TOP
4.5A
8.0A
BOTTOM
10A
Fig 14a. Switching Time Test Circuit
Fig 14b. Switching Time Waveforms
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
f
t
r
V
GS
Pulse Width < 1μs
Duty Factor < 0.1%
V
DD
V
DS
L
D
D.U.T
Fig 12. On-Resistance Vs. Gate Voltage
2.0
4.0
6.0
8.0
10.0
VGS, Gate-to-Source Voltage (V)
0
5
10
15
20
25
30
R
D
S
(o
n)
,
D
ra
in
-t
o
-S
ou
rc
e
O
n
R
es
is
ta
nc
e
(m
Ω
)
TJ = 25°C
TJ = 125°C
ID = 13A
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D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
μF
50K
Ω
.2
μF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 16. Gate Charge Test Circuit
Fig 15.
Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 17. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
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Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the R
ds(on)
of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
This can be expanded and approximated by;
P
loss
= I
rms
2
× R
ds(on )
(
)
+ I ×
Q
gd
i
g
× V
in
× f
⎛
⎝
⎜
⎞
⎠
⎟ + I ×
Q
gs 2
i
g
× V
in
× f
⎛
⎝
⎜
⎞
⎠
⎟
+ Q
g
× V
g
× f
(
)
+
Q
oss
2
×V
in
× f
⎛
⎝
⎞
⎠
This simplified loss equation includes the terms Q
gs2
and Q
oss
which are new to Power MOSFET data sheets.
Q
gs2
is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q
gs1
and Q
gs2
, can be seen from
Fig 16.
Q
gs2
indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to I
dmax
at which time the drain voltage be-
gins to change. Minimizing Q
gs2
is a critical factor in
reducing switching losses in Q1.
Q
oss
is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Q
oss
is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances C
ds
and C
dg
when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss
= P
conduction
+ P
drive
+ P
output
*
P
loss
= I
rms
2
× R
ds(on)
(
)
+ Q
g
× V
g
× f
(
)
+
Q
oss
2
× V
in
× f
⎛
⎝
⎜
⎞
⎠
+ Q
rr
× V
in
× f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, R
ds(on)
is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
oss
and re-
verse recovery charge Q
rr
both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in
. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd
/Q
gs1
must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Q
oss
Characteristic
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SO-8 Package Details
SO-8 Part Marking
e 1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN
MAX
MILLIMETERS
INCHES
MIN
MAX
DIM
8°
e
c
.0075
.0098
0.19
0.25
.025 BASIC
0.635 BASIC
8
7
5
6
5
D
B
E
A
e
6X
H
0.25 [.010]
A
6
7
K x 45°
8X L
8X c
y
0.25 [.010]
C A B
e1
A
A1
8X b
C
0.10 [.004]
4
3
1
2
FOOTPRINT
8X 0.72 [.028]
6.46 [.255]
3X 1.27 [.050]
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS -012AA.
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
8X 1.78 [.070]
DATE CODE (YWW)
XXXX
INTERNATIONAL
RECTIFIER
LOGO
F7101
Y = LAS T DIGIT OF THE YEAR
PART NUMBER
LOT CODE
WW = WEEK
EXAMPLE: THIS IS AN IRF7101 (MOSFET)
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
A = AS SEMBLY S ITE CODE
Dimensions are shown in milimeters (inches)
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/
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10
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330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
FEED DIRECTION
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
SO-8 Tape and Reel
(Dimensions are shown in milimeters (inches))
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 0.87mH, R
G
= 25
Ω, I
AS
= 10A.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
When mounted on 1 inch square copper board
R
θ
is measured at T
J
approximately 90°C
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/
† Qualification standards can be found at International Rectifier’s web site:
http://www.irf.com/product-info/reliability
††
Applicable version of JEDEC standard at the time of product release
MS L1
(per JEDEC J-S TD-020D
††
)
RoHS compliant
Yes
Qualification information
†
Qualification level
Industrial
(per JEDEC JES D47F
††
guidelines)
Moisture Sensitivity Level
SO-8
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit
http://www.irf.com/whoto-call/