IRF2804PbF
IRF2804SPbF
IRF2804LPbF
HEXFET
®
Power MOSFET
V
DSS
= 40V
R
DS(on)
= 2.0m
Ω
I
D
= 75A
05/12/10
www.irf.com
1
HEXFET
®
is a registered trademark of International Rectifier.
Description
This HEXFET
®
Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating. These features combine
to make this design an extremely efficient and
reliable device for use in a wide variety of other
applications.
S
D
G
Features
l
Advanced Process Technology
l
Ultra Low On-Resistance
l
175°C Operating Temperature
l
Fast Switching
l
Repetitive Avalanche Allowed up to Tjmax
l
Lead-Free
D
2
Pak
IRF2804SPbF
TO-220AB
IRF2804PbF
TO-262
IRF2804LPbF
Absolute Maximum Ratings
Parameter
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
A
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V (See Fig. 9)
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
(Package Limited)
I
DM
Pulsed Drain Current
c
P
D
@T
C
= 25°C
Maximum Power Dissipation
W
Linear Derating Factor
W/°C
V
GS
Gate-to-Source Voltage
V
E
AS
Single Pulse Avalanche Energy (Thermally Limited)
d
mJ
E
AS
(tested)
Single Pulse Avalanche Energy Tested Value
i
I
AR
Avalanche Current
c
A
E
AR
Repetitive Avalanche Energy
h
mJ
T
J
Operating Junction and
°C
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter
Typ.
Max.
Units
R
θJC
Junction-to-Case
–––
0.50
l
°C/W
R
θCS
Case-to-Sink, Flat, Greased Surface
0.50
–––
R
θJA
Junction-to-Ambient
–––
62
R
θJA
Junction-to-Ambient (PCB Mount, steady state)
j
–––
40
Max.
270
190
1080
75
10 lbf•in (1.1N•m)
300
2.0
± 20
540
1160
See Fig.12a,12b,15,16
300 (1.6mm from case )
-55 to + 175
PD - 95332B
IRF2804/S/LPbF
2
www.irf.com
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by T
Jmax
, starting T
J
= 25°C,
L=0.24mH, R
G
= 25
Ω, I
AS
= 75A, V
GS
=10V.
Part not recommended for use above this value.
I
SD
≤ 75A, di/dt ≤ 220A/µs, V
DD
≤ V
(BR)DSS
,
T
J
≤ 175°C.
Pulse width
≤ 1.0ms; duty cycle ≤ 2%.
C
oss
eff. is a fixed capacitance that gives the same
charging time as C
oss
while V
DS
is rising from 0 to 80%
V
DSS
.
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
This is applied to D
2
Pak, when mounted on 1" square PCB
( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.
Max R
DS(on)
for D
2
Pak and TO-262 (SMD) devices.
TO-220 device will have an Rth value of 0.45°C/W.
S
D
G
S
D
G
Static @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage
40
–––
–––
V
∆ΒV
DSS
/
∆T
J
Breakdown Voltage Temp. Coefficient
–––
0.031
–––
V/°C
R
DS(on)
SMD
Static Drain-to-Source On-Resistance
–––
1.5
2.0
m
Ω
R
DS(on)
TO-220 Static Drain-to-Source On-Resistance
–––
1.8
2.3
V
GS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
gfs
Forward Transconductance
130
–––
–––
S
I
DSS
Drain-to-Source Leakage Current
–––
–––
20
µA
–––
–––
250
I
GSS
Gate-to-Source Forward Leakage
–––
–––
200
nA
Gate-to-Source Reverse Leakage
–––
–––
-200
Q
g
Total Gate Charge –––
160
240
nC
Q
gs
Gate-to-Source Charge
–––
41
62
Q
gd
Gate-to-Drain ("Miller") Charge
–––
66
99
t
d(on)
Turn-On Delay Time
–––
13
–––
ns
t
r
Rise Time
–––
120
–––
t
d(off)
Turn-Off Delay Time
–––
130
–––
t
f
Fall Time
–––
130
–––
L
D
Internal Drain Inductance
–––
4.5
–––
nH
Between lead,
6mm (0.25in.)
L
S
Internal Source Inductance
–––
7.5
–––
from package
and center of die contact
C
iss
Input Capacitance
–––
6450
–––
pF
C
oss
Output Capacitance
–––
1690
–––
C
rss
Reverse Transfer Capacitance
–––
840
–––
C
oss
Output Capacitance
–––
5350
–––
C
oss
Output Capacitance
–––
1520
–––
C
oss
eff.
Effective Output Capacitance
–––
2210
–––
Diode Characteristics
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
–––
–––
270
(Body Diode)
A
I
SM
Pulsed Source Current
–––
–––
1080
(Body Diode)
c
V
SD
Diode Forward Voltage
–––
–––
1.3
V
t
rr
Reverse Recovery Time
–––
56
84
ns
Q
rr
Reverse Recovery Charge
–––
67
100
nC
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 40V, V
GS
= 0V
V
DS
= 40V, V
GS
= 0V, T
J
= 125°C
Conditions
V
GS
= 0V, I
D
= 250µA
Reference to 25°C, I
D
= 1mA
V
GS
= 10V, I
D
= 75A
f
V
GS
= 10V, I
D
= 75A
f
T
J
= 25°C, I
F
= 75A, V
DD
= 20V
di/dt = 100A/µs
f
T
J
= 25°C, I
S
= 75A, V
GS
= 0V
f
showing the
integral reverse
p-n junction diode.
V
GS
= 0V, V
DS
= 1.0V, ƒ = 1.0MHz
V
GS
= 10V
f
MOSFET symbol
V
GS
= 0V
V
DS
= 25V
V
GS
= 0V, V
DS
= 32V, ƒ = 1.0MHz
Conditions
V
GS
= 0V, V
DS
= 0V to 32V
ƒ = 1.0MHz, See Fig. 5
R
G
= 2.5
Ω
I
D
= 75A
V
DS
= 10V, I
D
= 75A
V
DD
= 20V
I
D
= 75A
V
GS
= 20V
V
GS
= -20V
V
DS
= 32V
V
GS
= 10V
f
IRF2804/S/LPbF
www.irf.com
3
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance
vs. Drain Current
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
4.5V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.0
5.0
6.0
7.0
8.0
9.0
VGS, Gate-to-Source Voltage (V)
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
Α
)
TJ = 25°C
TJ = 175°C
VDS = 10V
20µs PULSE WIDTH
0
40
80
120
160
200
ID, Drain-to-Source Current (A)
0
50
100
150
200
250
300
G
fs
, F
or
w
ar
d
T
ra
ns
co
nd
uc
ta
nc
e
(
S
)
TJ = 25°C
TJ = 175°C
VDS = 10V
20µs PULSE WIDTH
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
4.5V
20µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
V
GS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
IRF2804/S/LPbF
4
www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
0
2000
4000
6000
8000
10000
12000
C
, C
ap
ac
ita
nc
e
(p
F
)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0
40
80
120
160
200
240
QG Total Gate Charge (nC)
0
4
8
12
16
20
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 32V
VDS= 20V
VDS= 8.0V
ID= 75A
0.2
0.6
1.0
1.4
1.8
2.2
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
0
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
Tc = 25°C
Tj = 175°C
Single Pulse
IRF2804/S/LPbF
www.irf.com
5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Normalized On-Resistance
vs. Temperature
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 75A
VGS = 10V
25
50
75
100
125
150
175
TC , Case Temperature (°C)
0
50
100
150
200
250
300
I D
,
D
ra
in
C
ur
re
nt
(
A
)
Limited By Package
1E-008
1E-007
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
T
he
rm
al
R
es
po
ns
e
(
Z
th
JC
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
IRF2804/S/LPbF
6
www.irf.com
Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
µF
50K
Ω
.2
µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage vs. Temperature
RG
IAS
0.01
Ω
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
V
GS
-75 -50 -25
0
25
50
75 100 125 150 175
TJ , Temperature ( °C )
1.0
2.0
3.0
4.0
V
G
S
(t
h)
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 250µA
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
200
400
600
800
1000
1200
E
A
S
,
S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
ID
TOP 31A
53A
BOTTOM 75A
IRF2804/S/LPbF
www.irf.com
7
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/ Z
thJC
I
av
=
2
DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
1
10
100
1000
A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
∆ Tj = 25°C due to
avalanche losses
0.01
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 10% Duty Cycle
ID = 75A
IRF2804/S/LPbF
8
www.irf.com
Fig 17.
Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
V
DS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
IRF2804/S/LPbF
www.irf.com
9
TO-220AB Part Marking Information
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
/27&2'(
(;$03/( 7+,6,6$1,5)
1RWH3LQDVVHPEO\OLQHSRVLWLRQ
LQGLFDWHV/HDG)UHH
,17+($66(0%/</,1(&
$66(0%/('21::
,17(51$7,21$/
3$57180%(5
5(&7,),(5
/27&2'(
$66(0%/<
/2*2
<($5
'$7(&2'(
:((.
/,1(&
Notes:
1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/datasheets/data/auirf2804.pdf
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF2804/S/LPbF
10
www.irf.com
D
2
Pak Part Marking Information
D
2
Pak Package Outline
Dimensions are shown in millimeters (inches)
'$7(&2'(
<($5
:((.
$ $66(0%/<6,7(&2'(
5(&7,),(5
,17(51$7,21$/
3$57180%(5
3 '(6,*1$7(6/($')5((
352'8&7237,21$/
)6
,17+($66(0%/</,1(/
$66(0%/('21::
7+,6,6$1,5)6:,7+
/27&2'(
,17(51$7,21$/
/2*2
5(&7,),(5
/27&2'(
$66(0%/<
<($5
3$57180%(5
'$7(&2'(
/,1(/
:((.
25
)6
/2*2
$66(0%/<
/27&2'(
Notes:
1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/datasheets/data/auirf2804.pdf
2. For the most current drawing please refer to IR website at http://www.irf.com/package/