07/06/10
www.irf.com
1
HEXFET
®
is a registered trademark of International Rectifier.
IRF1010EZPbF
IRF1010EZSPbF
IRF1010EZLPbF
HEXFET
®
Power MOSFET
S
D
G
V
DSS
= 60V
R
DS(on)
= 8.5m
Ω
I
D
= 75A
Features
l
Advanced Process Technology
l
Ultra Low On-Resistance
l
Dynamic dv/dt Rating
l
175°C Operating Temperature
l
Fast Switching
l
Repetitive Avalanche Allowed up to Tjmax
l
Lead-Free
Description
This HEXFET
®
Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating.These features
combine to make this design an extremely efficient
and reliable device for use in a wide variety of
applications.
D
2
Pak
IRF1010EZSPbF
TO-220AB
IRF1010EZPbF
TO-262
IRF1010EZLPbF
Absolute Maximum Ratings
Parameter
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
A
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V (See Fig. 9)
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
(Package Limited)
I
DM
Pulsed Drain Current
c
P
D
@T
C
= 25°C
Maximum Power Dissipation
W
Linear Derating Factor
W/°C
V
GS
Gate-to-Source Voltage
V
E
AS
Single Pulse Avalanche Energy (Thermally Limited)
d
mJ
E
AS
(tested)
Single Pulse Avalanche Energy Tested Value
i
I
AR
Avalanche Current
c
A
E
AR
Repetitive Avalanche Energy
h
mJ
T
J
Operating Junction and
°C
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter
Typ.
Max.
Units
R
θJC
Junction-to-Case
–––
1.11
°C/W
R
θCS
Case-to-Sink, Flat, Greased Surface
0.50
–––
R
θJA
Junction-to-Ambient
–––
62
R
θJA
Junction-to-Ambient (PCB Mount, steady state)
j
–––
40
Max.
84
60
340
75
10 lbf•in (1.1N•m)
140
0.90
± 20
99
180
See Fig.12a,12b,15,16
300 (1.6mm from case )
-55 to + 175
PD - 95483C
IRF1010EZ/S/LPbF
2
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Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.077mH,
R
G
= 25
Ω, I
AS
= 51A, V
GS
=10V. Part not
recommended for use above this value.
I
SD
≤ 51A, di/dt ≤ 260A/µs, V
DD
≤ V
(BR)DSS
,
T
J
≤ 175°C.
Pulse width
≤ 1.0ms; duty cycle ≤ 2%.
C
oss
eff. is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
This is applied to D
2
Pak, when mounted on 1" square PCB
( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.
S
D
G
S
D
G
Static @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage
60
–––
–––
V
∆ΒV
DSS
/
∆T
J
Breakdown Voltage Temp. Coefficient –––
0.058 –––
V/°C
R
DS(on)
Static Drain-to-Source On-Resistance –––
6.8
8.5
m
Ω
V
GS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
gfs
Forward Transconductance
200
–––
–––
S
I
DSS
Drain-to-Source Leakage Current
–––
–––
20
µA
–––
–––
250
I
GSS
Gate-to-Source Forward Leakage
–––
–––
200
nA
Gate-to-Source Reverse Leakage
–––
–––
-200
Q
g
Total Gate Charge –––
58
86
nC
Q
gs
Gate-to-Source Charge
–––
19
28
Q
gd
Gate-to-Drain ("Miller") Charge
–––
21
32
t
d(on)
Turn-On Delay Time
–––
19
–––
ns
t
r
Rise Time
–––
90
–––
t
d(off)
Turn-Off Delay Time
–––
38
–––
t
f
Fall Time
–––
54
–––
L
D
Internal Drain Inductance
–––
4.5
–––
nH
Between lead,
6mm (0.25in.)
L
S
Internal Source Inductance
–––
7.5
–––
from package
and center of die contact
C
iss
Input Capacitance
–––
2810
–––
pF
C
oss
Output Capacitance
–––
420
–––
C
rss
Reverse Transfer Capacitance
–––
200
–––
C
oss
Output Capacitance
–––
1440
–––
C
oss
Output Capacitance
–––
320
–––
C
oss
eff.
Effective Output Capacitance
–––
510
–––
Diode Characteristics
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
–––
–––
84
(Body Diode)
A
I
SM
Pulsed Source Current
–––
–––
340
(Body Diode)
c
V
SD
Diode Forward Voltage
–––
–––
1.3
V
t
rr
Reverse Recovery Time
–––
41
62
ns
Q
rr
Reverse Recovery Charge
–––
54
81
nC
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Conditions
V
GS
= 0V, I
D
= 250µA
Reference to 25°C, I
D
= 1mA
V
GS
= 10V, I
D
= 51A
f
V
DS
= V
GS
, I
D
= 100µA
V
DS
= 60V, V
GS
= 0V
V
DS
= 60V, V
GS
= 0V, T
J
= 125°C
R
G
= 7.95
Ω
I
D
= 51A
V
DS
= 25V, I
D
= 51A
V
DD
= 30V
I
D
= 51A
V
GS
= 20V
V
GS
= -20V
T
J
= 25°C, I
F
= 51A, V
DD
= 30V
di/dt = 100A/µs
f
T
J
= 25°C, I
S
= 51A, V
GS
= 0V
f
showing the
integral reverse
p-n junction diode.
MOSFET symbol
V
GS
= 0V
V
DS
= 25V
V
GS
= 0V, V
DS
= 48V, ƒ = 1.0MHz
Conditions
V
GS
= 0V, V
DS
= 0V to 48V
V
DS
= 48V
V
GS
= 10V
f
ƒ = 1.0MHz, See Fig. 5
V
GS
= 0V, V
DS
= 1.0V, ƒ = 1.0MHz
V
GS
= 10V
f
IRF1010EZ/S/LPbF
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3
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance
vs. Drain Current
0.01
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
20µs PULSE WIDTH
Tj = 175°C
4.5V
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
4
5
6
7
8
9
10
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
Α
)
TJ = 25°C
TJ = 175°C
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
10000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
20µs PULSE WIDTH
Tj = 25°C
4.5V
0
20
40
60
80
100
120
140
ID,Drain-to-Source Current (A)
0
10
20
30
40
50
60
70
80
90
100
G
fs
, F
or
w
ar
d
T
ra
ns
co
nd
uc
ta
nc
e
(S
)
TJ = 25°C
TJ = 175°C
VDS = 25V
≤60µs PULSE WIDTH
IRF1010EZ/S/LPbF
4
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C
, C
ap
ac
ita
nc
e(
pF
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0
10
20
30
40
50
60
QG Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 48V
VDS= 30V
VDS= 12V
ID= 51A
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VSD, Source-to-Drain Voltage (V)
0.10
1.00
10.00
100.00
1000.00
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
10000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
Tc = 25°C
Tj = 175°C
Single Pulse
IRF1010EZ/S/LPbF
www.irf.com
5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Normalized On-Resistance
vs. Temperature
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 84A
VGS = 10V
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
he
rm
al
R
es
po
ns
e
(
Z
th
JC
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W)
τi (sec)
0.415 0.000246
0.410 0.000898
0.285 0.009546
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
τ
τ
C
Ci i
/Ri
Ci=
τi/Ri
25
50
75
100
125
150
175
TC , Case Temperature (°C)
0
10
20
30
40
50
60
70
80
90
100
I D
,
D
ra
in
C
ur
re
nt
(
A
)
Limited By Package
IRF1010EZ/S/LPbF
6
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Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
µF
50K
Ω
.2
µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage vs. Temperature
RG
IAS
0.01
Ω
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
V
GS
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
50
100
150
200
250
300
350
400
E
A
S
,
S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
ID
TOP 5.7A
9.1A
BOTTOM 51A
-75 -50 -25
0
25
50
75 100 125 150 175
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V
G
S
(t
h)
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 250µA
IRF1010EZ/S/LPbF
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7
Fig 15. Typical Avalanche Current vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/ Z
thJC
I
av
=
2
DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
0.1
1
10
100
1000
A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
∆ Tj = 25°C due to
avalanche losses
0.01
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
25
50
75
100
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 51A
IRF1010EZ/S/LPbF
8
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Fig 17.
Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
V
DS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
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9
TO-220AB Part Marking Information
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
INTERNATIONAL
PART NUMBER
RECTIFIER
LOT CODE
ASSEMBLY
LOGO
YEAR 0 = 2000
DATE CODE
WEEK 19
LINE C
LOT CODE 1789
EXAMPLE: THIS IS AN IRF1010
Note: "P" in assembly line position
indicates "Lead - Free"
IN THE ASSEMBLY LINE "C"
ASSEMBLED ON WW 19, 2000
Notes:
1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/datasheets/data/auirf1010ez.pdf
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF1010EZ/S/LPbF
10
www.irf.com
D
2
Pak (TO-263AB) Part Marking Information
DATE CODE
YEAR 0 = 2000
WEEK 02
A = ASS EMBLY SITE CODE
RECT IFIER
INT ERNAT IONAL
PART NUMBER
P = DESIGNATES LEAD - FREE
PRODUCT (OPTIONAL)
F530S
IN THE ASS EMBLY LINE "L"
ASSEMBLED ON WW 02, 2000
THIS IS AN IRF530S WITH
LOT CODE 8024
INTERNAT IONAL
LOGO
RECT IFIER
LOT CODE
ASSEMBLY
YEAR 0 = 2000
PART NUMBER
DATE CODE
LINE L
WEEK 02
OR
F530S
LOGO
ASSEMBLY
LOT CODE
D
2
Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
Notes:
1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/datasheets/data/auirf1010ez.pdf
2. For the most current drawing please refer to IR website at http://www.irf.com/package/