ICB1FL03G
Smart Ballast Control IC for
Fluorescent Lamp Ballasts
I n d u s t r i a l & M u l t i m a r k e t
Preliminary Datasheet Version 1.02, March 2009
Edition 2009-03
Published by
Infineon Technologies AG
81726 Munich, Germany
©
2009 Infineon Technologies AG.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a
guarantee of conditions or characteristics. With respect to any examples or
hints given herein, any typical values stated herein and/or any information
regarding the application of the device, Infineon Technologies hereby disclaims
any and all warranties and liabilities of any kind, including without limitation,
warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices,
please contact the nearest Infineon Technologies Office (
www.infineon.com
).
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substances. For information on the types in question, please contact the
nearest Infineon Technologies Office.
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ICB1FL03G
Revision History:
2009-03
V 1.02
Previous Version:
V 1.01
Page
Subjects (major changes since last revision)
Type
Package
ICB1FL03G
PG-DSO-18-2
ICB1FL03G
PG-DSO-18-1
Preliminary Datasheet Version 1.02
3
March 2009
Product Highlights
• Lowest Count of external Components
• HV-Driver with coreless Transformer Technology
• Improved Reliability and minimized Spread due to
digital and optimized analog control functions
Features PFC
• Discontinuous Conduction Mode PFC
• Integrated Compensation of PFC Control Loop
• Adjustable PFC Current Limitation
• Adjustable PFC Bus Voltage
Features Lamp Ballast Inverter
• Supports Restart after Lamp Removal and End-of-
Life Detection even in serial Multi-Lamp Topologies
• End-of-Life (EOL) detected by adjustable
± Thresholds of sensed lamp voltage
• Rectifier Effect detected by ratio of ± Amplitude of
Lamp Voltage
• Detection of different capacitive Mode Operations
• Adjustable Inverter Overcurrent Shutdown
• Self-adaption of Ignition Time from 40ms to 235ms
• Parameters adjustable by Resistors only
• Pb-free lead plating; RoHS compliant
• Halogen-free mould compound, WEEE compliant
Smart Ballast Control IC for
Fluorescent Lamp Ballasts
Description
The Smart Ballast IC is designed to control a Fluorescent
Lamp Ballast including a Discontinuous Conduction
Mode Power Factor Correction (PFC), a lamp Inverter
Control and a High Voltage Level Shift Half-Bridge
Driver.
The application requires a minimum of external
components. There are integrated low pass filters and an
internal compensation for the PFC voltage loop control.
Preheating time is adjustable by a single resistor only in
the range between 0 and 2000ms. In the same way the
preheating frequency and run frequency are set by
resistors only. The control concept covers requirements
for T5 lamp ballasts such as detection of end-of-life and
detection of capacitive mode operation and other
protection measures in serial multilamp topologies.
ICB1FL03G is easy to use and easy to design and
therefore a basis for a cost effective solution for
fluorescent lamp ballasts.
PG-DSO-18-2
RF
R
U
N
RF
P
H
RT
P
H
VC
C
PFCZCD
PFCGD
PFCVS
PFCCS
HSGD
HSVCC
HSGND
LSGD
LSCS
GN
D
90 ... 270 VAC
IC
B
1
F
L
03
G
RE
S
C2
C10
C11
C1
C16
C14
C13
C12
C15
C17
C19
R1
R2
R3
R13
R14
R15
R16
R20
R18 R19
R21R22R23
R11
R12
R34
R35
R41
R42 R43
R26
R27
R30
R24R25
D1...4
D9
D8
D5
D7
D6
L10
L1
L2
Q1
Q2
Q3
LV
S
R36
C3
PE
C4
C5
C24
K1
K2
K5
K6
C18
C61
SMD
R61
D61
SMD-Z
ICB1FL03G
Table of Contents
Page
Preliminary Datasheet Version 1.02
4
March 2009
1
Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1
Pin Configuration
PG-DSO-18-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1
Typical operating levels during start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.2
PFC Preconverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3
Typical operating levels during start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.4
Detection of End-of-Life and Rectifier Effect . . . . . . . . . . . . . . . . . . . . . . . .14
3.5
Detection of capacitive mode operating conditions . . . . . . . . . . . . . . . . . . .15
3.6
Interruption of Operation and Restart after Lamp Removal . . . . . . . . . . . . .16
4
State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6.2
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.3
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.3.1
Power Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.3.2
PFC Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.3.2.1
PFC Current Sense (PFCCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.3.2.2
PFC Zero Current Detector (PFCZCD) . . . . . . . . . . . . . . . . . . . . . . . .23
6.3.2.3
PFC Bus Voltage Sense (PFCVS) . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.3.2.4
PFC PWM Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6.3.2.5
PFC Gate Drive (PFCGD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6.3.3
Inverter Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6.3.3.1
Inverter Control (RFRUN, RFPH, RTPH) . . . . . . . . . . . . . . . . . . . . . .25
6.3.3.2
Inverter Low Side Current Sense (LSCS) . . . . . . . . . . . . . . . . . . . . . .25
6.3.3.3
Restart after Lamp Removal (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6.3.3.4
Lamp Voltage Sense (LVS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6.3.3.5
Inverter Low Side Gate Drive (LSGD) . . . . . . . . . . . . . . . . . . . . . . . . .27
6.3.3.6
Inverter High Side Gate Drive (HSGD) . . . . . . . . . . . . . . . . . . . . . . . .28
7
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7.1
Operating Behaviour of a Ballast for a single Fluorescent Lamp . . . . . . . . .29
7.2
Design Equations of a Ballast Application . . . . . . . . . . . . . . . . . . . . . . . . . .30
7.3
Multilamp Ballast Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
8
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Preliminary Datasheet Version 1.02
5
March 2009
ICB1FL03G
Pin Configuration and Description
1
Pin Configuration and Description
1.1
Pin Configuration PG-DSO-18-2
Pin
Symbol
Function
1
LSCS
Low side current sense (inverter)
2
LSGD
Low side gate drive (inverter)
3
VCC
Supply voltage
4
GND
Controller ground
5
PFCGD
PFC gate drive
6
PFCCS
PFC current sense
7
PFCZCD PFC zero current detector
8
PFCVS
PFC voltage sense
9
RFRUN
Set R for run frequency
10
RFPH
Set R for preheating frequency
11
RTPH
Set R for preheating time
12
RES
Restart after lamp removal
13
LVS
Lamp voltage sense
14
n.c.
Not connected
15
n.e.
Not existing
16
n.e.
Not existing
17
HSGND
High side ground
18
HSVCC
High side supply voltage
19
HSGD
High side gate drive
20
HSGND
High side ground
HSVCC
HSGND
RFPH
RES
LVS
PG-DSO-18-2 (300mil)
N.C.
RFRUN
PFCVS
PFCZCD
IC
B
1
F
L0
3
G
GND
HSGD
LSGD
PFCGD
LSCS
PFCCS
VCC
RTPH
N.C.
10
9
8
7
4
2
5
1
6
3
11
12
13
14
17
19
16
20
15
18
1.2
Pin Description
LSCS (Low side current sense, Pin 1)
This pin is directly connected to the shunt resistor
which is located between the Source terminal of the
low-side MOSFET of the inverter and ground.
Internal clamping structures and filtering measures
allow for sensing the Source current of the low-side
inverter MOSFET without additional filter components.
There is a first threshold of 0,8V, which provides a
couple of increasing steps of frequency during ignition
mode, if exceeded by the sensed current signal for a
time longer than 250ns. If the sensed current signal
exceeds a second threshold of 1,6V for longer than
400ns during all operating modes, a latched shut down
of the IC will be the result.
LSGD (Low side gate drive, Pin 2)
The Gate of the low-side MOSFET in a half-bridge
inverter topology is controlled by this pin. There is an
active L-level during UVLO (undervoltage lockout) and
a limitation of the max. H-level at 11V during normal
operation. Turning on the MOSFET softly (with reduced
di
DRAIN
/dt), the Gate drive voltage rises within 220ns
from L-level to H-level. The fall time of the Gate drive
voltage is less than 50ns in order to turn off quickly.
This measure produces different switching speeds
during turn-on and turn-off as it is usually achieved with
a diode in parallel to a resistor in the Gate drive loop. It
is recommended to use a resistor of about 15Ohm
between drive pin and Gate in order to avoid
oscillations and in order to shift the power dissipation of
discharging the Gate capacitance into this resistor. The
dead time between LSGD signal and HSGD signal is
1800ns typically.
VCC (Supply voltage, Pin 3)
This pin provides the power supply of the ground
related section of the IC. There is a turn-on threshold at
14V and an UVLO threshold at 10,5V. Upper supply
voltage level is 17,5V. There is an internal zener diode
clamping Vcc at 16V (2mA typically). The zener current
is internally limited to 5mA max. For higher current
levels an external zener diode is required. Current
consumption during UVLO and during fault mode is
less than 150
µA. A ceramic capacitor close to the
supply and GND pin is required in order to act as a low-
impedance power source for Gate drive and logic
signal currents.
GND (Ground, Pin 4)
This pin is connected to ground and represents the
ground level of the IC for supply voltage, Gate drive
and sense signals.
ICB1FL03G
Pin Configuration and Description
Preliminary Datasheet Version 1.02
6
March 2009
PFCGD (PFC gate drive, Pin 5)
The Gate of the MOSFET in the PFC preconverter
designed in boost topology is controlled by this pin.
There is an active L-level during UVLO and a limitation
of the max. H-level at 11V during normal operation.
Turning on the MOSFET softly (with a reduced di
DRAIN
/
dt), the Gate drive voltage rises within 220ns from L-
level to H-level. The fall time of the Gate voltage is less
than 50ns in order to turn off quickly. A resistor of about
15
Ω between drive pin and Gate in order to avoid
oscillations and in order to shift the power dissipation of
discharging the Gate capacitance into this resistor is
recommended.
The PFC section of the IC controls a boost converter as
a PFC preconverter in discontinuous conduction mode
(DCM). Typically the control starts with Gate drive
pulses with an on-time of 1
µs increasing up to 24µs and
a off-time of 40
µs. As soon as a sufficient ZCD (zero
current detector) signal is available, the operating
mode changes from a fixed frequent operation to an
operation with variable frequency. During rated and
medium load conditions we get an operation with
critical conduction mode (CritCM), that means
triangular shaped currents in the boost converter choke
without gaps when reaching the zero level and variable
operating frequency. During light load (detected by the
internal error amplifier) we get an operation with
discontinuous conduction mode (DCM), that means
triangular shaped currents in the boost converter choke
with gaps when reaching the zero level and variable
operating frequency in order to avoid steps in the
consumed line current.
PFCCS (PFC current sense, Pin 6)
The voltage drop across a shunt resistor located
between Source of the PFC MOSFET and GND is
sensed with this pin. If the level exceeds a threshold of
1V for longer than 260ns the PFC Gate drive is turned
off as long as the ZCD (zero current detector) enables
a new cycle. If there is no ZCD signal available within
40µs after turn-off of the PFC Gate drive, a new cycle
is initiated from an internal start-up timer.
PFCZCD (PFC zero current detection, Pin 7)
This pin senses the point of time when the current
through the boost inductor becomes zero during off-
time of the PFC MOSFET in order to initiate a new
cycle. The moment of interest appears when the
voltage of the separate ZCD winding changes from
positive to negative level which represents a voltage of
zero at the inductor windings and therefore the end of
current flow from lower input voltage level to higher
output voltage level. There is a threshold with
hysteresis, for increasing voltage a level of 1,5V, for
decreasing voltage a level of 0,5V, that detects the
change of inductor voltage. A resistor connected
between ZCD winding and sense input limits the sink
and source current of the sense pin, when the voltage
of the ZCD winding exceeds the internal clamping
levels (6,3V and -2,9V @ 4mA) of the IC.
If the sensed level of the ZCD winding is not sufficient
(e.g. during start-up), an internal start-up timer will
initiate a new cycle every 40
µs after turn-off of the PFC
Gate drive.
PFCVS (PFC voltage sense, Pin 8)
The intermediate circuit voltage (bus voltage) at the
smoothing capacitor is sensed by a resistive divider at
this pin. The internal reference voltage for rated bus
voltage is 2,5V. There are further thresholds at 0,375V
(15% of rated bus voltage), 1,83V (73% of rated bus
voltage) and 2,725V (109% of rated bus voltage) for
detecting open control loop, undervoltage and
overvoltage.
RFRUN (Set R for run frequency, Pin 9)
A resistor from this pin to ground sets the operating
frequency of the inverter during run mode. Typical run
frequency range is 20kHz to 100kHz. The set resistor
R
RFRUN
can be calculated based on the run frequency
f
RUN
according to the equation
RRFRUN
5 10
8ΩHz
⋅
fRUN
-----------------------------
=
RFPH (Set R for preheating frequency, Pin 10)
A resistor from this pin to ground sets together with the
resistor at pin 9 the operating frequency of the inverter
during preheat mode. Typical preheat frequency range
is run frequency (as a minimum) to 150kHz. The set
resistor R
RFPH
can be calculated based on the preheat
frequency f
PH
and the resistor R
RFRUN
according to the
equation:
RRFPH
RRFRUN
fPH RRFRUN
⋅
5 10
8ΩHz
⋅
----------------------------------------
1
–
--------------------------------------------------
=
The total value of both resistors R
RFPH
and R
RFRUN
switched in parallel should not be less than 3,3kOhm.
RTPH (Set R for preheating time, Pin 11)
A resistor from this pin to ground sets the preheating
time of the inverter during preheat mode. A set resistor
range from zero to 18kOhm corresponds to a range of
preheating time from zero to 2000ms subdivided in 127
steps.
RES (Restart after lamp removal, Pin 12)
A source current out of this pin via resistor and filament
to ground monitors the existence of the low-side
filament of the fluorescent lamp for restart after lamp
ICB1FL03G
Pin Configuration and Description
Preliminary Datasheet Version 1.02
7
March 2009
removal. A capacitor from this pin directly to ground
eliminates a superimposed AC voltage that is
generated as a voltage drop across the low-side
filament.
During typical start-up with connected filaments of the
lamp a current source I
RES3
(20µA) is active as long as
Vcc> 10,5V and V
RES
< V
RESC1
(1,6V). An open Low-
side filament is detected, when V
RES
> V
RESC1
. Such a
condition will prevent the start-up of the IC. In addition
the comparator threshold is set to V
RESC2
(1,3V) and
the current source changes to I
RES4
(17µA). Now the
system is waiting for a voltage level lower than V
RESC2
at the RES-Pin that indicates a connected low-side
filament, which will enable the start-up of the IC.
An open high-side filament is detected when there is no
sink current I
LVSsink
(15µA) into the LVS-Pin before the
V
CC
start-up threshold is reached. Under these
conditions the current source at the RES-Pin is I
RES1
(41µA) as long as Vcc> 10,5V and V
RES
< V
RESC1
(1,6V)
and the current source is I
RES2
(34µA) when the
threshold has changed to V
RESC2
(1,3V). In this way the
detection of the high-side filament is mirrored to the
levels on the RES-Pin.
Finally there is a delay function implemented at the
RES-Pin. When a fault condition happens e.g. by an
end-of-life criteria the inverter is turned-off. In some
topologies a transient AC lamp voltage may occur
immediately after shut down of the Gate drives which
could be interpreted as a lamp removal. In order to
generate a delay for the detection of a lamp removal
the capacitor at the RES-Pin is charged by the I
RES3
(20µA) current source up to the threshold V
RESC1
(1,6V)
and discharged by an internal resistor R
RESdisch
, which
operates in parallel to the external sense resistor at this
pin, to the threshold V
RESC3
(0,375V). The total delay
amounts to 32 of these cycles, which corresponds to a
delay time between 30ms to 100ms dependent on
capacitor value.
In addition this pin is applied to sense capacitive mode
operation by use of a further capacitor connected from
this pin to the nod of the high-side MOSFET’s Source
terminal and the low-side MOSFET’s Drain terminal.
The sense capacitor and the filter capacitor are acting
as a capacitive voltage divider that allows for detecting
voltage slopes versus timing sequence and therefore
indicating capacitive mode operation. A typical ratio of
the capacitive divider is 410V/2,2V which results in the
capacitor values e.g. of 10nF and 53pF (56pF).
LVS (Lamp voltage sense, Pin 13)
Before the IC enters the softstart mode this pin has to
sense a sink current above 26
µA (max) which is fed via
resistors from the bus voltage across the high-side
filament of the fluorescent lamp in order to monitor the
existence of the filament for restart after lamp removal.
Together with RES (pin 12) the IC can monitor the lamp
removal of totally 2 lamps in series.
During run mode the lamp voltage is sensed by the AC
current fed into this pin via resistors. Exceeding one of
the two thresholds of either +215
µA or -215µA cycle by
cycle for longer than 610µs, the interpretation of this
event is a failure due to EOL1 (end-of-life). A rectifier
effect (EOL2) is assumed if the ratio of the sequence of
positive and negative amplitudes is above 1,15 or
below 0,85 for longer than 500ms. A failure due to
EOL1 or EOL2 changes the operating mode from run
mode into a latched fault mode that stops the operation
until a reset occurs by lamp removal or by cycle of
power.
EOL1 and EOL2 require an AC current with
zerocrossings at LVS-Pin for a reliable detection. A DC
current at LVS-Pin results in a definite turn-off action
acc. to EOL1 only if the sensed current exceeds the
threshold I
LVSEOLDC
= +/-175µA (typically).
If the functionality of this pin is not required it can be
disabled by connecting this pin to ground.
Not Connected (Pin 14)
This pin is internally not connected.
HSGND (High side ground, Pin 17)
This pin is connected to the Source terminal of the
high-side MOSFET, which is also the nod of high-side
and low-side MOSFET. This pin represents the floating
ground level of the high-side driver and high-side
supply.
HSVCC (High side supply voltage, Pin 18)
This pin provides the power supply of the high-side
ground related section of the IC. An external capacitor
between pin 15 and 16 acts like a floating battery which
has to be recharged cycle by cycle via high voltage
diode from low-side supply voltage during on-time of
the low-side MOSFET. There is an UVLO threshold
with hysteresis that enables high-side section at 10,1V
and disables it at 8,4V.
HSGD (High side gate drive, Pin 19)
The Gate of the high-side MOSFET in a half-bridge
inverter topology is controlled by this pin. There is an
active L-level during UVLO and a limitation of the max.
H-level at 11V during normal operation. The switching
characteristics are the same as described for LSGD
(pin 2). It is recommended to use a resistor of about
15Ohm between drive pin and Gate in order to avoid
oscillations and in order to shift the power dissipation of
discharging the Gate capacitance into this resistor.
The dead time between LSGD signal and HSGD signal
is 1800ns typically.
HSGND (High side ground, Pin 20)
This pin is internally connected with pin 17.
ICB1FL03G
Block Diagram
Preliminary Datasheet Version 1.02
8
March 2009
2
Block Diagram
9
RF
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8
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si
en
t
vo
lta
g
e le
ve
ls
(0
..
2,
5
V
)
5,
0
V
da
c7
da
c4
VC
O
2,
5
V
da
c7
OP
Bi
a
s C
e
ll
1
OP
Bi
a
s C
e
ll
2
OP
Bi
a
s C
e
ll
3
S2
VC
C
OP
1
R1
A
v
= 2
.5
R2
V
RE
F
= 2
,5
0V
8-
B
it A
D
C
C1
V
TH
1
=
2,
725
V
V
TH
2
=
2,
625
V
C2
V
TH
= 1
,8
3
V
C3
V
TH
= 0,
3
75V
VB
U
S
O
V
ER
VO
L
T
AG
E
VB
U
S
U
N
DE
RV
O
LT
A
G
E
VBU
S O
P
E
N
L
OOP
D
E
T
E
C
T
D
IGITA
L L
OOP
C
O
NT
RO
L
PF
C
_
PW
M
_I
N
5µ
s
Bl
a
nk
5µ
s
Bl
a
nk
5µ
s
Bl
a
nk
PF
C
_V
S
SP
I
fo
r
Te
st
Mo
d
e
B
and
ga
p
Vr
e
f=
2.
5
V
Ma
st
er
Cl
o
ck
Di
g
ita
l
se
q
u
en
tia
l
con
tr
o
l
da
c
4
da
c
7
DS
C
OS
C
PH
EN
D
_
H
M
C
LO
CK
_S
P
I
PO
W
ER
_
D
O
W
N
_
L
D1
PF
C
C
S
C1
1.
0V
26
0
ns
Bl
an
k
C2
V
TH
1
=1
,5
V
V
TH
2
=0
,5
V
D2
R1
R2
D3
5,
0V
PF
C
_
ZC
D
PF
C
_
C
L
IM
6
P
F
CCS
7
PF
C
Z
C
D
D1
St
a
rt
-u
p
tim
e
r
of
f-
tim
e
40
µ
s
PF
C
PW
M
&
C
ont
ro
l
PF
C
P
W
M
PF
C
_
PW
M
_I
N
PF
C
G
D
IN
DS
C
PF
C
G
D
Z1
1
G1
T2
T1
D2
D1
VC
C
PF
C
G
D
IN
5
PF
C
G
D
sl
op
e co
n
tro
l
Z1
=1
2
V
0
2
20n
s
t
V
GA
T
E
1,
8
µs
De
ad
tim
e
PW
M
in
ve
rt
er
IN
V
P
W
M
DS
C
LS
HS
C1
C2
0,
8
V
1,
6
V
250n
s
Bl
a
nk
400n
s
Bl
a
nk
IN
V
_
O
C
IG
N
-L
IM
IN
V
C
LI
M
1
LS
C
S
2
LS
G
D
3
4
GND
LS
G
D
Z1
1
G1
T2
T1
D2
D1
VC
C
LS
sl
op
e c
o
nt
rol
Z1
=1
2V
0
220
ns
t
V
GA
T
E
HS
G
D
Z1
1
G1
D2
D1
T1
T2
HS
V
CC
19
18
17
HS
G
D
HS
G
ND
sl
op
e c
on
tr
o
l
Z1
=
12V
02
2
0n
s
t
V
GA
T
E
HS
Co
re
le
ss
T
.
&
G6
C3
C4
D2
D1
VC
C
5V
EN
D
-O
F
-L
IF
E
DQ
&
G2
EN
I1
=
5
µ
A
PO
W
E
R
_D
O
W
N
_
L
H =
o
n
L =
of
f
E
O
L
O
FF_
L
E
O
LAC
TI
VE_
H
L
IN
SER
T
_H
G3
E
N
=
L
=
> S
ta
tus
La
tc
he
d
+
2
15µ
A
-2
15
µA
1
G5
C1
15
µ
A
C2
2,
0
V
D3
1
G1
1
G4
I
LV
S
LV
S
13
LV
S
>
1
,1
5
....
.....=
>
Q
=
H
= 0
,8
5
..1
,1
5
=> Q
= L
<
0
,8
5
…
..
...
=> Q
= H
Q
OF
F
_
H
V
PEAK
(N
+
1)
V
PEAK
(N
)
=
LV
S
T1
N
I
LV
S
P
eak
R
ec
tif
ic
at
io
n
N+
2
N+
1
V
P
EAK
(N
+1
)
V
PE
AK
(N
)
EN
D
-O
F
-L
IF
E
2
C
A
PA
C
IT
IVE
L
O
AD
1
OP
E
N
FIL
A
M
E
N
T
V
B
U
S
O
V
ER
VO
LT
AG
E
IN
V
E
R
T
E
R
OV
E
R
C
U
R
R
E
N
T
Up
&
Do
w
n
C
oun
te
r
m
in.
du
rat
ion
of
e
ffe
ct
:
50
0
m
s
EN
D
-O
F
-L
IF
E
1
C
A
PA
C
IT
IVE
L
O
AD
2
O
P
ER
AT
IO
N
A
BO
V
E
R
UN
F
R
E
Q
UE
NC
Y
1
E
R
RO
R_
LO
G
IC
m
in.
du
rat
io
n of
e
ff
ec
t:
40
0ns
m
in
.dur
at
io
n
of
ef
fe
ct
:
610µ
s
23
5m
s
af
ter
en
d of
p
reh
eat
m
ode
1
R
S
Q
Q
FA
U
L
T
LA
T
C
H
1
P
O
W
E
R_
DO
W
N_
L
LVS_
L
OF
F
_H
LAM
P
_
IN
SER
T_
H
UV
LO
_
L
O
PEN
_
LO
O
P_
L
&
1
1
0,
375
V
1,
3
V
1,
6
V
5,
0
V
T1
3,
2
V
0,
24V
IN
V
1
T1
D
Q
D
Q
G1
D
Q
G2
G3
12
RE
S
5µ
s
Bl
an
k
5µ
s
Bl
an
k
5µ
s
Bl
an
k
I3
=
2
0µ
A
;
V
RE
S
< 1
,6
V
; V
CC
> 1
0,
5
V
; I
LVS
>
15
µA
;
or
du
rin
g r
un
m
ode
I1
=
4
1µ
A
;
V
RE
S
< 1
,6
V
; V
CC
> 1
0,
5
V
; I
LVS
< 1
5
µA
;
I4
=
1
7µ
A
;
V
RE
S
> 1
,6
V
; V
CC
> 1
0,
5
V
; I
LVS
> 1
5
µA
;
I2
=
3
4µ
A
;
V
RE
S
> 1
,6
V
; V
CC
> 1
0,
5
V
; I
LVS
< 1
5
µA
;
I5=
4
1µ
A
&
0
µA
a
lte
rnat
in
g f
o
r 32
c
yc
le
s as
a
de
la
y;
V
DS
C
a
pac
iti
ve
Lo
ad
De
te
ct
io
n
CA
P
LO
A
D
1
V
DS
CA
P
LO
A
D
2
CA
P
L
O
A
D
-R
E
S
La
m
p i
ns
er
t
de
tec
tio
n f
or
VR
E
S
<
1
,6
V
du
ring
p
owe
r dow
n.
D
e
la
y ge
ner
a
tor
fo
r ac
tiv
a
ting
la
mp
re
mo
va
l
a
fte
r f
au
lt l
atc
h
is
s
e
t.
LS
G
D
IN
_
H
HS
G
D
IN
_
H
CA
P
L
O
A
D
1
CA
P
L
O
A
D
2
O
PEN
_F
IL
AM
EN
T
LV
S
LA
M
P
_I
N
S
E
R
T
_H
C1
C4
C3
C5
C2
54
k
Figure 1
Simplified Blockdiagram of ICB1FL03G
ICB1FL03G
Functional Description
Preliminary Datasheet Version 1.02
9
March 2009
3
Functional Description
3.1
Typical operating levels during start-up
The control of the ballast should be able to start the operation within less than 100ms. Therefore the current
consumption of the IC is less than 150µA during UVLO. With a small start-up capacitor (about 1µF) and a power
supply, that feeds within 100µs (charge pump of the inverter) the IC can cover this feature.
As long as the Vcc is less than 10,5V, the current consumption is typically 80µA. Above a Vcc voltage level of
10,5V the IC checks whether the lamp(s) are assembled by detecting a current across the filaments. The low-side
filament is checked from a source current (20µA typ.) out of pin RES, that produces a voltage drop at the sense
resistor, which is connected via low-side filament to ground. An open filament is detected, when the voltage level
at pin RES is above 1,6V. The high-side filament (or the high-side of a series topology) is checked by a current
(15µA typ.) into the LVS pin. An open high-side filament causes a higher source current (41µA / 34µA typ.) out of
pin RES in order to exceed the 1,6V threshold. If the filament is not able to conduct the test current, the control
circuit is disabled. The IC is enabled as soon as a sufficient current is detected across the filament or the supply
voltage drops below the UVLO threshold (10,5V) e.g. by turn-off and turn-on of mains switch.
V
CC
14,0V
10,5V
I
VCC
80µA
5mA
+ QGate
V
RES
1,6V
I
RES
20µA
I
LVS
>15µA
< +/- 2,5mA
3,2V
UVLO
START-UP
HYSTERESIS
IC ACTIVE
SOFTSTART
t
t
t
t
t
<150µA
80µA
<3,2V
20µA
>15µA
Figure 2
Progress of levels during a typical start-up.
When the previous conditions are fulfilled, and Vcc has reached the start-up threshold (14V), there is finally a
check of the Bus voltage. If the level is less than 15% of rated Bus voltage, the IC is waiting in power down mode
until the voltage increases. If the level is above 109% of rated Bus voltage there is no Gate drive, but an active
IC. The supply voltage Vcc will fall below the UVLO threshold and a new start-up attempt is initiated.
As soon as start-up conditions are fulfilled the IC starts driving the inverter with the start-up frequency of 125kHz.
Now the complete control including timers and the PFC control can be set in action. There are current limitation
thresholds for PFC preconverter and ballast inverter equipped with spike filters. The PFC current limitation
interrupts the on-time of the PFC MOSFET if the voltage drop at shunt resistor exceeds 1V and restarts after next
input from ZCD. The inverter current limitation operates with a first threshold of 0,8V which increases the operating
frequency during ignition mode if exceeded. A second threshold is provided at 1,6V that stops the whole control
circuit and latches this event as a fault.
V
CC
14,0V
10,5V
I
VCC
80µA
5mA
+ QGate
V
RES
1,6V
I
RES
20µA
I
LVS
>15µA
3,2V
UVLO
START-UP
HYSTERESIS
IC ACTIVE
SOFTSTART
t
t
t
t
t
< +/- 2,5mA
17µA
34µA
17µA
20µA
16,0V
LS FILAMENT OPEN
HS FILAMENT CLOSED
LAMP REMOVAL
LS + HS OPEN
1,3V
POWER
DOWN
SIGNAL
t
20µA
5,0V
H
V
RES
> 1,3V
80µA
<170µA
>15µA
>15µA
<3,2V
<150µA
ICB1FL03G
Functional Description
Preliminary Datasheet Version 1.02
10
March 2009
Figure 3
Start-up with LS filament broken and subsequent lamp removal.
V
CC
14,0V
10,5V
I
VCC
80µA
5mA
+ QGate
V
RES
1,6V
I
RES
20µA
I
LVS
>15µA
3,2V
UVLO
IC ACTIVE
SOFTSTART
t
t
t
t
t
< +/- 2,5mA
34µA
34µA
17µA
20µA
16,0V
LAMP REMOVAL
LS + HS OPEN
V
RES
> 1,3V
1,3V
POWER
DOWN
SIGNAL
t
41µA
5,0V
H
<3,2V
<170µA
80µA
START-UP
HYSTERESIS
HS FILAMENT OPEN
LS FILAMENT CLOSED
>15µA
1,3V
<150µA
Figure 4
Start-up with HS filament broken and subsequent lamp removal.