AUIRLR3105
V
DSS
55V
R
DS(on)
typ.
30m
max.
37m
I
D
25A
Features
Advanced Planar Technology
Logic-Level Gate Drive
Dynamic dv/dt Rating
Low
On-Resistance
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
Description
Specifically designed for Automotive applications, this Stripe Planar
design of HEXFET® Power MOSFETs utilizes the latest
processing techniques to achieve low on-resistance per silicon
area. This benefit combined with the fast switching speed and
ruggedized device design that HEXFET power MOSFETs are well
known for, provides the designer with an extremely efficient and
reliable device for use in Automotive and a wide variety of other
applications.
1
2015-12-11
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at
www.infineon.com
AUTOMOTIVE GRADE
Symbol Parameter
Max.
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
25
A
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V
18
I
DM
Pulsed Drain Current 100
P
D
@T
C
= 25°C
Maximum Power Dissipation
57
W
Linear Derating Factor
0.38
W/°C
V
GS
Gate-to-Source Voltage
± 16
V
E
AS
Single Pulse Avalanche Energy (Thermally Limited) 61
mJ
E
AS
(Tested)
Single Pulse Avalanche Energy Tested Value 94
I
AR
Avalanche Current
See Fig.15,16, 12a, 12b
A
E
AR
Repetitive Avalanche Energy
mJ
dv/dt
Peak Diode Recovery dv/dt 3.4
V/ns
T
J
Operating Junction and
-55 to + 175
°C
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
300
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless
otherwise specified.
Thermal Resistance
Symbol Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case –––
2.65
°C/W
R
JA
Junction-to-Ambient ( PCB Mount) –––
50
R
JA
Junction-to-Ambient
–––
110
D-Pak
AUIRLR3105
Base part number
Package Type
Standard Pack
Orderable Part Number
Form
Quantity
AUIRLR3105
D-Pak
Tube
75
AUIRLR3105
Tape and Reel Left
3000
AUIRLR3105TRL
G D S
Gate Drain Source
S
G
D
HEXFET
®
Power MOSFET
AUIRLR3105
2
2015-12-11
Notes:
Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
Limited by
T
Jmax ,
starting T
J
= 25°C, L = 0.55mH, R
G
= 25
, I
AS
= 15A, V
GS
=10V.
I
SD
25A, di/dt 290A/µs, V
DD
V
(BR)DSS
, T
J
175°C.
Pulse width
300µs; duty cycle 2%.
C
oss
eff. is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 to 80% V
DSS
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
This value determined from sample failure population, starting 100% tested to this value in production.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994
R
is measured at T
J
approximately 90°C.
Static @ T
J
= 25°C (unless otherwise specified)
Parameter Min.
Typ.
Max.
Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
55
––– –––
V V
GS
= 0V, I
D
= 250µA
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
––– 0.056 ––– V/°C Reference to 25°C, I
D
= 1mA
R
DS(on)
Static Drain-to-Source On-Resistance
––– 30 37
m
V
GS
= 10V, I
D
= 15A
––– 35 43
V
GS
= 5.0V, I
D
= 13A
V
GS(th)
Gate Threshold Voltage
1.0
–––
3.0
V V
DS
= V
GS
, I
D
= 250µA
gfs
Forward Trans conductance
15
––– –––
S V
DS
= 25V, I
D
= 15A
I
DSS
Drain-to-Source Leakage Current
––– ––– 20
µA
V
DS
= 55V, V
GS
= 0V
––– ––– 250
V
DS
= 44V,V
GS
= 0V,T
J
=150°C
I
GSS
Gate-to-Source Forward Leakage
–––
––– 200
nA
V
GS
= 16V
Gate-to-Source Reverse Leakage
–––
––– -200
V
GS
= -16V
Dynamic Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Q
g
Total Gate Charge
–––
–––
20
nC
I
D
= 15A
Q
gs
Gate-to-Source Charge
–––
–––
5.6
V
DS
= 44V
Q
gd
Gate-to-Drain Charge
–––
–––
9.0
V
GS
= 5.0V, See Fig.6 & 13
t
d(on)
Turn-On Delay Time
–––
8.0
–––
ns
V
DD
= 28V
t
r
Rise Time
–––
57
–––
I
D
= 15A
t
d(off)
Turn-Off Delay Time
–––
25
–––
R
G
= 24
t
f
Fall Time
–––
37
–––
R
D
= 5.0
, See Fig. 18
L
D
Internal Drain Inductance
–––
4.5
–––
nH
Between lead,
6mm (0.25in.)
L
S
Internal Source Inductance
–––
7.5
–––
from package
and center of die contact
C
iss
Input Capacitance
–––
710 –––
pF
V
GS
= 0V
C
oss
Output Capacitance
–––
150 –––
V
DS
= 25V
C
rss
Reverse Transfer Capacitance
–––
28
–––
ƒ = 1.0MHz, See Fig. 5
C
oss
Output Capacitance
–––
890 –––
V
GS
= 0V, V
DS
= 1.0V ƒ = 1.0MHz
C
oss
Output Capacitance
–––
110 –––
V
GS
= 0V, V
DS
= 44V ƒ = 1.0MHz
C
oss eff.
Effective Output Capacitance
–––
210 –––
V
GS
= 0V, V
DS
= 0V to 44V
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
––– ––– 25
A
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
––– ––– 100
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
–––
–––
1.3
V T
J
= 25°C,I
S
= 15A, V
GS
= 0V
t
rr
Reverse Recovery Time
–––
52
78
ns T
J
= 25°C ,I
F
= 15A, V
DD
= 28V
Q
rr
Reverse Recovery Charge
–––
82
120
nC di/dt = 100A/µs
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
AUIRLR3105
3
2015-12-11
Fig. 2 Typical Output Characteristics
Fig. 3
Typical Transfer Characteristics
Fig. 4
Typical Forward Trans conductance
Vs. Drain Current
Fig. 1 Typical Output Characteristics
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
2.0V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP 15V
10V
5.0V
3.0V
2.7V
2.5V
2.25V
BOTTOM 2.0V
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
2.0V
20µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
5.0V
3.0V
2.7V
2.5V
2.25V
BOTTOM 2.0V
2.0
4.0
6.0
8.0
VGS, Gate-to-Source Voltage (V)
0.01
0.10
1.00
10.00
100.00
1000.00
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
A
)
TJ = 25°C
TJ = 175°C
VDS = 25V
20µs PULSE WIDTH
0
10
20
30
40
ID, Drain-to-Source Current (A)
0
5
10
15
20
25
30
G
fs
,
F
or
w
ar
d
T
ra
ns
co
nd
uc
ta
nc
e
(S
)
TJ = 25°C
TJ = 175°C
VDS = 25V
20µs PULSE WIDTH
AUIRLR3105
4
2015-12-11
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
0
400
800
1200
1600
C
, C
ap
ac
ita
nc
e
(p
F
)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0
10
20
30
40
QG Total Gate Charge (nC)
0
4
8
12
16
20
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 44V
VDS= 28V
VDS= 11V
ID= 15A
FOR TEST CIRCUIT
SEE FIGURE 13
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
1
10
100
1000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
AUIRLR3105
5
2015-12-11
Fig 10. Normalized On-Resistance
Vs. Temperature
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
25
50
75
100
125
150
175
0
5
10
15
20
25
30
T , Case Temperature ( C)
I
, D
rai
n
C
u
rr
e
n
t (
A
)
°
C
D
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T , Junction Temperature
( C)
R
,
D
rai
n-
to
-S
o
u
rc
e O
n
R
e
si
st
a
n
ce
(N
or
ma
liz
ed)
J
D
S
(on)
°
V
=
I
=
GS
D
10V
25A
0.01
0.1
1
10
0.00001
0.0001
0.001
0.01
0.1
Notes:
1. Duty factor D =
t / t
2. Peak T
= P
x Z
+ T
1
2
J
DM
thJC
C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
T
he
rm
al
R
es
pons
e
(Z
)
1
th
JC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
AUIRLR3105
6
2015-12-11
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive Waveforms
RG
IAS
0.01
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
tp
V
(BR)DSS
I
AS
Fig 13b. Gate Charge Test Circuit
Fig 13a. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 14. Threshold Voltage Vs. Temperature
25
50
75
100
125
150
175
0
20
40
60
80
100
Starting Tj, Junction Temperature
( C)
E
,
S
in
gle
P
uls
e A
val
an
ch
e E
ner
gy
(
m
J)
AS
°
ID
TOP
BOTTOM
6.1A
11A
15A
-75 -50 -25
0
25
50
75 100 125 150 175
TJ , Temperature ( °C )
0.0
0.5
1.0
1.5
2.0
V
G
S
(t
h)
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 250µA
AUIRLR3105
7
2015-12-11
Fig 15. Typical Avalanche Current Vs. Pulse width
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.infineon.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as T
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during
avalanche).
6. I
av
= Allowable avalanche current.
7.
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as
25°C in Figure 15, 16).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
T/ Z
thJC
I
av
= 2
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 16. Maximum Avalanche Energy
Vs. Temperature
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
0.1
1
10
100
1000
A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
10
20
30
40
50
60
70
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 50% Duty Cycle
ID = 15A
AUIRLR3105
8
2015-12-11
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
AUIRLR3105
9
2015-12-11
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/
D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches))
YWWA
XX
XX
Date Code
Y= Year
WW= Work Week
AULR3105
Lot Code
Part Number
IR Logo
D-Pak (TO-252AA) Part Marking Information
AUIRLR3105
10
2015-12-11
D-Pak (TO-252AA) Tape & Reel Information (Dimensions are shown in millimeters (inches))
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
TRR
TRL
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH