AUIRLL024Z
V
DSS
55V
R
DS(on)
typ.
48m
I
D
5.0A
max.
60m
Description
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to
achieve extremely low on-resistance per silicon area. Additional
features of this design are a junction operating temperature, fast
switching speed and improved repetitive avalanche rating . These
features combine to make this design an extremely efficient and
reliable device for use in Automotive applications and a wide
variety of other applications.
Features
Advanced Process Technology
Ultra Low On-Resistance
Logic Level Gate Drive
150°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
1
2015-10-29
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at
www.infineon.com
AUTOMOTIVE GRADE
Symbol Parameter
Max.
Units
I
D
@ T
A
= 25°C
Continuous Drain Current, V
GS
@ 10V 5.0
A
I
D
@ T
A
= 70°C
Continuous Drain Current, V
GS
@ 10V 4.0
I
DM
Pulsed Drain Current 40
P
D
@T
A
= 25°C
Maximum Power Dissipation (PCB Mount) 2.8
W
P
D
@T
A
= 25°C
Maximum Power Dissipation (PCB Mount) 1.0
Linear Derating Factor (PCB Mount) 0.02
W/°C
V
GS
Gate-to-Source Voltage
± 16
V
E
AS
Single Pulse Avalanche Energy (Thermally Limited) 21
E
AS (Tested)
Single Pulse Avalanche Energy (Tested Value) 38
I
AR
Avalanche Current
See Fig. 12a, 12b, 15, 16
A
E
AR
Repetitive Avalanche Energy
mJ
T
J
Operating Junction and
-55 to + 150
°C
T
STG
Storage Temperature Range
mJ
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless
otherwise specified.
Thermal Resistance
Symbol Parameter
Typ.
Max.
Units
°C/W
R
JA
Junction-to-Ambient (PCB Mount, steady state)
–––
45
R
JA
Junction-to-Ambient (PCB Mount, steady state)
–––
120
S
G
SOT-223
AUIRLL024Z
D
Base part number
Package Type
Standard Pack
Orderable Part Number
Form
Quantity
AUIRLL024Z
SOT-223
Tape and Reel
2500
AUIRLL024ZTR
G D S
Gate Drain Source
D
HEXFET
®
Power MOSFET
AUIRLL024Z
2
2015-10-29
Notes:
Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
Limited by T
Jmax
, Starting T
J
= 25°C, L = 4.8mH, R
G
= 25
, I
AS
= 3.A. V
GS
= 10V.Part not recommended for use above this value.
Pulse width
1.0ms; duty cycle 2%.
C
oss eff
. is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
This value determined from sample failure population, starting T
J
= 25°C, L = 4.8mH, R
G
= 25
, I
AS
= 3.0A, V
GS
=10V.
When mounted on 1 inch square copper board.
When mounted on FR-4 board using minimum recommended footprint.
Static @ T
J
= 25°C (unless otherwise specified)
Parameter Min.
Typ.
Max.
Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
55
––– –––
V V
GS
= 0V, I
D
= 250µA
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
––– 0.049 ––– V/°C Reference to 25°C, I
D
= 1mA
R
DS(on)
Static Drain-to-Source On-Resistance
––– 48 60
V
GS
= 10V, I
D
= 3.0A
––– ––– 80
V
GS
= 5.0V, I
D
= 3.0A
––– ––– 100
V
GS
= 4.5V, I
D
= 3.0A
V
GS(th)
Gate Threshold Voltage
1.0
–––
3.0
V V
DS
= V
GS
, I
D
= 250µA
gfs
Forward Trans conductance
7.5
––– –––
S V
DS
= 25V, I
D
= 3.0A
I
DSS
Drain-to-Source Leakage Current
––– ––– 20
µA
V
DS
= 55V, V
GS
= 0V
––– ––– 250
V
DS
= 55V,V
GS
= 0V,T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
–––
––– 200
nA
V
GS
= 16V
Gate-to-Source Reverse Leakage
–––
––– -200
V
GS
= -16V
Dynamic Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Q
g
Total Gate Charge
–––
7.0
11
nC
I
D
= 3.0A
Q
gs
Gate-to-Source Charge
–––
1.5
–––
V
DS
= 44V
Q
gd
Gate-to-Drain Charge
–––
4.0
–––
V
GS
= 5.0V
t
d(on)
Turn-On Delay Time
–––
8.6
–––
ns
V
DD
= 28V
t
r
Rise Time
–––
33
–––
I
D
= 3.0A
t
d(off)
Turn-Off Delay Time
–––
20
–––
R
G
= 56
t
f
Fall Time
–––
15
–––
V
GS
= 5.0V
C
iss
Input Capacitance
–––
380 –––
pF
V
GS
= 0V
C
oss
Output Capacitance
–––
66
–––
V
DS
= 25V
C
rss
Reverse Transfer Capacitance
–––
36
–––
ƒ = 1.0MHz
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
––– ––– 5.0
A
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
––– ––– 40
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
–––
–––
1.3
V T
J
= 25°C,I
S
= 3.0A,V
GS
= 0V
t
rr
Reverse Recovery Time
–––
15
23
ns T
J
= 25°C ,I
F
= 3.0A, V
DD
= 28V
Q
rr
Reverse Recovery Charge
–––
9.1
14
nC di/dt = 100A/µs
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
m
C
oss
Output Capacitance
–––
220 –––
V
GS
= 0V, V
DS
= 1.0V,ƒ = 1.0MHz
C
oss
Output Capacitance
–––
53
–––
V
GS
= 0V, V
DS
= 44V,ƒ = 1.0MHz
C
oss eff.
Effective Output Capacitance
–––
93
–––
V
GS
= 0V, V
DS
= 0V to 44V
AUIRLL024Z
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2015-10-29
Fig. 2 Typical Output Characteristics
Fig. 3
Typical Transfer Characteristics
Fig. 4
Typical Forward Trans conductance
vs. Drain Current
Fig. 1 Typical Output Characteristics
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
I D
, D
ra
in
-t
o
-S
ou
rc
e
C
u
rr
en
t
(A
)
VGS
TOP 10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM
3.0V
60µs PULSE WIDTH
Tj = 25°C
3.0V
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
u
rr
en
t (
A
)
3.0V
60µs PULSE WIDTH
Tj = 150°C
VGS
TOP 10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM
3.0V
0
2
4
6
8
10
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
)
TJ = 25°C
TJ = 150°C
VDS = 10V
60µs PULSE WIDTH
0
2
4
6
8
10
12
ID,Drain-to-Source Current (A)
0
2
4
6
8
10
G
fs
, F
or
w
ar
d
T
ra
ns
co
nd
uc
ta
nc
e
(S
)
TJ = 25°C
TJ = 150°C
VDS = 10V
300µs PULSE WIDTH
AUIRLL024Z
4
2015-10-29
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
C
, C
ap
ac
ita
nc
e(
pF
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0
1
2
3
4
5
6
7
8
QG Total Gate Charge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 44V
VDS= 28V
VDS= 11V
ID= 3.0A
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VSD, Source-to-Drain Voltage (V)
0
1
10
100
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 150°C
VGS = 0V
0.1
1.0
10
100
1000.0
VDS, Drain-to-Source Voltage (V)
0.0001
0.001
0.01
0.1
1
10
100
1000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
TA = 25°C
Tj = 150°C
Single Pulse
DC
AUIRLL024Z
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2015-10-29
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 9. Maximum Drain Current Vs.
Ambient Temperature
Fig 10. Normalized On-Resistance
vs. Temperature
25
50
75
100
125
150
TA , Ambient Temperature (°C)
0
1
2
3
4
5
I D
,
D
ra
in
C
ur
re
nt
(
A
)
-60 -40 -20 0
20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 3.0A
VGS = 10V
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
10
100
T
he
rm
al
R
es
po
ns
e
(
Z
th
JA
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
Ri (°C/W)
i (sec)
5.3396
0.000805
19.771
20.80000
19.881
0.706300
J
J
1
1
2
2
3
3
R
1
R
1
R
2
R
2
R
3
R
3
C
C
Ci=
iRi
Ci=
iRi
AUIRLL024Z
6
2015-10-29
Fig 12a.
Unclamped Inductive Test Circuit
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
tp
V
(BR)DSS
I
AS
RG
IAS
0.01
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
Fig 13b. Gate Charge Test Circuit
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 13a. Basic Gate Charge Waveform
Fig 14.
Threshold Voltage vs. Temperature
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
E
A
S
,
S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
ID
TOP 3.0A
0.80A
BOTTOM 0.69A
-75
-50
-25
0
25
50
75
100 125 150
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
V
G
S
(t
h)
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 250µA
AUIRLL024Z
7
2015-10-29
Fig 15. Typical Avalanche Current vs. Pulse width
Fig 16. Maximum Avalanche Energy
vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.infineon.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as T
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during
avalanche).
6. I
av
= Allowable avalanche current.
7.
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
T/ Z
thJC
I
av
= 2
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
tav (sec)
0.01
0.1
1
10
100
A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming Tj = 25°C due to
avalanche losses
0.01
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
0
5
10
15
20
25
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 3.0A
AUIRLL024Z
8
2015-10-29
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET
®
Power MOSFETs
AUIRLL024Z
9
2015-10-29
SOT-223(TO-261AA) Part Marking Information
SOT-223 (TO-261AA) Package Outline
(Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/
LL024Z
Date Code
Y= Year
WW= Work Week
A= Automotive, Lead Free
AUIRLL024Z
10
2015-10-29
SOT-223(TO-261AA) Tape and Reel (
Dimensions are shown in millimeters (inches)
4.10 (.161)
3.90 (.154)
1.85 (.072)
1.65 (.065)
2.05 (.080)
1.95 (.077)
12.10 (.475)
11.90 (.469)
7.10 (.279)
6.90 (.272)
1.60 (.062)
1.50 (.059)
TYP.
7.55 (.297)
7.45 (.294)
7.60 (.299)
7.40 (.292)
2.30 (.090)
2.10 (.083)
16.30 (.641)
15.70 (.619)
0.35 (.013)
0.25 (.010)
FEED DIRECTION
TR
13.20 (.519)
12.80 (.504)
50.00 (1.969)
MIN.
330.00
(13.000)
MAX.
NOTES :
1. CONTROLLING DIMENSION: MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
3. EACH O330.00 (13.00) REEL CONTAINS 2,500 DEVICES.
3
NOTES :
1. OUTLINE COMFORMS TO EIA-418-1.
2. CONTROLLING DIMENSION: MILLIMETER..
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
15.40 (.607)
11.90 (.469)
18.40 (.724)
MAX.
14.40 (.566)
12.40 (.488)
4
4
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/