AUIRL1404Z Datasheet

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AUIRL1404Z 

AUIRL1404ZS 

AUIRL1404ZL 

Absolute Maximum Ratings 

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress 
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not 
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance 
and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless 
otherwise specified. 

Features 

 Logic 

Level 

 

  Advanced Process Technology 

  Ultra Low On-Resistance 

  175°C Operating Temperature 
 Fast 

Switching 

  Repetitive Avalanche Allowed up to Tjmax 

  Lead-Free, RoHS Compliant 

  Automotive Qualified *  

Description 

Specifically designed for Automotive applications, this HEXFET® Power 
MOSFET utilizes the latest processing techniques to achieve extremely low 
on-resistance per silicon area.  Additional features of this design  are a 175°C 
junction operating temperature, fast switching speed and improved repetitive 
avalanche rating . These features combine to make this design an extremely 
efficient and reliable device for use in Automotive applications and a wide 
variety of other applications. 

 

2015-10-27 

HEXFET® is a registered trademark of Infineon. 
*Qualification standards can be found at 

www.infineon.com

 

AUTOMOTIVE GRADE 

HEXFET

® 

Power MOSFET 

V

DSS 

40V 

R

DS(on)

   typ. 

2.5m

 

              max. 

3.1m

 

I

D (Silicon Limited) 

180A 

I

D (Package Limited) 

160A  

 

TO-220AB 

AUIRL1404Z 

D

2

Pak 

AUIRL1404ZS 

TO-262 

AUIRL1404ZL 

G D  S 

Gate Drain Source 

Base part number 

Package Type 

Standard Pack 

Form 

Quantity 

AUIRL1404Z 

TO-220 

Tube 

50 

AUIRL1404Z 

AUIRL1404ZL 

TO-262  

Tube  

50 

AUIRL1404ZL 

AUIRL1404ZS  

D

2

-Pak    

Tube  

50 

AUIRL1404ZS 

Tape and Reel Left  

800 

AUIRL1404ZSTRL 

Orderable Part Number   

Symbol Parameter 

Max. 

Units 

I

D

 @ T

C

 = 25°C 

Continuous Drain Current, V

GS

 @ 10V (Silicon Limited) 

180 

I

D

 @ T

C

 = 100°C 

Continuous Drain Current, V

GS

 @ 10V (Silicon Limited) 

130 

I

D

 @ T

C

 = 25°C 

Continuous Drain Current, V

GS

 @ 10V (Package Limited) 

160 

I

DM 

Pulsed Drain Current  790 

P

D

 @T

C

 = 25°C 

Maximum Power Dissipation   

200 

  

Linear Derating Factor 

1.3 

W/°C 

V

GS 

Gate-to-Source Voltage 

 ± 16 

E

AS  

Single Pulse Avalanche Energy (Thermally Limited)  190 

mJ  

E

AS 

(tested)

 

Single Pulse Avalanche Energy Tested Value  490 

I

AR 

Avalanche Current  

See Fig.15,16, 12a, 12b   

E

AR 

Repetitive Avalanche Energy  

 

mJ 

T

J  

Operating Junction and 

-55  to + 175 

 

T

STG 

Storage Temperature Range 

  

°C 

  

Soldering Temperature, for 10 seconds (1.6mm from case) 

300 

 

 

Mounting torque, 6-32 or M3 screw 

10 lbf•in (1.1N•m) 

   

Thermal Resistance  

Symbol Parameter 

Typ. 

Max. 

Units 

R

JC

  

Junction-to-Case  

––– 

0.75 

°C/W   

R

CS

 

Case-to-Sink, Flat, Greased Surface  0.50 

––– 

R

JA

  

Junction-to-Ambient  ––– 

62 

R

JA

  

Junction-to-Ambient ( PCB Mount, steady state)   

40 

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AUIRL1404Z/S/L 

 

2015-10-27 

Notes:

 Repetitive rating;  pulse width limited by max. junction temperature. (See fig.11) 

  Limited by T

Jmax, 

starting  T

J

 = 25°C, L = 0.066mH, R

G

 = 25

, I

AS

 = 75A, V

GS

 =10V. Part not recommended for use above this value. 

 Pulse width 

1.0ms; duty cycle  2%. 

  C

oss

 eff.  is a fixed capacitance that gives the same charging time as C

oss

 while V

DS

 is rising from 0 to 80% V

DSS



Limited by T

Jmax

 , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.  

  This value determined from sample failure population 100%  tested to this value in production. 



This is only applied to TO-220AB package.

  When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering 

 

techniques refer to application note #AN-994  



TO-220Pak device will have an Rth value of 0.65°C/W. 



Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 160A. Note that current l

 

imitations arising from heating of the device leads may  occur with some lead mounting arrangements. 

** 

All AC and DC test conditions based on former package limited current of 75A. 

Static @ T

J

 = 25°C (unless otherwise specified) 

  

Parameter Min. 

Typ. 

Max. 

Units 

Conditions 

V

(BR)DSS 

Drain-to-Source Breakdown Voltage 

40 

–––  ––– 

V  V

GS

 = 0V, I

D

 = 250µA 

V

(BR)DSS

/

T

J  

Breakdown Voltage Temp. Coefficient 

–––  0.034  –––  V/°C  Reference to 25°C, I

D

 = 1mA  

R

DS(on) 

   

Static Drain-to-Source On-Resistance    

––– 2.5  3.1 

m



V

GS

 = 10V, I

D

 = 75A **

––– –––  4.7 

V

GS

 = 5.0V, I

D

 = 40A 

V

GS(th) 

Gate Threshold Voltage 

1.4  ––– 

2.7 

V  V

DS

 = V

GS

, I

D

 = 250µA 

gfs 

Forward Trans conductance 

120  –––  ––– 

S  V

DS

 = 10V, I

D

 = 75A** 

I

DSS 

  

Drain-to-Source Leakage Current   

––– –––  20 

µA 

V

DS

 = 40V, V

GS

 = 0V 

––– –––  250 

V

DS

 = 40V,V

GS

 = 0V,T

J

 =125°C 

I

GSS 

  

Gate-to-Source Forward Leakage 

–––  –––  200 

nA   

V

GS

 = 16V 

 

Gate-to-Source Reverse Leakage 

–––  –––  -200 

V

GS

 = -16V 

Dynamic  Electrical Characteristics @ T

J

 = 25°C (unless otherwise specified) 

Q

Total Gate Charge  

––– 

75 

110 

nC  

I

D

 = 75A** 

Q

gs 

Gate-to-Source Charge 

––– 

28 

––– 

V

DS

 = 32V 

Q

gd 

Gate-to-Drain Charge 

––– 

40 

––– 

V

GS

 = 5.0V 

t

d(on) 

Turn-On Delay Time 

––– 

19 

––– 

ns 

V

DD

 = 20V 

t

Rise Time 

–––  180  ––– 

I

D

 = 75A** 

t

d(off) 

Turn-Off Delay Time 

––– 

30 

––– 

R

G

= 4.0



t

Fall Time 

––– 

49 

––– 

V

GS

 = 5.0V  

L

D

 

Internal Drain Inductance 

–––  4.5 

––– 

Between lead, 
6mm (0.25in.) 

L

Internal Source Inductance 

–––  7.5 

––– 

from package 
and center of die contact 

C

iss 

Input Capacitance 

–––  5080  ––– 

pF  

V

GS

 = 0V 

C

oss 

Output Capacitance 

–––  970  ––– 

V

DS

 = 25V 

C

rss 

Reverse Transfer Capacitance 

–––  570  ––– 

ƒ = 1.0MHz 

C

oss 

Output Capacitance 

–––  3310  ––– 

V

GS

 = 0V, V

DS

 = 1.0V ƒ = 1.0MHz 

C

oss 

Output Capacitance 

–––  870  ––– 

V

GS

 = 0V, V

DS

 = 32V ƒ = 1.0MHz 

C

oss eff. 

Effective Output Capacitance  

–––  1280  ––– 

V

GS

 = 0V, V

DS

 = 0V to 32V  

Diode Characteristics  

  

        Parameter 

Min.  Typ.  Max.  Units 

Conditions 

I

  

Continuous Source Current  

––– –––  180 

MOSFET symbol 

(Body Diode) 

showing  the 

I

SM 

  

Pulsed Source Current 

––– –––  790 

integral reverse 

(Body Diode)

p-n junction diode. 

V

SD 

Diode Forward Voltage 

–––  ––– 

1.3 

V  T

J

 = 25°C,I

= 75A**,V

GS

 = 0V 

t

rr  

Reverse Recovery Time  

––– 

26 

39 

ns   T

J

 = 25°C ,I

F

 = 75A** , V

DD

 = 20V    

Q

rr  

Reverse Recovery Charge  

––– 

18 

27 

nC    di/dt = 100A/µs 

t

on 

Forward Turn-On Time 

Intrinsic turn-on time is negligible (turn-on is dominated by L

S

+L

D

nH   

–––  ––– 

5.9 

VGS = 4.5V, ID = 40A 

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AUIRL1404Z/S/L 

 

2015-10-27 

Fig. 2 Typical Output Characteristics 

Fig. 3 

Typical Transfer Characteristics

 

 

Fig. 1 Typical Output Characteristics 

Fig. 4 

Typical Forward Transconductance 

vs. Drain Current 

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

u

rr

en

t (

A

)

VGS

TOP          

10V

7.0V

5.0V

4.5V

4.0V

3.5V

3.3V

BOTTOM

3.0V

60µs PULSE WIDTH

Tj = 25°C

3.0V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

u

rr

en

t (

A

)

60µs PULSE WIDTH

Tj = 175°C

3.0V

VGS

TOP          

10V

7.0V

5.0V

4.5V

4.0V

3.5V

3.3V

BOTTOM

3.0V

2

3

4

5

6

7

8

9

10

VGS, Gate-to-Source Voltage (V)

1.0

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 



)

TJ = 25°C

TJ = 175°C

VDS = 10V

60µs PULSE WIDTH

0

50

100

150

200

ID,Drain-to-Source Current (A)

0

50

100

150

200

G

fs

, F

or

w

ar

T

ra

ns

co

nd

uc

ta

nc

(S

)

TJ = 25°C

TJ = 175°C

VDS = 10V

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AUIRL1404Z/S/L 

 

2015-10-27 

Fig 5.  Typical Capacitance vs. Drain-to-Source Voltage

 

 

Fig 8.  Maximum Safe Operating Area  

Fig 6.  Typical Gate Charge vs. Gate-to-Source Voltage

 

 

Fig. 7 Typical Source-to-Drain Diode 

 Forward Voltage 

1

10

100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

100000

C

, C

ap

ac

ita

nc

e(

pF

)

VGS   = 0V,       f = 1 MHZ

Ciss    = Cgs + Cgd,  C ds SHORTED
Crss    = Cgd 
Coss   = Cds + Cgd

Coss
Crss

Ciss

0

20

40

60

80

 QG  Total Gate Charge (nC)

0.0

1.0

2.0

3.0

4.0

5.0

6.0

V

G

S

, G

at

e-

to

-S

ou

rc

V

ol

ta

ge

 (

V

)

VDS= 32V

VDS= 20V

ID= 75A

0.0

0.5

1.0

1.5

2.0

2.5

VSD, Source-to-Drain Voltage (V)

1.00

10.00

100.00

1000.00

I S

D

, R

ev

er

se

 D

ra

in

 C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 175°C

VGS = 0V

1

10

100

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

10000

I D

,  

D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

1msec

10msec

OPERATION IN THIS AREA 

LIMITED BY R DS(on)

100µsec

Tc = 25°C

Tj = 175°C

Single Pulse

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AUIRL1404Z/S/L 

 

2015-10-27 

 

Fig 11.  Maximum Effective Transient Thermal Impedance, Junction-to-Case  

Fig 9.  Maximum Drain Current vs. 

 Case Temperature 

Fig 10.  Normalized On-Resistance 

vs. Temperature 

25

50

75

100

125

150

175

 TC , Case Temperature (°C)

0

50

100

150

200

I D

,   

D

ra

in

 C

ur

re

nt

 (

A

)

Limited By Package

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

R

D

S

(o

n)

 ,

 D

ra

in

-t

o-

S

ou

rc

O

R

es

is

ta

nc

   

   

   

   

   

   

   

 (

N

or

m

al

iz

ed

)

ID = 75A

VGS = 10V

1E-006

1E-005

0.0001

0.001

0.01

0.1

1

t1 , Rectangular Pulse Duration (sec)

0.0001

0.001

0.01

0.1

1

T

he

rm

al

 R

es

po

ns

Z

 th

JC

 )

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

Ri (°C/W) 

i (sec)

0.212 

0.000213 

0.277 

0.001234 

0.261 

0.021750 

J

J

1

1

2

2

3

3

R

1

R

1

R

2

R

2

R

3

R

3

C

C

Ci= 

iRi

Ci= 

iRi

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AUIRL1404Z/S/L 

 

2015-10-27 

Fig 12c. Maximum Avalanche Energy vs. Drain Current 

R G

IAS

0.01

tp

D.U.T

L

VDS

+

- VDD

DRIVER

A

15V

20V

Fig 12a.  Unclamped Inductive Test Circuit 

tp

V

(BR)DSS

I

AS

Fig 12b.  Unclamped Inductive Waveforms 

Fig 13a.  Gate Charge Test Circuit 

Vds

Vgs

Id

Vgs(th)

Qgs1 Qgs2

Qgd

Qgodr

Fig 13b.   Gate Charge Waveform 

Fig 14. Threshold Voltage vs. Temperature

 

25

50

75

100

125

150

175

Starting TJ , Junction Temperature (°C)

0

100

200

300

400

500

600

700

800

E

A

S

 , 

S

in

gl

P

ul

se

 A

va

la

nc

he

 E

ne

rg

(m

J)

ID

TOP         15A

24A

BOTTOM 75A

-75 -50 -25

0

25 50 75 100 125 150 175 200

TJ , Temperature ( °C )

0.5

1.0

1.5

2.0

2.5

3.0

V

G

S

(t

h)

 G

at

th

re

sh

ol

V

ol

ta

ge

 (

V

)

ID = 250µA

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AUIRL1404Z/S/L 

 

2015-10-27 

Fig 15.   Avalanche Current vs. Pulse width  

Fig 16.  Maximum Avalanche Energy vs. Temperature 

Notes on Repetitive Avalanche Curves , Figures 15, 16: 
(For further info, see AN-1005 at www.infineon.com)
 
1.  Avalanche failures assumption:  
 

Purely a thermal phenomenon and failure occurs at a temperature far in  

 

excess of T

jmax

. This is validated for every part type. 

2.  Safe operation in Avalanche is allowed as long as T

jmax

 is not exceeded. 

3.   Equation below based on circuit and waveforms shown in Figures 12a, 12b. 
4.   P

D (ave) 

= Average power dissipation per single avalanche pulse. 

5.   BV = Rated breakdown voltage (1.3 factor accounts for voltage increase  
 during 

avalanche). 

6.   I

av 

= Allowable avalanche current. 

7. 

T

 = 

Allowable rise in junction temperature, not to exceed

 

T

jmax 

(assumed as  

 

25°C in Figure 14, 15).  

 

t

av = 

Average time in avalanche. 

 

D = Duty cycle in avalanche =  t

av 

·f 

 

Z

thJC

(D, t

av

) = Transient thermal resistance, see Figures 13) 

 

P

D (ave)

 = 1/2 ( 1.3·BV·I

av

) = 

T/ Z

thJC

 

I

av

 = 2

T/ [1.3·BV·Z

th

E

AS (AR) 

= P

D (ave)

·t

av

 

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

1

10

100

A

va

la

nc

he

 C

ur

re

nt

 (

A

)

0.05

Duty Cycle = Single Pulse

0.10

Allowed avalanche Current vs 
avalanche pulsewidth, tav 
assuming   Tj = 25°C due to 

avalanche losses

0.01

25

50

75

100

125

150

175

Starting TJ , Junction Temperature (°C)

0

50

100

150

200

E

A

R

 , 

A

va

la

nc

he

 E

ne

rg

(m

J)

TOP          Single Pulse                
BOTTOM   1.0% Duty Cycle
ID = 75A

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AUIRL1404Z/S/L 

 

2015-10-27 

 

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs 

Fig 18a.  Switching Time Test Circuit 

Fig 18b.  Switching Time Waveforms 

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AUIRL1404Z/S/L 

 

2015-10-27 

TO-220AB Part Marking Information 

TO-220AB Package Outline (Dimensions are shown in millimeters (inches)) 

Note: For the most current drawing please refer to IR website at 

http://www.irf.com/package/

 

YWWA 

XX    

    XX 

Date Code 

Y= Year 

WW= Work Week 

AUIRL1404Z 

Lot Code 

Part Number 

IR Logo 

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AUIRL1404Z/S/L 

10 

 

2015-10-27 

 

Note: For the most current drawing please refer to IR website at 

http://www.irf.com/package/

 

D

2

Pak (TO-263AB) Part Marking Information 

YWWA 

XX    

    XX 

Date Code 

Y= Year 

WW= Work Week 

AUIRL1404ZS 

Lot Code 

Part Number 

IR Logo 

D

2

Pak (TO-263AB) Package Outline (Dimensions are shown in millimeters (inches)) 

Maker
Infineon Technologies
Datasheet PDF Download