10/04/11
www.irf.com
1
HEXFET
®
Power MOSFET
S
D
G
G
D
S
Gate
Drain
Source
AUIRFR4615
AUIRFU4615
DPak
AUIRFR4615
IPAK
AUIRFU4615
V
DSS
150V
R
DS(on)
typ.
34m:
max.
42m
:
I
D
33A
D
S
G
S
D
G
D
Specifically designed for Automotive applications, this
HEXFET
®
Power MOSFET utilizes the latest processing
techniques to achieve extremely low on-resistance per silicon
area. Additional features of this design are a 175°C junction
operating temperature, fast switching speed and improved
repetitive avalanche rating . These features combine to make
this design an extremely efficient and reliable device for use in
Automotive applications and a wide variety of other applications.
Description
Features
l
Advanced Process Technology
l
Low On-Resistance
l
175°C Operating Temperature
l
Fast Switching
l
Repetitive Avalanche Allowed up to Tjmax
l
Lead-Free, RoHS Compliant
l
Automotive Qualified *
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only; and functional operation of the device at these or any other condition beyond those indicated in the
specifications is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Ambient
temperature (T
A
) is 25°C, unless otherwise specified.
AUTOMOTIVE GRADE
HEXFET
®
is a registered trademark of International Rectifier.
*Qualification standards can be found at http://www.irf.com/
Parameter
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V
I
DM
Pulsed Drain Current
c
P
D
@T
C
= 25°C
Maximum Power Dissipation
W
Linear Derating Factor
W/°C
V
GS
Gate-to-Source Voltage
V
E
AS (Thermally limited)
Single Pulse Avalanche Energy d
mJ
I
AR
Avalanche Current c
A
E
AR
Repetitive Avalanche Energy c
mJ
dv/dt
Peak Diode Recovery
e
V/ns
T
J
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Thermal Resistance
Parameter
Typ.
Max.
Units
R
θJC
Junction-to-Case
j
–––
1.045
R
θJA
Junction-to-Ambient (PCB Mount)
i
–––
50
R
θJA
Junction-to-Ambient
–––
110
°C/W
°C
A
144
38
-55 to + 175
± 20
0.96
300(1.6mm from case)
109
See Fig. 14, 15, 22a, 22b,
Max.
33
24
140
PD -
96398A
AUIRFR/U4615
2
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S
D
G
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.51mH
R
G
= 25
Ω, I
AS
= 21A, V
GS
=10V. Part not recommended for use
above this value .
I
SD
≤ 21A, di/dt ≤ 549A/μs, V
DD
≤ V
(BR)DSS
, T
J
≤ 175°C.
Pulse width
≤ 400μs; duty cycle ≤ 2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application
note #AN-994
R
θ
is measured at T
J
approximately 90°C
Static Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage
150
–––
–––
V
ΔV
(BR)DSS
/ΔT
J
Breakdown Voltage Temp. Coefficient
–––
0.19
––– V/°C
R
DS(on)
Static Drain-to-Source On-Resistance
–––
34
42
mΩ
V
GS(th)
Gate Threshold Voltage
3.0
–––
5.0
V
gfs
Forward Transconductance
35
–––
–––
S
I
DSS
Drain-to-Source Leakage Current
–––
–––
20
–––
–––
250
I
GSS
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
R
G(int)
Internal Gate Resistance
–––
2.7
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Q
g
Total Gate Charge
–––
26
Q
gs
Gate-to-Source Charge
–––
8.6
–––
Q
gd
Gate-to-Drain ("Miller") Charge
–––
9.0
–––
Q
sync
Total Gate Charge Sync. (Q
g
- Q
gd
)
–––
17
–––
t
d(on)
Turn-On Delay Time
–––
15
–––
t
r
Rise Time
–––
35
–––
t
d(off)
Turn-Off Delay Time
–––
25
–––
t
f
Fall Time
–––
20
–––
C
iss
Input Capacitance
–––
1750
–––
C
oss
Output Capacitance
–––
155
–––
C
rss
Reverse Transfer Capacitance
–––
40
–––
C
oss
eff. (ER) Effective Output Capacitance (Energy Related)
–––
179
–––
C
oss
eff. (TR) Effective Output Capacitance (Time Related)
–––
382
–––
Diode Characteristics
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
(Body Diode)
I
SM
Pulsed Source Current
(Body Diode)
c
V
SD
Diode Forward Voltage
–––
–––
1.3
V
t
rr
Reverse Recovery Time
–––
70
–––
T
J
= 25°C
V
R
= 100V,
–––
83
–––
T
J
= 125°C
I
F
= 21A
Q
rr
Reverse Recovery Charge
–––
177
–––
T
J
= 25°C
di/dt = 100A/μs
f
–––
247
–––
T
J
= 125°C
I
RRM
Reverse Recovery Current
–––
4.9
–––
A
T
J
= 25°C
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
ns
nC
33
140
μA
nA
nC
ns
pF
A
–––
–––
–––
–––
I
D
= 21A
R
G
= 7.3Ω
V
GS
= 10V
f
V
DD
= 98V
I
D
= 21A, V
DS
=0V, V
GS
= 10V
T
J
= 25°C, I
S
= 21A, V
GS
= 0V
f
integral reverse
p-n junction diode.
Conditions
V
GS
= 0V, I
D
= 250μA
Reference to 25°C, I
D
= 5mA
c
V
GS
= 10V, I
D
= 21A
f
V
DS
= V
GS
, I
D
= 100μA
V
DS
= 150V, V
GS
= 0V
V
DS
= 150V, V
GS
= 0V, T
J
= 125°C
MOSFET symbol
showing the
V
DS
= 75V
Conditions
V
GS
= 10V
f
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz (See Fig.5)
V
GS
= 0V, V
DS
= 0V to 120V
h(See Fig.11)
V
GS
= 0V, V
DS
= 0V to 120V
g
Conditions
V
DS
= 50V, I
D
= 21A
I
D
= 21A
V
GS
= 20V
V
GS
= -20V
AUIRFR/U4615
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3
Qualification Information
†
Moisture Sensitivity Level
D
PAK
MSL1
I-PAK
N/A
RoHS Compliant
Yes
ESD
Machine Model
Class M3(+/- 400V )
†††
AEC-Q101-002
Human Body Model
Class H1B(+/- 1000V )
†††
AEC-Q101-001
Charged Device
Model
Class C5(+/- 2000V )
†††
AEC-Q101-005
Qualification Level
Automotive
(per AEC-Q101)
††
Comments:
This part number(s) passed Automotive
qualification. IR’s Industrial and Consumer qualification
level is granted by extension of the higher Automotive level.
† Qualification standards can be found at International Rectifier’s web site: http//www.irf.com/
†† Exceptions (if any) to AEC-Q101 requirements are noted in the qualification report.
††† Highest passing voltage
AUIRFR/U4615
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
VGS
TOP
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM
5.0V
≤60μs PULSE WIDTH
Tj = 25°C
5.0V
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
VGS
TOP
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM
5.0V
≤60μs PULSE WIDTH
Tj = 175°C
5.0V
2
4
6
8
10
12
14
16
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
I D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VDS = 50V
≤60μs PULSE WIDTH
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
3.0
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = 21A
VGS = 10V
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
100000
C
, C
ap
ac
ita
nc
e
(p
F
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0
5
10
15
20
25
30
35
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= 120V
VDS= 75V
VDS= 30V
ID= 21A
AUIRFR/U4615
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5
Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 11. Typical C
OSS
Stored Energy
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VSD, Source-to-Drain Voltage (V)
1.0
10
100
1000
I S
D
, R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 175°C
VGS = 0V
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
Tc = 25°C
Tj = 175°C
Single Pulse
100μsec
1msec
10msec
DC
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
140
145
150
155
160
165
170
175
180
185
190
V
(B
R
)D
S
S
, D
ra
in
-t
o-
S
ou
rc
e
B
re
ak
do
w
n
V
ol
ta
ge
(
V
)
Id = 5mA
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
50
100
150
200
250
300
350
400
450
500
E
A
S
,
S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
ID
TOP 2.8A
5.3A
BOTTOM 21A
-20
0
20
40
60
80 100 120 140 160
VDS, Drain-to-Source Voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
E
ne
rg
y
(μ
J)
25
50
75
100
125
150
175
TC , Case Temperature (°C)
0
5
10
15
20
25
30
35
40
I D
,
D
ra
in
C
ur
re
nt
(
A
)
AUIRFR/U4615
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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a,22b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
ΔT
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/ Z
thJC
I
av
=
2
DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
he
rm
al
R
es
po
ns
e
(
Z
th
JC
)
°
C
/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
0.1
1
10
100
A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔΤ j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔTj = 150°C and
Tstart =25°C (Single Pulse)
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
120
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 21A
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
Ci i
/Ri
Ci=
τi/Ri
τ
τ
C
τ
4
τ
4
R
4
R
4
Ri (°C/W)
τi (sec)
0.02324 0.000008
0.26212 0.000106
0.50102 0.001115
0.25880 0.005407
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7
Fig. 17 - Typical Recovery Current vs. di
f
/dt
Fig 16. Threshold Voltage vs. Temperature
Fig. 19 - Typical Stored Charge vs. di
f
/dt
Fig. 18 - Typical Recovery Current vs. di
f
/dt
Fig. 20 - Typical Stored Charge vs. di
f
/dt
-75 -50 -25 0
25 50 75 100 125 150 175
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
G
S
(t
h)
, G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = 100μA
ID = 250uA
ID = 1.0mA
ID = 1.0A
0
200
400
600
800
1000
diF /dt (A/μs)
100
200
300
400
500
600
700
800
Q
R
R
(
A
)
IF = 14A
VR = 100V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/μs)
100
200
300
400
500
600
700
800
900
1000
Q
R
R
(
A
)
IF = 21A
VR = 100V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/μs)
0
5
10
15
20
25
30
35
I R
R
M
(
A
)
IF = 21A
VR = 100V
TJ = 25°C
TJ = 125°C
0
200
400
600
800
1000
diF /dt (A/μs)
0
5
10
15
20
25
30
I R
R
M
(
A
)
IF = 14A
VR = 100V
TJ = 25°C
TJ = 125°C
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Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
RG
IAS
0.01
Ω
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
V
GS
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 21.
Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
μF
50K
Ω
.2
μF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
V
DS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
V
GS
AUIRFR/U4615
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
YWWA
XX or XX
Part Number
IR Logo
Lot Code
AUFR4615
Date Code
Y= Year
WW= Work Week
A= Automotive, Lead Free
AUIRFR/U4615
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I-Pak (TO-251AA) Part Marking Information
I-Pak (TO-251AA) Package Outline
( Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
YWWA
XX or XX
Part Number
IR Logo
Lot Code
AUFU4615
Date Code
Y= Year
WW= Work Week
A= Automotive, Lead Free