AUIRF4905S
AUIRF4905L
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless
otherwise specified.
Features
Advanced Planar Technology
P-Channel
MOSFET
Low
On-Resistance
150°C Operating Temperature
Fast
Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
Description
Specifically designed for Automotive applications, this cellular design of
HEXFET® Power MOSFETs utilizes the latest processing techniques to
achieve low on-resistance per silicon area. This benefit combined with the
fast switching speed and ruggedized device design that HEXFET power
MOSFETs are well known for, provides the designer with an extremely
efficient and reliable device for use in Automotive and a wide variety of other
applications.
1
2015-11-13
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at
www.infineon.com
AUTOMOTIVE GRADE
HEXFET
®
Power MOSFET
V
DSS
-55V
R
DS(on)
max.
20m
I
D (Silicon Limited)
-70A
I
D (Package Limited)
-42A
D
2
Pak
AUIRF4905S
S
D
G
G D S
Gate Drain Source
Base part number
Package Type
Standard Pack
Orderable Part Number
Form
Quantity
AUIRF4905L
TO-262
Tube
50
AUIRF4905L
AUIRF4905S
D
2
-Pak
Tube
50
AUIRF4905S
Tape and Reel Left
800
AUIRF4905STRL
Symbol Parameter
Max.
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
-70
A
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
-44
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Package Limited)
-42
I
DM
Pulsed Drain Current -280
P
D
@T
C
= 25°C
Maximum Power Dissipation
170
W
Linear Derating Factor
1.3
W/°C
V
GS
Gate-to-Source Voltage
± 20
V
E
AS
Single Pulse Avalanche Energy (Thermally Limited) 140
mJ
E
AS
(tested)
Single Pulse Avalanche Energy Tested Value 790
I
AR
Avalanche Current
See Fig.15,16, 12a, 12b
A
E
AR
Repetitive Avalanche Energy
mJ
T
J
Operating Junction and
-55 to + 150
T
STG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds (1.6mm from case)
300
Thermal Resistance
Symbol Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case –––
0.75
°C/W
R
JA
Junction-to-Ambient ( PCB Mount, steady state)
40
S
D
G
D
TO-262
AUIRF4905L
AUIRF4905S/L
2
2015-11-13
Notes:
Repetitive rating; pulse width limited by max. junction temperature. (See fig.11)
Limited by T
Jmax,
starting T
J
= 25°C, L = 0.16mH, R
G
= 25
, I
AS
= -42A, V
GS
=-10V. Part not recommended for use above this value.
Pulse width
1.0ms; duty cycle 2%.
C
oss
eff. is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
This value determined from sample failure population, starting T
J
= 25°C, L = 0.08mH, R
G
= 25
, I
AS
= 66A, V
GS
=10V.
This is applied to D
2
Pak, When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994
R
is measured at T
J
of approximately 90°C
Static @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
-55
–––
–––
V V
GS
= 0V, I
D
= -250µA
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
––– -0.054 ––– V/°C Reference to 25°C, I
D
= -1mA
R
DS(on)
Static Drain-to-Source On-Resistance
–––
–––
20
m
V
GS
= -10V, I
D
= -42A
V
GS(th)
Gate Threshold Voltage
-2.0 –––
-4.0
V V
DS
= V
GS
, I
D
= -250µA
gfs
Forward Trans conductance
19
–––
–––
S V
DS
= -25V, I
D
= -42A
I
DSS
Drain-to-Source Leakage Current
––– ––– -25
µA
V
DS
= -55V, V
GS
= 0V
––– ––– -250
V
DS
= -44V,V
GS
= 0V,T
J
=125°C
I
GSS
Gate-to-Source Forward Leakage
–––
––– -100
nA
V
GS
= -20V
Gate-to-Source Reverse Leakage
–––
–––
100
V
GS
= 20V
Dynamic Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Q
g
Total Gate Charge
–––
120
180
nC
I
D
= -42A
Q
gs
Gate-to-Source Charge
–––
32
–––
V
DS
= -44V
Q
gd
Gate-to-Drain Charge
–––
53
–––
V
GS
= -10V
t
d(on)
Turn-On Delay Time
–––
20
–––
ns
V
DD
= -28V
t
r
Rise Time
–––
99
–––
I
D
= -42A
t
d(off)
Turn-Off Delay Time
–––
51
–––
R
G
= 2.6
t
f
Fall Time
–––
64
–––
V
GS
= -10V
L
D
Internal Drain Inductance
–––
4.5
–––
nH
Between lead,
6mm (0.25in.)
L
S
Internal Source Inductance
–––
7.5
–––
from package
and center of die contact
C
iss
Input Capacitance
––– 3500 –––
pF
V
GS
= 0V
C
oss
Output Capacitance
––– 1250 –––
V
DS
= -25V
C
rss
Reverse Transfer Capacitance
–––
450
–––
ƒ = 1.0MHz
C
oss
Output Capacitance
––– 4620 –––
V
GS
= 0V,V
DS
= -1.0V ƒ = 1.0MHz
C
oss
Output Capacitance
–––
940
–––
V
GS
= 0V,V
DS
= -44V ƒ = 1.0MHz
C
oss eff.
Effective Output Capacitance
––– 1530 –––
V
GS
= 0V, V
DS
= 0V to -44V
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
––– ––– -42
A
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
––– ––– -280
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
–––
–––
-1.3
V T
J
= 25°C,I
S
= -42A,V
GS
= 0V
t
rr
Reverse Recovery Time
–––
61
92
ns T
J
= 25°C ,I
F
= -42A , V
DD
= -28V
Q
rr
Reverse Recovery Charge
–––
150
220
nC di/dt = 100A/µs
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
AUIRF4905S/L
3
2015-11-13
Fig. 2 Typical Output Characteristics
Fig. 3
Typical Transfer Characteristics
Fig. 1 Typical Output Characteristics
Fig. 4
Typical Forward Trans conductance
vs. Drain Current
0.1
1
10
100
1000
-VDS, Drain-to-Source Voltage (V)
1
10
100
1000
-I
D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
60µs PULSE WIDTH
Tj = 25°C
-4.5V
VGS
TOP -15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM
-4.5V
0.1
1
10
100
1000
-VDS, Drain-to-Source Voltage (V)
1
10
100
1000
-I
D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
60µs PULSE WIDTH
Tj = 150°C
-4.5V
VGS
TOP -15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM
-4.5V
3
4
5
6
7
8
9
10 11 12 13 14
-VGS, Gate-to-Source Voltage (V)
0.1
1.0
10.0
100.0
1000.0
-I
D
, D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
)
VDS = -25V
60µs PULSE WIDTH
TJ = 25°C
TJ = 150°C
0
20
40
60
80
-ID, Drain-to-Source Current (A)
0
10
20
30
40
G
fs
,
F
or
w
ar
d
T
ra
ns
co
nd
uc
ta
nc
e
(S
)
TJ = 25°C
TJ = 150°C
VDS = -10V
380µs PULSE WIDTH
AUIRF4905S/L
4
2015-11-13
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
1
10
100
-VDS, Drain-to-Source Voltage (V)
0
1000
2000
3000
4000
5000
6000
7000
C
, C
ap
ac
ita
nc
e
(p
F
)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0
40
80
120
160
200
QG Total Gate Charge (nC)
0
4
8
12
16
20
-V
G
S
, G
at
e-
to
-S
ou
rc
e
V
ol
ta
ge
(
V
)
VDS= -44V
VDS= -28V
VDS= -11V
ID= -42A
0.0
0.4
0.8
1.2
1.6
2.0
-VSD, Source-to-Drain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
-I
S
D
,
R
ev
er
se
D
ra
in
C
ur
re
nt
(
A
)
TJ = 25°C
TJ = 150°C
VGS = 0V
0
1
10
100
-VDS , Drain-toSource Voltage (V)
1
10
100
1000
-I
D
,
D
ra
in
-t
o-
S
ou
rc
e
C
ur
re
nt
(
A
)
Tc = 25°C
Tj = 150°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
DC
LIMITED BY PACKAGE
AUIRF4905S/L
5
2015-11-13
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Normalized On-Resistance
vs. Temperature
25
50
75
100
125
150
TC , Case Temperature (°C)
0
20
40
60
80
-I
D
,
D
ra
in
C
ur
re
nt
(
A
)
LIMITED BY PACKAGE
-60 -40 -20
0
20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
R
D
S
(o
n)
,
D
ra
in
-t
o-
S
ou
rc
e
O
n
R
es
is
ta
nc
e
(
N
or
m
al
iz
ed
)
ID = -42A
VGS = -10V
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
T
he
rm
al
R
es
po
ns
e
(
Z
th
JC
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
J
J
1
1
2
2
3
3
R
1
R
1
R
2
R
2
R
3
R
3
C
C
Ci=
iRi
Ci=
iRi
Ri (°C/W)
i (sec)
0.1165
0.000068
0.2608
0.014811
0.3734
0.002347
AUIRF4905S/L
6
2015-11-13
Fig 12c. Maximum Avalanche Energy vs. Drain Current
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 13a. Gate Charge Test Circuit
Fig 13b. Gate Charge Waveform
Fig 14. Threshold Voltage vs. Temperature
25
50
75
100
125
150
Starting TJ, Junction Temperature (°C)
0
100
200
300
400
500
600
E
A
S
,
S
in
gl
e
P
ul
se
A
va
la
nc
he
E
ne
rg
y
(m
J)
ID
TOP
-17A
-30A
BOTTOM
-42A
-75
-50
-25
0
25
50
75
100 125 150
TJ , Temperature ( °C )
2.0
2.4
2.8
3.2
3.6
-V
G
S
(t
h)
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = -250µA
AUIRF4905S/L
7
2015-11-13
Fig 15. Avalanche Current vs. Pulse width
Fig 16. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.infineon.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as T
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during
avalanche).
6. I
av
= Allowable avalanche current.
7.
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
T/ Z
thJC
I
av
= 2
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
0.1
1
10
100
1000
A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
0
40
80
120
160
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = -42A
AUIRF4905S/L
8
2015-11-13
Fig 17. Peak Diode Recovery dv/dt Test Circuit for P-Channel HEXFET® Power MOSFETs
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
AUIRF4905S/L
9
2015-11-13
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/
D
2
Pak (TO-263AB) Part Marking Information
YWWA
XX
XX
Date Code
Y= Year
WW= Work Week
AUIRF4905S
Lot Code
Part Number
IR Logo
D
2
Pak (TO-263AB) Package Outline (Dimensions are shown in millimeters (inches))
AUIRF4905S/L
10
2015-11-13
TO-262 Part Marking Information
YWWA
XX
XX
Date Code
Y= Year
WW= Work Week
AUIRF4905L
Lot Code
Part Number
IR Logo
TO-262 Package Outline (Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at
http://www.irf.com/package/