AUIRF1404
V
DSS
40V
R
DS(on)
typ.
3.5m
max.
4.0m
I
D (Silicon Limited)
202A
I
D (Package Limited)
160A
Features
Advanced Planar Technology
Low
On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast
Switching
Fully Avalanche Rated
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
Description
Specifically designed for Automotive applications, this Stripe
Planar design of HEXFET
®
Power MOSFETs utilizes the latest
processing techniques to achieve low on-resistance per silicon
area. This benefit combined with the fast switching speed and
ruggedized device design that HEXFET
®
power MOSFETs are
well known for, provides the designer with an extremely efficient
and reliable device for use in Automotive and a wide variety of
other applications.
1
2015-9-30
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at
www.infineon.com
AUTOMOTIVE GRADE
Symbol Parameter
Max.
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
202
A
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
143
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Package Limited)
160
I
DM
Pulsed Drain Current 808
P
D
@T
C
= 25°C
Maximum Power Dissipation
333
W
Linear Derating Factor
2.2
W/°C
V
GS
Gate-to-Source Voltage
± 20
V
E
AS
Single Pulse Avalanche Energy (Thermally Limited) 620
mJ
I
AR
Avalanche Current
See Fig.15,16, 12a, 12b
A
E
AR
Repetitive Avalanche Energy
mJ
T
J
Operating Junction and
-55 to + 175
T
STG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds (1.6mm from case)
300
Mounting torque, 6-32 or M3 screw
10 lbf•in (1.1N•m)
dv/dt
Peak Diode Recovery dv/dt 1.5
V/ns
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless
otherwise specified.
Thermal Resistance
Symbol Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case –––
0.45
°C/W
R
CS
Case-to-Sink, Flat, Greased Surface
0.50
–––
R
JA
Junction-to-Ambient
–––
62
TO-220AB
AUIRF1404
S
D
G
Base part number
Package Type
Standard Pack
Form
Quantity
AUIRF1404
TO-220
Tube
50
AUIRF1404
Orderable Part Number
G D S
Gate Drain Source
AUIRF1404
2
2015-9-30
Notes:
Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
starting T
J
= 25°C, L = 85
H, R
G
= 25
, I
AS
= 121A, V
GS
=10V. (See fig. 12)
I
SD
121A, di/dt 130A/µs, V
DD
V
(BR)DSS
, T
J
175°C.
Pulse width
400µs; duty cycle 2%.
C
oss
eff. is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 160A.
R
is measured at T
J
of approximately 90°C.
Static @ T
J
= 25°C (unless otherwise specified)
Parameter Min.
Typ.
Max.
Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
40
––– –––
V V
GS
= 0V, I
D
= 250µA
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
––– 0.039 ––– V/°C Reference to 25°C, I
D
= 1mA
R
DS(on)
Static Drain-to-Source On-Resistance
–––
3.5
4.0
m
V
GS
= 10V, I
D
= 121A
V
GS(th)
Gate Threshold Voltage
2.0
–––
4.0
V V
DS
= V
GS
, I
D
= 250µA
gfs
Forward Trans conductance
76
––– –––
S V
DS
= 25V, I
D
= 121A
I
DSS
Drain-to-Source Leakage Current
––– ––– 20
µA
V
DS
=40 V, V
GS
= 0V
––– ––– 250
V
DS
=32V,V
GS
= 0V,T
J
=150°C
I
GSS
Gate-to-Source Forward Leakage
–––
––– 100
nA
V
GS
= 20V
Gate-to-Source Reverse Leakage
–––
––– -100
V
GS
= -20V
Dynamic Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Q
g
Total Gate Charge
–––
131 196
nC
I
D
= 121A
Q
gs
Gate-to-Source Charge
–––
36
–––
V
DS
= 32V
Q
gd
Gate-to-Drain Charge
–––
37
56
V
GS
= 10V
t
d(on)
Turn-On Delay Time
–––
17
–––
ns
V
DD
= 20V
t
r
Rise Time
–––
190 –––
I
D
= 121A
t
d(off)
Turn-Off Delay Time
–––
46
–––
R
G
= 2.5
t
f
Fall Time
–––
33
–––
R
D
= 0.2
L
D
Internal Drain Inductance
–––
4.5
–––
nH
Between lead,
6mm (0.25in.)
L
S
Internal Source Inductance
–––
7.5
–––
from package
and center of die contact
C
iss
Input Capacitance
––– 5669 –––
pF
V
GS
= 0V
C
oss
Output Capacitance
––– 1659 –––
V
DS
= 25V
C
rss
Reverse Transfer Capacitance
–––
223 –––
ƒ = 1.0MHz, See Fig. 5
C
oss
Output Capacitance
––– 6205 –––
V
GS
= 0V, V
DS
= 1.0V ƒ = 1.0MHz
C
oss
Output Capacitance
––– 1467 –––
V
GS
= 0V, V
DS
= 32V ƒ = 1.0MHz
C
oss eff.
Effective Output Capacitance
––– 2249 –––
V
GS
= 0V, V
DS
= 0V to 32V
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
––– ––– 202
A
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
––– ––– 808
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
–––
–––
1.5
V T
J
= 25°C,I
S
= 121A,V
GS
= 0V
t
rr
Reverse Recovery Time
–––
78
117
ns T
J
= 25°C ,I
F
= 121A
Q
rr
Reverse Recovery Charge
–––
163 245
nC di/dt = 100A/µs
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
AUIRF1404
3
2015-9-30
Fig. 2 Typical Output Characteristics
Fig. 3
Typical Transfer Characteristics
Fig. 4 Normalized On-Resistance
vs. Temperature
Fig. 1 Typical Output Characteristics
1
10
100
1000
0.1
1
10
100
20µs PULSE WIDTH
T = 25 C
J
°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I
,
D
ra
in
-to
-S
o
u
rc
e
C
u
rr
e
n
t (A
)
DS
D
4.5V
1
10
100
1000
0.1
1
10
100
20µs PULSE WIDTH
T = 175 C
J
°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , D
ra
in
-to
-S
o
u
rc
e
C
u
rr
e
n
t (
A
)
DS
D
4.5V
10
100
1000
4
5
6
7
8
9
10
11
12
V = 25V
20µs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I
, D
ra
in
-to
-S
o
u
rc
e
C
u
rr
e
n
t (A
)
GS
D
T = 25 C
J
°
T = 175 C
J
°
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
T , Junction Temperature ( C)
R
,
D
ra
in
-to
-S
o
u
rc
e
O
n
R
e
sis
ta
n
ce
(N
or
m
a
liz
ed)
J
DS
(o
n
)
°
V
=
I =
GS
D
10V
202A
AUIRF1404
4
2015-9-30
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
0
2000
4000
6000
8000
10000
C
, C
ap
ac
ita
nc
e(
pF
)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0
50
100
150
200
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V
,
G
a
te
-t
o
-S
o
u
rc
e
V
o
lta
g
e
(
V
)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
121A
V
= 20V
DS
V
= 32V
DS
0.1
1
10
100
1000
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V ,Source-to-Drain Voltage (V)
I
, R
e
ve
rs
e
D
ra
in
C
u
rr
e
n
t (A
)
SD
SD
V = 0 V
GS
T = 25 C
J
°
T = 175 C
J
°
1
10
100
1000
10000
1
10
100
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
Single Pulse
T
T
= 175 C
= 25 C
°
°
J
C
V , Drain-to-Source Voltage (V)
I , D
ra
in
C
ur
re
nt (
A
)
I , D
ra
in
C
ur
re
nt (
A
)
DS
D
10us
100us
1ms
10ms
AUIRF1404
5
2015-9-30
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
25
50
75
100
125
150
175
TC , Case Temperature (°C)
0
50
100
150
200
250
I D
,
D
ra
in
C
ur
re
nt
(
A
)
Limited By Package
0.001
0.01
0.1
1
0.00001
0.0001
0.001
0.01
0.1
Notes:
1. Duty factor D =
t / t
2. Peak T = P
x Z
+ T
1
2
J
DM
thJC
C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Th
erm
al R
esp
on
se
(Z
)
1
th
JC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
AUIRF1404
6
2015-9-30
Fig 14.
Threshold Voltage vs. Temperature
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive Waveforms
R G
IAS
0.01
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
tp
V
(BR)DSS
I
AS
Fig 13b. Gate Charge Test Circuit
Fig 13a. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
25
50
75
100
125
150
175
0
300
600
900
1200
1500
Starting T , Junction Temperature
( C)
E ,
S
ingl
e P
ul
se Av
ala
nc
he Ener
gy (
m
J)
J
AS
°
ID
TOP
BOTTOM
49A
101A
121A
-75
-50
-25
0
25
50
75
100 125 150
TJ , Temperature ( °C )
1.0
2.0
3.0
4.0
-V
G
S
(t
h)
G
at
e
th
re
sh
ol
d
V
ol
ta
ge
(
V
)
ID = -250µA
AUIRF1404
7
2015-9-30
Fig 15. Typical Avalanche Current vs. Pulse width
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.infineon.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as T
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during
avalanche).
6. I
av
= Allowable avalanche current.
7.
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as
25°C in Figure 15, 16).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
T/ Z
thJC
I
av
= 2
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 16. Maximum Avalanche Energy
vs. Temperature
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
1
10
100
1000
A
va
la
nc
he
C
ur
re
nt
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
Tj = 25°C due to
avalanche losses
0.01
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
50
100
150
200
250
300
350
400
E
A
R
,
A
va
la
nc
he
E
ne
rg
y
(m
J)
TOP Single Pulse
BOTTOM 10% Duty Cycle
ID = 121A
AUIRF1404
8
2015-9-30
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
AUIRF1404
9
2015-9-30
TO-220AB package is not recommended for Surface Mount Application.
TO-220AB Part Marking Information
YWWA
XX
XX
Date Code
Y= Year
WW= Work Week
AUF1404
Lot Code
Part Number
IR Logo
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
AUIRF1404
10
2015-9-30
Qualification Information
Qualification Level
Automotive
(per AEC-Q101)
Comments: This part number(s) passed Automotive qualification. Infineon’s
Industrial and Consumer qualification level is granted by extension of the higher
Automotive level.
Moisture Sensitivity Level
TO-220AB
N/A
ESD
Machine Model
Class M4 (+/- 425V)
†
AEC-Q101-002
Human Body Model
Class H2 (+/- 4000V)
†
AEC-Q101-001
Charged Device Model
Class C5 (+/- 1125V)
†
AEC-Q101-005
RoHS Compliant
Yes
Published by
Infineon Technologies AG
81726 München, Germany
©
Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (
www.infineon.com
).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
Revision History
Date Comments
9/30/2015
Updated datasheet with corporate template.
Corrected typo on IDSS test condition on page 2.
Updated Package outline on page 9.
† Highest passing voltage.