2013-2015 Microchip Technology Inc.
DS00001987A-page 1
Highlights
• Single-Chip Ethernet Physical Layer Transceiver
(PHY)
• Compliant with Energy Efficient Ethernet 802.3az
• Cable diagnostic support
• Wake on LAN (WoL) support
• Comprehensive flexPWR technology
- Flexible power management architecture
- LVCMOS Variable I/O voltage range: +1.8 V to
+3.3 V
- Integrated 1.2 V regulator with disable feature
• HP Auto-MDIX support
• Small footprint 32-pin VQFN, RoHS-compliant
package (5 x 5 x 0.9 mm height)
• Deterministic 100 Mb internal loopback latency
(MII Mode)
Target Applications
• Set-Top Boxes
• Networked Printers and Servers
• Test Instrumentation
• LAN on Motherboard
• Embedded Telecom Applications
• Video Record/Playback Systems
• Cable Modems/Routers
• DSL Modems/Routers
• Digital Video Recorders
• IP and Video Phones
• Wireless Access Points
• Digital Televisions
• Digital Media Adapters/Servers
• Gaming Consoles
• POE Applications
(Refer to Microchip Application Note 17.18)
Key Benefits
• High-performance 10/100 Ethernet transceiver
- Compliant with IEEE802.3/802.3u (Fast Ethernet)
- Compliant with ISO 802-3/IEEE 802.3
(10BASE-T)
- Compliant with Energy Efficient Ethernet IEEE
802.3az
- Loop-back modes
- Auto-negotiation
- Automatic polarity detection and correction
- Link status change wake-up detection
- Vendor specific register functions
- Supports both MII and the reduced pin count RMII
interfaces
• Power and I/Os
- Various low power modes
- Integrated power-on reset circuit
- Two status LED outputs
- May be used with a single 3.3 V supply
• Additional Features
- Ability to use a low cost 25 MHz crystal for
reduced BOM
• Packaging
- 32-pin VQFN (5 x 5 mm), RoHS-compliant
package with MII and RMII
• Environmental
- Commercial temperature range (0°C to +70°C)
- Industrial temperature range (-40°C to +85°C)
LAN8740A/LAN8740Ai
Small Footprint MII/RMII 10/100 Energy Efficient Ethernet
Transceiver with HP Auto-MDIX and flexPWR
®
Technology
LAN8740A/LAN8740Ai
DS00001987A-page 2
2013-2015 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
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2013-2015 Microchip Technology Inc.
DS00001987A-page 3
LAN8740A/LAN8740Ai
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 6
3.0 Functional Description .................................................................................................................................................................. 17
4.0 Register Descriptions .................................................................................................................................................................... 58
5.0 Operational Characteristics ......................................................................................................................................................... 113
6.0 Package Outline .......................................................................................................................................................................... 127
Appendix A: Revision History ............................................................................................................................................................ 130
The Microchip Web Site .................................................................................................................................................................... 133
Customer Change Notification Service ............................................................................................................................................. 133
Customer Support ............................................................................................................................................................................. 133
Product Identification System ........................................................................................................................................................... 134
LAN8740A/LAN8740Ai
DS00001987A-page 4
2013-2015 Microchip Technology Inc.
1.0
INTRODUCTION
1.1
General Terms and Conventions
The following is a list of the general terms used throughout this document:
1.2
General Description
The LAN8740A/LAN8740Ai is a low-power 10BASE-T/100BASE-TX physical layer (PHY) transceiver with variable I/O
voltage that is compliant with the IEEE 802.3, 802.3u, and 802.3az (Energy Efficient Ethernet) standards. Energy Effi-
cient Ethernet (EEE) support results in significant power savings during low link utilizations.
The LAN8740A/LAN8740Ai supports communication with an Ethernet MAC via a standard MII (IEEE 802.3u)/RMII inter-
face. It contains a full-duplex 10-BASE-T/100BASE-TX transceiver and supports 10 Mbps (10BASE-T) and 100 Mbps
(100BASE-TX) operation. The LAN8740A/LAN8740Ai implements auto-negotiation to automatically determine the best
possible speed and duplex mode of operation. HP Auto-MDIX support allows the use of direct connect or cross-over
LAN cables. Integrated Wake on LAN (WoL) support provides a mechanism to trigger an interrupt upon reception of a
perfect DA, broadcast, magic packet, or wakeup frame.
The LAN8740A/LAN8740Ai supports both IEEE 802.3-2005 compliant and vendor-specific register functions. However,
no register access is required for operation. The initial configuration may be selected via the configuration pins as
described in
Section 3.7, "Configuration Straps"
. Register-selectable configuration options may be used to further define
the functionality of the transceiver.
The LAN8740A/LAN8740Ai can be programmed to support wake-on-LAN at the physical layer, allowing detection of
configurable Wake-up Frame and Magic packets. This feature allows filtering of packets at the PHY layer, without requir-
ing MAC intervention. Additionally, the LAN8740A/LAN8740Ai supports cable diagnostics which allow the device to
identify opens/shorts and their location on the cable via vendor-specific registers.
Per IEEE 802.3-2005 standards, all digital interface pins are tolerant to 3.6 V. The device can be configured to operate
on a single 3.3 V supply utilizing an integrated 3.3 V to 1.2 V linear regulator. The linear regulator may be optionally
disabled, allowing usage of a high efficiency external regulator for lower system power dissipation.
BYTE
8 bits
FIFO
First In First Out buffer; often used for elasticity buffer
MAC
Media Access Controller
MII
Media Independent Interface
RMII™
Reduced Media Independent Interface
N/A
Not Applicable
X
Indicates that a logic state is “don’t care” or undefined.
RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must always be zero
for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits.
Unless otherwise noted, do not read or write to reserved addresses.
SMI
Serial Management Interface
2013-2015 Microchip Technology Inc.
DS00001987A-page 5
LAN8740A/LAN8740Ai
The LAN8740A/LAN8740Ai is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature
range versions. A typical system application is shown in
Figure 1-1
.
Figure 1-2
provides an internal block diagram of the
device.
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
FIGURE 1-2:
ARCHITECTURAL OVERVIEW
LAN8740A/
LAN8740Ai
10/100
Ethernet
MAC
MII/
RMII
Mode
LED
Transformer
Crystal or
Clock
Oscillator
MDI
RJ45
RM
II/
M
II Lo
g
ic
Interrupt
Generator
LEDs
PLL
Receiver
DSP System:
Clock
Data Recovery
Equalizer
Squeltch
& Filters
Analog-to-
Digital
10M RX
Logic
100M RX
Logic
100M PLL
10M PLL
Transmitter
10M
Transmitter
100M
Transmitter
10M TX
Logic
100M TX
Logic
Central Bias
PHY Address
Latches
LAN8740A/LAN8740Ai
RBIAS
LED1
nINT
XTAL2
XTAL1/CLKIN
LED2
Management
Control
Mode Control
Reset Control
MDIX
Control
HP Auto-MDIX
RXP/RXN
TXP/TXN
TXD[0:3]
TXEN
TXER
TXCLK
RXD[0:3]
RXDV
RXER
RXCLK
CRS
COL/CRS_DV
MDC
MDIO
Auto-
Negotiation
RMIISEL
nRST
MODE[0:2]
SMI
PHYAD[0:2]
WoL
LAN8740A/LAN8740Ai
DS00001987A-page 6
2013-2015 Microchip Technology Inc.
2.0
PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
32-VQFN PIN ASSIGNMENTS (TOP VIEW)
Note:
When a lower case “n” is used at the beginning of the signal name, it indicates that the signal is active low.
For example, nRST indicates that the reset signal is active low.
Note:
The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the buffer types
is provided in
Section 2.2
.
Note: Exposed pad (VSS) on bottom of package must be connected to ground.
MDIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
RXD3/PHYAD2
RXCLK/PHYAD1
VDDCR
XTAL1/CLKIN
XTAL2
LED1/nINT/nPME/REGOFF
LED2/nINT/nPME/nINTSEL
VDD2A
TXD2
TXD1
TXD0
TXEN
TXCLK
nRST
nINT/TXER/TXD4
MDC
TX
D
3
RX
D
V
VDD1A
TX
N
TX
P
RX
N
RX
P
RB
IA
S
COL/CR
S_
DV/MODE2
CR
S
R
XER/RXD4/P
HYA
D
0
VDD
IO
RXD
0/MODE0
RXD
1/MODE1
RX
D
2/
nPM
E/
RM
IISE
L
L A N 8740A /
L A N 8740A i
2013-2015 Microchip Technology Inc.
DS00001987A-page 7
LAN8740A/LAN8740Ai
TABLE 2-1:
MII/RMII SIGNALS
Num Pins
Name
Symbol
Buffer Type
Description
1
Transmit
Data 0
TXD0
VIS
The MAC transmits data to the transceiver using
this signal in all modes.
1
Transmit
Data 1
TXD1
VIS
The MAC transmits data to the transceiver using
this signal in all modes.
1
Transmit
Data 2
(MII Mode)
TXD2
VIS
The MAC transmits data to the transceiver using
this signal in MII mode.
Note:
This signal must be grounded in RMII
mode.
1
Transmit
Data 3
(MII Mode)
TXD3
VIS
The MAC transmits data to the transceiver using
this signal in MII mode.
Note:
This signal must be grounded in RMII
mode.
1
Interrupt Out-
put
nINT
VOD8
(PU)
Active low interrupt output. Place an external resis-
tor pull-up to VDDIO.
Note:
The nINT signal can be optionally con-
figured to output on the LED1 or LED2
pins. Refer to
Section 3.6, "Interrupt
Management"
for additional details on
device interrupts.
Note:
Refer to
Section 3.8.1.6, "nINTSEL and
LED2 Polarity Selection"
for details on
how the nINTSEL configuration strap is
used to determine the function of this
pin.
Transmit Error
(MII Mode)
TXER
VIS
When driven high, the 4B/5B encode process sub-
stitutes the Transmit Error code-group (/H/) for the
encoded data word. This input is ignored in the
10BASE-T mode of operation. This signal is also
used in EEE mode as TXER when TXEN = 1, and
as LPI when TXEN = 0.
Note:
This signal is not used in RMII mode.
Transmit
Data 4
(MII Mode)
TXD4
VIS
(PU)
In Symbol Interface (5B decoding) mode, this sig-
nal becomes the MII Transmit Data 4 line (the MSB
of the 5-bit symbol code-group).
Note:
This signal is not used in RMII mode.
1
Transmit
Enable
TXEN
VIS
(PD)
Indicates that valid transmission data is present on
TXD[3:0]. In RMII mode, only TXD[1:0] provide
valid data.
1
Transmit Clock
(MII Mode)
TXCLK
VO8
Used to latch data from the MAC into the trans-
ceiver.
• MII (100BASE-TX): 25 MHz
• MII (10BASE-T): 2.5 MHz
Note:
This signal is not used in RMII mode.
LAN8740A/LAN8740Ai
DS00001987A-page 8
2013-2015 Microchip Technology Inc.
1
Receive
Data 0
RXD0
VO8
Bit 0 of the 4 (2 in RMII mode) data bits that are
sent by the transceiver on the receive path.
PHY Operat-
ing Mode 0
Configuration
Strap
MODE0
VIS
(PU)
Combined with MODE1 and MODE2, this configu-
ration strap sets the default PHY mode.
See
Note 1
for more information on configuration
straps.
Note:
Refer to
Section 3.7.2, "MODE[2:0]:
Mode Configuration"
for additional
details.
1
Receive
Data 1
RXD1
VO8
Bit 1 of the 4 (2 in RMII mode) data bits that are
sent by the transceiver on the receive path.
PHY Operat-
ing Mode 1
Configuration
Strap
MODE1
VIS
(PU)
Combined with MODE0 and MODE2, this configu-
ration strap sets the default PHY mode.
See
Note 1
for more information on configuration
straps.
Note:
Refer to
Section 3.7.2, "MODE[2:0]:
Mode Configuration"
for additional
details.
1
Receive
Data 2
(MII Mode)
RXD2
VO8
Bit 2 of the 4 (in MII mode) data bits that are sent by
the transceiver on the receive path.
Note:
This signal is not used in RMII mode.
Power Man-
agement Event
Output
nPME
VO8
When in RMII mode, this pin may be used alterna-
tively as an active low Power Management Event
(PME) output.
Note:
The nPME signal can be optionally con-
figured to output on the LED1, LED2, or
RXD2/nPME/nINTSEL pins. Refer to
Section 3.8.4, "Wake on LAN (WoL)"
for
additional nPME and WoL information.
MII/RMII Mode
Select Configu-
ration Strap
RMIISEL
VIS
(PD)
This configuration strap selects the MII or RMII
mode of operation. When strapped low to VSS, MII
mode is selected. When strapped high to VDDIO
RMII mode is selected.
See
Note 1
for more information on configuration
straps.
Note:
Refer to
Section 3.7.3, "RMIISEL:
MII/RMII Mode Configuration"
for addi-
tional details.
TABLE 2-1:
MII/RMII SIGNALS (CONTINUED)
Num Pins
Name
Symbol
Buffer Type
Description
2013-2015 Microchip Technology Inc.
DS00001987A-page 9
LAN8740A/LAN8740Ai
1
Receive
Data 3
(MII Mode)
RXD3
VO8
Bit 3 of the 4 (in MII mode) data bits that are sent by
the transceiver on the receive path.
Note:
This signal is not used in RMII mode.
PHY Address 2
Configuration
Strap
PHYAD2
VIS
(PD)
Combined with PHYAD0 and PHYAD1, this config-
uration strap sets the transceiver’s SMI address.
See
Note 1
for more information on configuration
straps.
Note:
Refer to
Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration"
for addi-
tional information.
1
Receive Error
RXER
VO8
This signal is asserted to indicate that an error was
detected somewhere in the frame presently being
transferred from the transceiver. This signal is also
used in EEE mode as RXER when RXDV = 1, and
as LPI when RXDV = 0.
Note:
This signal is optional in RMII mode.
Receive
Data 4
(MII Mode)
RXD4
VO8
In Symbol Interface (5B decoding) mode, this sig-
nal is the MII Receive Data 4 signal, the MSB of the
received 5-bit symbol code-group.
Note:
Unless configured to the Symbol Inter-
face mode, this pin functions as RXER.
PHY Address 0
Configuration
Strap
PHYAD0
VIS
(PD)
Combined with PHYAD1 and PHYAD2, this config-
uration strap sets the transceiver’s SMI address.
See
Note 1
for more information on configuration
straps.
Note:
Refer to
Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration"
for addi-
tional information.
1
Receive Clock
(MII Mode)
RXCLK
VO8
In MII mode, this pin is the receive clock output.
• MII (100BASE-TX): 25 MHz
• MII (10BASE-T): 2.5 MHz
PHY Address 1
Configuration
Strap
PHYAD1
VIS
(PD)
Combined with PHYAD0 and PHYAD2, this config-
uration strap sets the transceiver’s SMI address.
See
Note 1
for more information on configuration
straps.
Note:
Refer to
Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration"
for addi-
tional information.
1
Receive Data
Valid
RXDV
VO8
Indicates that recovered and decoded data is avail-
able on the RXD pins.
TABLE 2-1:
MII/RMII SIGNALS (CONTINUED)
Num Pins
Name
Symbol
Buffer Type
Description
LAN8740A/LAN8740Ai
DS00001987A-page 10
2013-2015 Microchip Technology Inc.
Note 1: Configuration strap values are latched on power-on reset and system reset. Configuration straps are iden-
tified by an underlined symbol name. Signals that function as configuration straps must be augmented with
an external resistor when connected to a load. Refer to
Section 3.7, "Configuration Straps"
for additional
information.
1
Collision Detect
(MII Mode)
COL
VO8
This signal is asserted to indicate detection of a
collision condition in MII mode.
Carrier Sense /
Receive Data
Valid
(RMII Mode)
CRS_DV
VO8
This signal is asserted to indicate the receive
medium is non-idle in RMII mode. When a
10BASE-T packet is received, CRS_DV is
asserted, but RXD[1:0] is held low until the SFD
byte (10101011) is received.
Note:
Per the RMII standard, transmitted data
is not looped back onto the receive data
pins in 10BASE-T half-duplex mode.
PHY Operat-
ing Mode 2
Configuration
Strap
MODE2
VIS
(PU)
Combined with MODE0 and MODE1, this configu-
ration strap sets the default PHY mode.
See
Note 1
for more information on configuration
straps.
Note:
Refer to
Section 3.7.2, "MODE[2:0]:
Mode Configuration"
for additional
details.
1
Carrier Sense
(MII Mode)
CRS
VO8
(PD)
This signal indicates detection of a carrier in MII
mode.
TABLE 2-1:
MII/RMII SIGNALS (CONTINUED)
Num Pins
Name
Symbol
Buffer Type
Description