SMSC LAN91C96 5v&3v
Revision 1.0 (10-24-08)
DATASHEET
LAN91C96
Non-PCI Single-Chip
Full Duplex Ethernet
Controller with Magic
Packet
Datasheet
Product Features
Non-PCI Single-Chip Ethernet Controller
A Subset of Motorola 68000 Bus Interface
Support
Fully Supports Full Duplex Switched Ethernet
Supports Enhanced Transmit Queue
Management
6K Bytes of On-Chip RAM
Supports IEEE 802.3 (ANSI 8802-3) Ethernet
Standards
Automatic Detection of TX/RX Polarity Reversal
Enhanced Power Management Features
Supports “Magic Packet” Power Management
Technology
Hardware Memory Management Unit
Optional
Configuration via Serial EEPROM
Interface (Jumperless)
Supports single +5V or +3.3V (for Revisions E
and Later) VCC Designs
Supports Mixed Voltage External PHY Designs
1
Low Power CMOS Design
100 Pin QFP and TQFP (1.0 mm body
Thickness) Lead-Free RoHS Compliant
Packages
Pin Compatible with the LAN91C92 and
LAN91C94
Bus Interface
Direct Interface to Local Bus, PCMCIA, and
68000 Buses with No Wait States
Flexible Bus Interface
16 Bit Data and Control Paths
Fast Access Time
Pipelined Data Path
Handles Block Word Transfers for any
Alignment
1
Refer to Description of Pin Functions on Page 17 for
5V tolerant pins
High Performance Chained ("Back-to-Back")
Transmit and Receive
Pin Compatible with the LAN91C92 (in Local
Bus Mode) and the LAN91C94 in Both Local
Bus and PCMCIA Modes
Dynamic Memory Allocation Between Transmit
and Receive
Flat Memory Structure for Low CPU Overhead
Buffered Architecture, Insensitive to Bus
Latencies (No Overruns/Underruns)
Supports Boot PROM for Diskless Local Bus
Applications
Network Interface
Integrated
10BASE-T
Transceiver
Functions:
-
Driver and Receiver
-
Link Integrity Test
-
Receive Polarity Detection and Correction
Integrated AUI Interface
10 Mb/s Manchester Encoding/Decoding and
Clock Recovery
Automatic Retransmission, Bad Packet
Rejection, and Transmit Padding
External and Internal Loopback Modes
Four Direct Driven LEDs for Status/ Diagnostics
Software Drivers
LAN9000 Drivers for Major Network Operating
Systems Utilizing Local Bus or PCMCIA
Interface
Software Drivers Compatible with the
LAN91C92, LAN91C94, LAN91C100FD (100
Mb/s), and LAN91C110 (100 Mb/s) Controllers
in Local Bus Mode
Software Drivers Utilize Full Capability of 32 Bit
Microprocessor
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Revision 1.0 (10-24-08)
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SMSC LAN91C96 5v&3v
DATASHEET
ORDER NUMBERS:
LAN91C96-MS for 100 pin, QFP Lead-Free RoHS Compliant package
LAN91C96-MU for 100 pin, TQFP Lead-Free RoHS Compliant package
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2008 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
SMSC LAN91C96 5v&3v
Page 3
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DATASHEET
Table of Contents
CHAPTER 1 GENERAL DESCRIPTION ..................................................................... 7
CHAPTER 2 OVERVIEW ............................................................................................. 8
CHAPTER 3 PIN CONFIGURATIONS....................................................................... 11
3.1
Local Bus vs. PCMCIA vs. 68000 Pin Requirements...................................................................................15
CHAPTER 4 DESCRIPTION OF PIN FUNCTIONS ................................................... 17
4.1
Buffer Symbols ................................................................................................................................................21
CHAPTER 5 FUNCTIONAL DESCRIPTION .............................................................. 23
5.1
Buffer Memory................................................................................................................................................24
5.2
Interrupt Structure.........................................................................................................................................31
5.3
Reset Logic.......................................................................................................................................................32
5.4
Power Down Logic States ...............................................................................................................................32
5.5
LAN91C96 Power Down States .....................................................................................................................33
5.6
PCMCIA CONFIGURATION REGISTERS DESCRIPTION ..................................................................36
CHAPTER 6 FRAME FORMAT IN BUFFER MEMORY FOR ETHERNET ............... 38
CHAPTER 7 REGISTERS MAP IN I/O SPACE ......................................................... 42
7.1
I/O Space Access .............................................................................................................................................42
7.2
I/O Space Registers Description ....................................................................................................................42
CHAPTER 8 THEORY OF OPERATION ................................................................... 65
8.1
Typical Flow of Events for Transmit (Auto Release = 0) ............................................................................67
8.2
Typical Flow of Events for Transmit (Auto Release = 1) ............................................................................68
8.3
Flow of Events for Receive .............................................................................................................................69
CHAPTER 9 FUNCTIONAL DESCRIPTION OF THE BLOCKS................................ 79
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Datasheet
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9.1
Memory Management Unit ............................................................................................................................79
9.2
Arbiter .............................................................................................................................................................79
9.3
Bus Interface ...................................................................................................................................................80
9.4
Wait State Policy .............................................................................................................................................80
9.5
Arbitration Considerations ............................................................................................................................81
9.6
DMA Block ......................................................................................................................................................82
9.7
Packet Number FIFOS ...................................................................................................................................82
9.8
CSMA Block....................................................................................................................................................84
9.9
Network Interface ...........................................................................................................................................85
9.10
10Base-T.......................................................................................................................................................86
9.11
AUI ...............................................................................................................................................................86
9.12
Physical Interface ........................................................................................................................................86
9.13
Transmit Functions .....................................................................................................................................86
9.13.1
Manchester Encoding.............................................................................................................................86
9.13.2
Transmit Drivers ....................................................................................................................................86
9.13.3
Jabber Function ......................................................................................................................................87
9.13.4
SQE Function .........................................................................................................................................87
9.14
Receive Functions ........................................................................................................................................87
9.14.1
Receive Drivers......................................................................................................................................87
9.14.2
Manchester Decoder and Clock Recovery .............................................................................................87
9.14.3
Squelch Function....................................................................................................................................87
9.14.4
Reverse Polarity Function ......................................................................................................................87
9.14.5
Collision Detection Function .................................................................................................................88
9.14.6
Link Integrity .........................................................................................................................................88
CHAPTER 10 BOARD SETUP INFORMATION ........................................................ 89
10.1
Diagnostic LEDs ..........................................................................................................................................90
10.2
Bus Clock Considerations...........................................................................................................................90
10.3
68000 Bus Interface .....................................................................................................................................90
CHAPTER 11 OPERATIONAL DESCRIPTION ......................................................... 92
11.1
Maximum Guaranteed Ratings* ................................................................................................................92
11.2
DC Electrical Characteristics.....................................................................................................................92
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Datasheet
SMSC LAN91C96 5v&3v
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CHAPTER 12 TIMING DIAGRAMS ........................................................................... 99
CHAPTER 13 LAN91C96 REVISIONS .................................................................... 125
List of Figures
Figure 3.1 - LAN91C96 100 Pin QFP...........................................................................................................................11
Figure 3.2 - LAN91C96 100 Pin TQFP.........................................................................................................................12
Figure 3.3 - LAN91C96 System Block Diagram ...........................................................................................................13
Figure 3.4 – System Diagram for Local Bus with Boot Prom .......................................................................................14
Figure 4.1 - LAN91C96 Internal Block Diagram ...........................................................................................................22
Figure 5.1 – Mapping and Paging vs. Receive and Transmit Area ..............................................................................25
Figure 5.2 – Transmit Queues and Mapping ................................................................................................................26
Figure 5.3 – Receive Queues and Mapping .................................................................................................................27
Figure 5.4 - LAN91C96 Internal Block Diagram with Data Path ...................................................................................28
Figure 5.5 – Logical Address Generation and Relevant Registers...............................................................................29
Figure 6.1 – Data Frame Format..................................................................................................................................38
Figure 6.2 - LAN91C96 Registers ................................................................................................................................41
Figure 7.1 – Interrupt Structure.....................................................................................................................................61
Figure 8.1 – Interrupt Service Routine .........................................................................................................................70
Figure 8.2 - RX INTR ...................................................................................................................................................71
Figure 8.3 -TX INTR.....................................................................................................................................................72
Figure 8.4 -TXEMPTY INTR ........................................................................................................................................73
Figure 8.5 – Driver Send and Allocate Routines ..........................................................................................................74
Figure 8.6 – Interrupt Generation for Transmit; Receive, MMU ...................................................................................78
FIGURE 9.1 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS.........................................................84
FIGURE 10.1 - 64 X 16 SERIAL EEPROM MAP .........................................................................................................91
Figure 12.1 – Card Configuration Registers – Read/Write PCMCIA Mode (A15=1) ....................................................99
Figure 12.2 – Local Bus Consecutive Read Cycles ...................................................................................................100
Figure 12.3 - PCMCIA Consecutive Read Cycles ......................................................................................................101
Figure 12.4 – Local Bus Consecutive Write Cycles....................................................................................................102
Figure 12.5 - PCMCIA Consecutive Write Cycles ......................................................................................................103
Figure 12.6 – Local Bus Consecutive Read and Write Cycles ...................................................................................104
Figure 12.7 – Data Register Special Read Access ....................................................................................................105
Figure 12.8 – Data Register Special Write Access.....................................................................................................106
Figure 12.9 - 8-Bit Mode Register Cycles ..................................................................................................................107
Figure 12.10 - 68000 Read Timing.............................................................................................................................108
Figure 12.11 - 68000 Write Timing.............................................................................................................................109
Figure 12.12 – External ROM Read Access ..............................................................................................................110
Figure 12.13 – Local Bus Register Access When Using Bale ....................................................................................111
Figure 12.14 – External ROM Read Access Using Bale ............................................................................................112
Figure 12.15 - EEPROM Read...................................................................................................................................113
Figure 12.16 - EEPROM Write ...................................................................................................................................114
Figure 12.17 - PCMCIA Attribute Memory Read/Write (A15=0) .................................................................................115
Figure 12.18 – External ENDEC Interface – Start of Transmit ...................................................................................115
Figure 12.19 – External ENDEC Interface – Receive Data ........................................................................................116
Figure 12.20 – Differential Output Signal Timing (10BASE-T and AUI) .....................................................................117
Figure 12.21 – Receive Timing – Start of Frame (AUI and 10BASE-T) .....................................................................118
Figure 12.22 – Receive Timing – End of Frame (AUI and 10BASE-T).......................................................................119
Figure 12.23 – Transmit Timing – End of Frame (AUI and 10BASE-T)......................................................................120
Figure 12.24 – Collision Timing (AUI) ........................................................................................................................121
Figure 12.25 – Memory Read Timing.........................................................................................................................121
Figure 12.26 – Input Clock Timing .............................................................................................................................122
Figure 12.27 – Memory Write Timing .........................................................................................................................122
Figure 12.28 - 100 PIN QFP Package........................................................................................................................123
Figure 12.29 - 100 PIN TQFP Package .....................................................................................................................124
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
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SMSC LAN91C96 5v&3v
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List of Tables
Table 5.1 - LAN91C96 Address Space ........................................................................................................................30
Table 5.2 - Bus Transactions In LOCAL BUS Mode ....................................................................................................30
Table 5.3 - Bus Transactions In PCMCIA Mode...........................................................................................................31
Table 5.4 - Bus Transactions In 68000 Mode................................................................................................................31
Table 5.5 - Interrupt Merging........................................................................................................................................32
Table 5.6 - LOCAL BUS Mode Defined States (Refer To Table 5.7 For Next States To Wake-Up Events).................33
Table 5.7- LOCAL BUS Mode ......................................................................................................................................33
Table 5.8 - PCMCIA Mode (Refer To Table 5.7 For Next States To Wake-Up Events) ...............................................34
Table 5.9 - PCMCIA Mode ...........................................................................................................................................34
Table 7.1 - Transmit Loop ............................................................................................................................................45
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Datasheet
SMSC LAN91C96 5v&3v
Page 7
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DATASHEET
Chapter 1 General Description
The LAN91C96 is a VLSI Ethernet Controller that combines Local Bus, PCMCIA, and Motorola 68000 bus
interfaces in one chip. LAN91C96 integrates all MAC and physical layer functions, as well as the packet
RAM, needed to implement a high performance 10BASE-T (twisted pair) node. For 10BASE5 (thick coax),
10BASE2 (thin coax), and 10BASE-F (fiber) implementations, the LAN91C96 interfaces to external
transceivers via the provided AUI port. Only one additional IC is required for most applications. The
LAN91C96 comes with Full Duplex Switched Ethernet (FDSWE) support allowing the controller to provide
much higher throughput. 6K bytes of RAM is provided to support enhanced throughput and compensate
for any increased system service latencies. The controller implements multiple advanced power-down
modes including Magic Packet to conserve power and operate more efficiently. The LAN91C96 can
directly interface with the Local Bus, PCMCIA, and 68000 buses and deliver no-wait-state operation. For
Local Bus and PCMCIA interfaces, the LAN91C96 occupies 16 I/0 locations and no memory space except
for PCMCIA attribute memory space. The same I/O space is used for both LOCAL BUS and PCMCIA
operations. Its shared memory is sequentially accessed with 40ns access times to any of its registers,
including its packet memory. DMA services are not used by the LAN91C96, virtually de-coupling network
traffic from local or system bus utilization. For packet memory management, the LAN91C96 integrates a
unique hardware Memory Management Unit (MMU) with enhanced performance and decreased software
overhead when compared to ring buffer and linked list architectures. The LAN91C96 is portable to
different CPU and bus platforms due to its flexible bus interface, flat memory structure (no pointers), and
its loosely coupled buffered architecture (not sensitive to latency).
The LAN91C96 is available in 100-pin QFP and TQFP (1.0 mm body thickness) packages. The low profile
TQFP is ideal for mobile applications such as PC Card LAN adapters. The LAN91C96 operates with a
single power supply voltage of 5.0V. Revisions E and later will also operate using a single 3.3V power
supply.
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Chapter 2 Overview
A unique architecture allows the LAN91C96 to combine high performance, flexibility, high integration and
simple software interface.
The LAN91C96 incorporates the LAN91C92 functionality for LOCAL BUS environments, as well as a
PCMCIA interface and attribute registers like the LAN91C94 It also includes a subset of the Motorola
68000 interface. Mode selection between LOCAL BUS and PCMCIA is static and is done only at the end
of a reset. Selection of 68000 operation mode is performed at power-up.
The LAN91C96 consists of the same logical I/O register structure in LOCAL BUS and PCMCIA modes.
However, some of the signals used to access the PCMCIA differ from the LOCAL BUS mode. The MMU
(Memory Management Unit) architecture used by the LAN91C96 combines the simplicity and low
overhead of fixed areas with the flexibility of linked lists providing improved performance over other
methods.
Packet reception and transmission are determined by memory availability. All other resources are always
available if memory is available. To complement this flexible architecture, bus interface functions are
incorporated in the LAN91C96, as well as a 6144 byte packet RAM - and serial EEPROM-based setup.
The user can select or modify configuration choices. The LAN91C96 integrates most of the 802.3
functionality, incorporating the MAC layer protocol, the physical layer encoding and decoding functions
with the ability to handle the AUI interface. For twisted pair networks, LAN91C96 integrates the twisted pair
transceiver as well as the link integrity test functions.
The LAN91C96 is a true 10BASE-T single chip device able to interface to a system or a local bus.
Support for direct-driven LEDs for installation and run-time diagnostics is provided. 802.3 statistics are
gathered to facilitate network management.
The LAN91C96 is a single chip Ethernet controller designed to be 100% pin and software compatible with the
LAN91C92 and LAN91C94 in LOCAL BUS mode. Similar to the LAN91C94, the LAN91C96 has support
necessary for providing a true single chip single function PCMCIA Ethernet socket adapter. The LAN91C96
incorporates all of the PCMCIA registers and signals that interface to the PCMCIA bus.
The LAN91C96 has been designed to support full duplex switched Ethernet and provides Fully independent
transmit and receive operations.
The LAN91C96 internal packet memory is extended to 6k bytes, and the MMU will continue to manage
memory in 256 byte pages. The increase in memory size accommodates the potential for simultaneous
transmit and receive traffic in some full duplex applications as well as support for enhanced performance on
systems that introduce increased latency.
The LAN91C96 has the ability to retrieve configuration information from a serial EEPROM on reset or power-
up. In LOCAL BUS mode, the serial EPROM acts as storage of configuration and IEEE Ethernet address
information compatible with the existing LAN91C90, LAN91C92, and LAN91C94 LOCAL BUS Ethernet
controllers. In PCMCIA mode, the EEPROM function is the same as in LOCAL BUS mode. External Flash
ROM is required for CIS storage.
THE LAN91C96 OFFERS:
High integration:
Single chip controller including:
Packet
RAM
LOCAL BUS interface
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
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SMSC LAN91C96 5v&3v
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PCMCIA interface
68000 interface
EEPROM
interface
Encoder/decoder with AUI interface
10BASE-T
transceiver
High performance:
Chained ("Back-to-back") packet handling with no CPU intervention:
Queues transmit packets
Queues receive packets
Stores results in memory along with packet
Queues
interrupts
Optional single interrupt upon completion of transmit chain
Fast block move operation for load/unload:
CPU sees packet bytes as if stored continuously.
Handles 16 bit transfers regardless of address alignment.
Access to packet through fixed window.
Fast bus interface:
Compatible with LOCAL BUS type and faster buses.
Flexibility:
Flexible packet and header processing:
Can access any byte in the packet.
Can immediately remove undesired packets from queue.
Can move packets from receive to transmit queue.
Can alter receive processing order without copying data.
Can discard or enqueue again a failed transmission.
Resource allocation:
Memory dynamically allocated for transmit and receive.
Can automatically release memory on successful transmission.
Configuration:
LOCAL BUS:
Uses non-volatile jumperless setup via serial EEPROM.
PCMCIA:
Uses ROM or Flash ROM for attribute memory storage and optional serial EEPROM for IEEE
address storage. PCMCIA I/O ignores address lines A4-A15 and relies on the PCMCIA host,
decoding for the slot.
nROM/nPCMCIA, on LAN91C96, is left open with a pullup for LOCAL BUS mode. This pin is
sampled at the end of RESET. If found low, the LAN91C96 is configured for PCMCIA mode.
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
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Motorola 68000:
Uses
non-volatile
jumperless
setup via serial EEPROM. The device must power up in LOCAL BUS
mode with nIORD and nIOWR asserted simultaneously to make the controller enter the 68000
mode.
Note:
The first write to the 68000 configured controller must be a write.