24LC41A 1K/4K 2.5V Dual Mode, Dual Port I2C Serial EEPROM

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 1

24LC41A

Features

• Single supply with operation down to 2.5V
• Completely implements DDC1



/DDC2



interface

for monitor identification, including recovery to
DDC1

• Improved noise immunity
• Separate high speed 2-wire bus for

microcontroller access to 4K-bit Serial EEPROM

• Low-power CMOS technology
• 2 mA active current typical
• 20

A standby current typical at 5.5V

• Dual 2-wire serial interface bus, I

™

compatible

• Hardware write-protect for Microcontroller Access

Port

• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes (DDC port) or

16 bytes (4K Port)

• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• 1,000,000 erase/write cycles
• Data retention > 40 years
• 8-pin PDIP package
• Available for extended temperature ranges

Description

The Microchip Technology Inc. 24LC41A is a dual port
128 x 8 and 512 x 8-bit Electrically Erasable PROM
(EEPROM). This device is designed for use in applica-
tions requiring storage and serial transmission of
configuration and control information. Three modes of
operation have been implemented:

• Transmit-only mode for the DDC Monitor Port

• Bidirectional mode for the DDC Monitor Port

• Bidirectional, industry-standard 2-wire bus for the

4K Microcontroller Access Port

Upon power-up, the DDC Monitor Port will be in the
Transmit-only mode, repeatedly sending a serial bit
stream of the entire memory array contents, clocked by
the VCLK pin. A valid high-to-low transition on the
DSCL pin will cause the device to enter the transition
mode, an look for a valid control byte on the I

C bus. If

it detects a valid control byte from the master, it will
switch to Bidirectional mode, with byte selectable read/
write capability of the memory array using DSCL. If no
control byte is received, the device will revert to the
Transmit-only mode after it received 128 consecutive
VCLK Package Type pulses while the DSCL pin is idle.

The 4K-bit microcontroller port is completely indepen-
dent of the DDC port, therefore, it can be accessed
continuously by a microcontroller without interrupting
DDC transmission activity. The 24LC41A is available in
a standard 8-pin PDIP package in both commercial and
industrial temperature ranges.

Package Type

Block Diagram

Pin Function Table

- Commercial (C):

+70°C

- Industrial (I):

-40

C to

+85

Name

Function

DSCL

Serial Clock for DDC Bidirectional mode
(DDC2)

DSDA

Serial Address and Data I/O(DDC Bus)

VCLK

Serial Clock for DDC Transmit-only mode
(DDC1)

MSCL

Serial clock for 4K-bit MCU port

MSDA

Serial Address and Data I/O for 4K-bit MCU port

MWP

Hardware write-protect for Microcontroller
Access Port

Ground

+2.5V to +5.5V power supply

24
LC
41
A

PDIP

DSCL

VCLK

MSDA

DSDA

Vcc

MWP

MSCL

EDID Table

1K-Bit

4K-Bit

Serial

EEPROM

MSDA

MSCL

DDC M

ito

r P

icr

ocon

ller

cess P

DSDA

VCLK

DSCL

1K/4K 2.5V Dual Mode, Dual Port I

C™ Serial EEPROM

DDC is a trademark of Video Electronics Standards Association.

C is a trademark of Philips Corporation.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 2



2003 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

......................................................................................................... -0.6V to V

+1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-65°C to +125°C

ESD protection on all pins

......................................................................................................................................................≥

4 kV

TABLE 1-1:

DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0°C to +70°C

Industrial (I):

=-40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

DSCL, DSDA, MSCL & MSDA pins:

High-level input voltage
Low-level input voltage

.7 V

—

.3 V

V
V

Input levels on VCLK pin:

High-level input voltage
Low-level input voltage

2.0

—

.2 V

V
V

≥

2.7V (Note)

< 2.7V (Note)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note)

Low-level output voltage

—

= 3 mA, V

= 2.5V (Note)

Low-level output voltage

—

= 6 mA, V

= 2.5V

Input leakage current

—

±1

=.1V to V

Output leakage current

—

±1

OUT

=.1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, DSCL or MSCL = 400 kHz

Standby current

CCS

—
—

200

= 3.0V, DSDA or MSDA = DSCL

or MSCL = V

= 5.5V, DSDA or MSDA = DSCL

or MSCL = V

CLK

= V

Note:

This parameter is periodically sampled and not 100% tested.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 3

24LC41A

TABLE 1-2:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS PORTS)

DDC Monitor Port (Bidirectional mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency (DSCL and
MSCL)

CLK

—

100

—

400

kHz

Clock high time (DSCL and
MSCL)

HIGH

4000

—

600

—

Clock low time (DSCL and
MSCL)

LOW

4700

—

1300

—

DSCL, DSDA, MSCL &
MSDA rise time

—

1000

—

300

(Note 1)

DSCL, DSDA, MSCL &
MSDA fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first clock
pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

min to V

max

—

250

20 + .1

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (DSCL, DSDA, MSCL
& MSDA pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, Vcc = 5.0V, Block mode
(Note 4)

DDC Monitor Port Transmit-only mode Parameters

Output valid from VCLK

VAA

—

2000

—

1000

VCLK high time

VHIGH

4000

—

600

—

VCLK low time

VLOW

4700

—

1300

—

VCLK setup time

VHST

—

VCLK hold time

SPVL

4000

—

600

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up
time

VPU

—

Input filter spike
suppression (VCLK pin)

SPV

—

100

—

100

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of Start or Stop
conditions.

The combined T

and V

HYS

specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 4



2003 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

DDC Monitor Port

The DDC Monitor Port operates in two modes, the
Transmit-only mode and the Bidirectional mode. There
is a separate 2-wire protocol to support each mode,
each having a separate clock input and sharing a
common data line (DSDA). The device enters the
Transmit-only mode upon power-up. In this mode, the
device transmits data bits on the DSDA pin in response
to a clock signal on the VCLK pin. The device will
remain in this mode until a valid high-to-low transition is
placed on the DSCL input. When a valid transition on
DSCL is recognized, the device will switch into the
Bidirectional mode and look for its control byte to be
sent by the master. If it detects its control byte, it will
stay in the Bidirectional mode. Otherwise, it will revert
to the Transmit-only mode after it sees 128 VCLK
pulses.

2.1.1

TRANSMIT-ONLY MODE

The device will power-up in the Transmit-only mode
at address 00H. This mode supports a unidirectional
2-wire protocol for transmission of the contents of the
memory array.

This device requires that it be initialized prior to valid
data being sent in the Transmit-only mode (see
Section 2.1.2 “Initialization Procedure”). In this
mode, data is transmitted on the DSDA pin in 8-bit
bytes, each followed by a ninth, null bit (see Figure 2-
1). The clock source for the Transmit-only mode is
provided on the VCLK pin, and a data bit is output on
the rising edge on this pin. The eight bits in each byte
are transmitted by Most Significant bit first. Each byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmit-
ted, the output will wrap around to the first location
and continue. The Bidirectional mode Clock (DSCL)
pin must be held high for the device to remain in the
Transmit-only mode.

2.1.2

INITIALIZATION PROCEDURE

After V

has stabilized, the device will be in the

Transmit-only mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the DSDA pin will be
in a high-impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the Most Significant bit of a byte.
The device will power-up at an indeterminate byte
address (Figure 2-2).

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

SCL

SDA

VCLK

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

VCLK

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 5

24LC41A

2.1.3

BIDIRECTIONAL MODE

Before the 24LC41A can be switched into the Bidirec-
tional mode (Figure 2-4), it must enter the transition
mode, which is done by applying a valid high-to-low
transition on the Bidirectional mode Clock (DSCL). As
soon it enters the transition mode, it looks for a control
byte 1010 000X on the I

C™ bus, and starts to count

pulses on VCLK. Any high-to-low transition on the
DSCL line will reset the count. If it sees a pulse count
of 128 on VCLK while the DSCL line is idle, it will revert
back to the Transmit-only mode, and transmit its
contents starting with the Most Significant bit in
address 00h. However, if it detects the control byte on
the I

C bus, (Figure 2-3) it will switch to the in the

Bidirectional mode. Once the device has made the
transition to the Bidirectional mode, the only way to
switch the device back to the Transmit-only mode is to
remove power from the device. The mode transition
process is shown in detail in Figure 2-4.

Once the device has switched into the Bidirectional
mode, the VCLK input is disregarded, with the excep-
tion that a logic high level is required to enable write
capability. This mode supports a two-wire bidirectional
data transmission protocol (I

)

. In this protocol, a

device that sends data on the bus is defined to be the
transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be
controlled by a master device that generates the
Bidirectional mode Clock (DSCL), controls access to
the bus and generates the Start and Stop conditions,
while the monitor port acts as the slave. Both master
and slave can operate as transmitter or receiver, but
the master device determines which mode is activated.
In the Bidirectional mode, the monitor port only
responds to commands for device 1010 000X.

2.2

Microcontroller Access Port

The Microcontroller Access Port supports a bidirec-
tional 2-wire bus and data transmission protocol. A
device that sends data onto the bus is defined as
transmitter, and a device receiving data as receiver.
The bus has to be controlled by a master device which
generates the serial clock (MSCL), controls the bus
access, and generates the Start and Stop conditions,
while the Microcontroller Access Port works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.

FIGURE 2-3:

SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE

FIGURE 2-4:

MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE

Transition mode with possibility to return to Transmit-only mode

Bidirectional

permanently

SCL

SDA

VCLK count = 1 2 n 0

VCLK

Transmit-only
mode

MODE

ACK

n < 128

TVHZ

SCL

SDA

VCLK

Transmit-only

MODE

Bidirectional

Recovery to Transmit-only mode

Bit8

(MSB of data in 00h)

VCLK count = 1 2 3 4 127 128

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 6



2003 Microchip Technology Inc.

FIGURE 2-5:

DISPLAY OPERATION PER DDC

STANDARD PROPOSED BY VESA

Communication

is idle

Is Vsync

present?

Send EDID continuously

using Vsync as clock

High-to-low

transition on

SCL?

Yes

Stop sending EDID.

Switch to DDC2 mode.

Display has

transition state

optional

Set Vsync counter = 0

Change on

VCLK lines?

SCL, SDA or

Yes

High - low

transition on SCL

Reset Vsync counter = 0

Yes

Valid

received?

DDC2 address

VCLK

cycle?

Yes

Increment VCLK counter

Yes

Switch back to DDC1

mode.

DDC2 communication

idle. Display waiting for

address byte.

DDC2B

address

received?

Yes

Receive DDC2B

command

Respond to DDC2B

command

Is display

Access.bus

Yes

Valid Access.bus

address?

Yes

See Access.bus

specification to determine

correct procedure.

Yes

Display Power-on

DDC Circuit Powered

from +5 volts

or start timer

Reset counter or timer

(if appropriate)

Counter=128 or

timer expired?

High-to-low

transition on

SCL?

Yes

Note 1: The base flowchart is copyright



1993, 1994, 1995 Video Electronic Standard Association (VESA) from

VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.

2: The dash box and text “The 24LC41A and ... inside dash box.” are added by Microchip Technology Inc.

3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC41A.

capable?

The 24LC41A was designed to comply to the
portion of flowchart inside dash box.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 7

24LC41A

3.0

BIDIRECTIONAL BUS
CHARACTERISTICS

Characteristics for the Bidirectional bus are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port The following bus pro-
tocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Start condition. All commands must be preceded by a
Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Stop condition. All operations must be ended with a
Stop condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an over-
write does occur, it will replace data in a first in first out
fashion.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the
DSDA or MSDA line during the Acknowledge clock
pulse in such a way that the DSDA or MSDA line is
stable low during the high period of the acknowledge
related clock pulse. Of course, setup and hold times
must be taken into account. A master must signal an
end of data to the slave by not generating an Acknowl-
edge bit on the last byte that has been clocked out of
the slave. In this case, the slave must leave the data
line high to enable the master to generate the Stop
condition.

3.6

Device Addressing

A control byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit control code. This
control code is set as 1010 for both read and write
operations and is the same for both the DDC Monitor
Port and Microcontroller Access Port. The next three
bits of the control byte are block select bits (B1, B2, and
B0). All three of these bits are zero for the DDC Monitor
Port. The B2 and B1 bits are don’t care bits for the
Microcontroller Access Port, and the B0 bit is used by
the Microcontroller Access Port to select which of the
two 256 word blocks of memory are to be accessed
(see Figure 3-4). The B0 bit is effectively the Most
Significant bit of the word address. The last bit of the
control byte defines the operation to be performed.
When set to one, a read operation is selected; when set
to zero, a write operation is selected. Following the Start
condition, the device monitors the DSDA or MSDA bus
checking the device type identifier being transmitted,
upon a 1010 code the slave device outputs an Acknowl-
edge signal on the SDA line. Depending on the state of
the R/W bit, the device will select a read or a write
operation. The DDC Monitor Port and Microcontroller
Access Port can be accessed simultaneously because
they are completely independent of one another.

Note:

The microcontroller access port and the
DDC Monitor Port (in Bidirectional mode)
will not generate any Acknowledge bits if
an internal programming cycle is in
progress.

Operation

Control Code

Block Select

R/W

Read

1010

B2B1B0

Write

1010

B2B1B0

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 8



2003 Microchip Technology Inc.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(

)

(B)

(D)

(C)

(

)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

MSCL

MSDA

MSCL

DSDA

STA

START

STOP

HYS

STO

MSCL

MSDA

DSCL

DSDA

STA

HIGH

STO

DAT

BUF

STA

LOW

MSCL

MSDA

OUT

B0, B1, and B2 are zeros for DDC Monitor Port. B1 and B2 are don’t care bits for the Microcontroller Access Port,
and B0 is used to select which of the two 256 word blocks of memory are to be accessed.

R/W

READ/WRITE

START

SLAVE ADDRESS

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 9

24LC41A

4.0

WRITE OPERATION

Write operations are identical for the DDC Monitor Port
(when in Bidirectional mode) and the Microcontroller
Access Port, with the exception of the VCLK and MWP
pins noted in the next sections. Data can be written
using either a Byte Write or Page Write command. Write
commands for the DDC Monitor Port and the
Microcontroller Access Port are completely
independent of one another.

4.1

Byte Write

Following the Start signal from the master, the slave
address (4-bits), the chip select bits (3-bits) and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be
written into the address pointer of the port. After
receiving another Acknowledge signal from the port,
the master device will transmit the data word to be
written into the addressed memory location. The port
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle, and
during this time, the port will not generate Acknowledge
signals (see Figure 4-1).

For the DDC Monitor Port it is required that VCLK be
held at a logic high level in order to program the device.
This applies to byte write and page write operation.
Note that VCLK can go low while the device is in its
self-timed program operation and not affect program-
ming. The MWP pin must be held high for the duration
of the write protection.

4.2

Page Write

The write control byte, word address, and the first data
byte are transmitted to the port in the same way as in a
byte write. But, instead of generating a Stop condition,
the master transmits up to eight data bytes to the DDC
Monitor Port or 16 bytes to the Microcontroller Access
Port, which are temporarily stored in the on-chip page
buffer and will be written into the memory after the
master has transmitted a Stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order 5-bits of the word address remains
constant. If the master should transmit more than eight
words to the DDC Monitor Port or 16 words to the
Microcontroller Access Port prior to generating the Stop
condition, the address counter will roll over and the
previously received data will be overwritten. As with the
byte write operation, once the Stop condition is received
an internal write cycle will begin (see Figure 4-2).

For the DDC Monitor Port, it is required that VCLK be
held at a logic high level in order to program the device.
This applies to byte write and page write operation.
Note that VCLK can go low while the device is in its
self-timed program operation and not affect program-
ming. For the DDC Monitor Port, the MWP pin must be
held high for the duration of the write cycle.

Note:

Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
Start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size - 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 10



2003 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

FIGURE 4-3:

VCLK WRITE ENABLE TIMING

S
T
A
R
T

S
T
O
P

BUS ACTIVITY
MASTER

SDA or

BUS ACTIVITY

A
C
K

CONTROL

BYTE

WORD

ADDRESS

DATA

MSDA LINE

VCLK

BUS ACTIVITY
MASTER

DSDA or

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA n

DATAn + 7

DATAn + 1

A
C
K

MSDA LINE

VCLK

SCL

SDA

VCLK

VHST

SPVL

STA

STO

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 1

24LC41A

Features

• Single supply with operation down to 2.5V
• Completely implements DDC1



/DDC2



interface

for monitor identification, including recovery to
DDC1

• Improved noise immunity
• Separate high speed 2-wire bus for

microcontroller access to 4K-bit Serial EEPROM

• Low-power CMOS technology
• 2 mA active current typical
• 20

A standby current typical at 5.5V

• Dual 2-wire serial interface bus, I

™

compatible

• Hardware write-protect for Microcontroller Access

Port

• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes (DDC port) or

16 bytes (4K Port)

• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• 1,000,000 erase/write cycles
• Data retention > 40 years
• 8-pin PDIP package
• Available for extended temperature ranges

Description

• Transmit-only mode for the DDC Monitor Port

• Bidirectional mode for the DDC Monitor Port

• Bidirectional, industry-standard 2-wire bus for the

4K Microcontroller Access Port

C bus. If

Package Type

Block Diagram

Pin Function Table

- Commercial (C):

+70°C

- Industrial (I):

-40

C to

+85

Name

Function

DSCL

Serial Clock for DDC Bidirectional mode
(DDC2)

DSDA

Serial Address and Data I/O(DDC Bus)

VCLK

Serial Clock for DDC Transmit-only mode
(DDC1)

MSCL

Serial clock for 4K-bit MCU port

MSDA

Serial Address and Data I/O for 4K-bit MCU port

MWP

Hardware write-protect for Microcontroller
Access Port

Ground

+2.5V to +5.5V power supply

24
LC
41
A

PDIP

DSCL

VCLK

MSDA

DSDA

Vcc

MWP

MSCL

EDID Table

1K-Bit

4K-Bit

Serial

EEPROM

MSDA

MSCL

DDC M

ito

r P

icr

ocon

ller

cess P

DSDA

VCLK

DSCL

1K/4K 2.5V Dual Mode, Dual Port I

C™ Serial EEPROM

DDC is a trademark of Video Electronics Standards Association.

C is a trademark of Philips Corporation.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 2



2003 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

......................................................................................................... -0.6V to V

+1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-65°C to +125°C

ESD protection on all pins

......................................................................................................................................................≥

4 kV

TABLE 1-1:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0°C to +70°C

Industrial (I):

=-40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

DSCL, DSDA, MSCL & MSDA pins:

High-level input voltage
Low-level input voltage

.7 V

—

.3 V

V
V

Input levels on VCLK pin:

High-level input voltage
Low-level input voltage

2.0

—

.2 V

V
V

≥

2.7V (Note)

< 2.7V (Note)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note)

Low-level output voltage

—

= 3 mA, V

= 2.5V (Note)

Low-level output voltage

—

= 6 mA, V

= 2.5V

Input leakage current

—

±1

=.1V to V

Output leakage current

—

±1

OUT

=.1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, DSCL or MSCL = 400 kHz

Standby current

CCS

—
—

200

= 3.0V, DSDA or MSDA = DSCL

or MSCL = V

= 5.5V, DSDA or MSDA = DSCL

or MSCL = V

CLK

= V

Note:

This parameter is periodically sampled and not 100% tested.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 3

24LC41A

TABLE 1-2:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS PORTS)

DDC Monitor Port (Bidirectional mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency (DSCL and
MSCL)

CLK

—

100

—

400

kHz

Clock high time (DSCL and
MSCL)

HIGH

4000

—

600

—

Clock low time (DSCL and
MSCL)

LOW

4700

—

1300

—

DSCL, DSDA, MSCL &
MSDA rise time

—

1000

—

300

(Note 1)

DSCL, DSDA, MSCL &
MSDA fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first clock
pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

min to V

max

—

250

20 + .1

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (DSCL, DSDA, MSCL
& MSDA pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, Vcc = 5.0V, Block mode
(Note 4)

DDC Monitor Port Transmit-only mode Parameters

Output valid from VCLK

VAA

—

2000

—

1000

VCLK high time

VHIGH

4000

—

600

—

VCLK low time

VLOW

4700

—

1300

—

VCLK setup time

VHST

—

VCLK hold time

SPVL

4000

—

600

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up
time

VPU

—

Input filter spike
suppression (VCLK pin)

SPV

—

100

—

100

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

The combined T

and V

HYS

specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 4



2003 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

DDC Monitor Port

2.1.1

TRANSMIT-ONLY MODE

The device will power-up in the Transmit-only mode
at address 00H. This mode supports a unidirectional
2-wire protocol for transmission of the contents of the
memory array.

2.1.2

INITIALIZATION PROCEDURE

After V

has stabilized, the device will be in the

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

SCL

SDA

VCLK

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

VCLK

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 5

24LC41A

2.1.3

BIDIRECTIONAL MODE

C™ bus, and starts to count

C bus, (Figure 2-3) it will switch to the in the

)

. In this protocol, a

2.2

Microcontroller Access Port

FIGURE 2-3:

SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE

FIGURE 2-4:

MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE

Transition mode with possibility to return to Transmit-only mode

Bidirectional

permanently

SCL

SDA

VCLK count = 1 2 n 0

VCLK

Transmit-only
mode

MODE

ACK

n < 128

TVHZ

SCL

SDA

VCLK

Transmit-only

MODE

Bidirectional

Recovery to Transmit-only mode

Bit8

(MSB of data in 00h)

VCLK count = 1 2 3 4 127 128

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 6



2003 Microchip Technology Inc.

FIGURE 2-5:

DISPLAY OPERATION PER DDC

STANDARD PROPOSED BY VESA

Communication

is idle

Is Vsync

present?

Send EDID continuously

using Vsync as clock

High-to-low

transition on

SCL?

Yes

Stop sending EDID.

Switch to DDC2 mode.

Display has

transition state

optional

Set Vsync counter = 0

Change on

VCLK lines?

SCL, SDA or

Yes

High - low

transition on SCL

Reset Vsync counter = 0

Yes

Valid

received?

DDC2 address

VCLK

cycle?

Yes

Increment VCLK counter

Yes

Switch back to DDC1

mode.

DDC2 communication

idle. Display waiting for

address byte.

DDC2B

address

received?

Yes

Receive DDC2B

command

Respond to DDC2B

command

Is display

Access.bus

Yes

Valid Access.bus

address?

Yes

See Access.bus

specification to determine

correct procedure.

Yes

Display Power-on

DDC Circuit Powered

from +5 volts

or start timer

Reset counter or timer

(if appropriate)

Counter=128 or

timer expired?

High-to-low

transition on

SCL?

Yes

Note 1: The base flowchart is copyright



1993, 1994, 1995 Video Electronic Standard Association (VESA) from

VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.

2: The dash box and text “The 24LC41A and ... inside dash box.” are added by Microchip Technology Inc.

3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC41A.

capable?

The 24LC41A was designed to comply to the
portion of flowchart inside dash box.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 7

24LC41A

3.0

BIDIRECTIONAL BUS
CHARACTERISTICS

Characteristics for the Bidirectional bus are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port The following bus pro-
tocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Start condition. All commands must be preceded by a
Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Stop condition. All operations must be ended with a
Stop condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

3.6

Device Addressing

Note:

The microcontroller access port and the
DDC Monitor Port (in Bidirectional mode)
will not generate any Acknowledge bits if
an internal programming cycle is in
progress.

Operation

Control Code

Block Select

R/W

Read

1010

B2B1B0

Write

1010

B2B1B0

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 8



2003 Microchip Technology Inc.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(

)

(B)

(D)

(C)

(

)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

MSCL

MSDA

MSCL

DSDA

STA

START

STOP

HYS

STO

MSCL

MSDA

DSCL

DSDA

STA

HIGH

STO

DAT

BUF

STA

LOW

MSCL

MSDA

OUT

R/W

READ/WRITE

START

SLAVE ADDRESS

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 9

24LC41A

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 10



2003 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

FIGURE 4-3:

VCLK WRITE ENABLE TIMING

S
T
A
R
T

S
T
O
P

BUS ACTIVITY
MASTER

SDA or

BUS ACTIVITY

A
C
K

CONTROL

BYTE

WORD

ADDRESS

DATA

MSDA LINE

VCLK

BUS ACTIVITY
MASTER

DSDA or

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA n

DATAn + 7

DATAn + 1

A
C
K

MSDA LINE

VCLK

SCL

SDA

VCLK

VHST

SPVL

STA

STO

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 1

24LC41A

Features

• Single supply with operation down to 2.5V
• Completely implements DDC1



/DDC2



interface

for monitor identification, including recovery to
DDC1

• Improved noise immunity
• Separate high speed 2-wire bus for

microcontroller access to 4K-bit Serial EEPROM

• Low-power CMOS technology
• 2 mA active current typical
• 20

A standby current typical at 5.5V

• Dual 2-wire serial interface bus, I

™

compatible

• Hardware write-protect for Microcontroller Access

Port

• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes (DDC port) or

16 bytes (4K Port)

• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• 1,000,000 erase/write cycles
• Data retention > 40 years
• 8-pin PDIP package
• Available for extended temperature ranges

Description

• Transmit-only mode for the DDC Monitor Port

• Bidirectional mode for the DDC Monitor Port

• Bidirectional, industry-standard 2-wire bus for the

4K Microcontroller Access Port

C bus. If

Package Type

Block Diagram

Pin Function Table

- Commercial (C):

+70°C

- Industrial (I):

-40

C to

+85

Name

Function

DSCL

Serial Clock for DDC Bidirectional mode
(DDC2)

DSDA

Serial Address and Data I/O(DDC Bus)

VCLK

Serial Clock for DDC Transmit-only mode
(DDC1)

MSCL

Serial clock for 4K-bit MCU port

MSDA

Serial Address and Data I/O for 4K-bit MCU port

MWP

Hardware write-protect for Microcontroller
Access Port

Ground

+2.5V to +5.5V power supply

24
LC
41
A

PDIP

DSCL

VCLK

MSDA

DSDA

Vcc

MWP

MSCL

EDID Table

1K-Bit

4K-Bit

Serial

EEPROM

MSDA

MSCL

DDC M

ito

r P

icr

ocon

ller

cess P

DSDA

VCLK

DSCL

1K/4K 2.5V Dual Mode, Dual Port I

C™ Serial EEPROM

DDC is a trademark of Video Electronics Standards Association.

C is a trademark of Philips Corporation.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 2



2003 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

......................................................................................................... -0.6V to V

+1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-65°C to +125°C

ESD protection on all pins

......................................................................................................................................................≥

4 kV

TABLE 1-1:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0°C to +70°C

Industrial (I):

=-40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

DSCL, DSDA, MSCL & MSDA pins:

High-level input voltage
Low-level input voltage

.7 V

—

.3 V

V
V

Input levels on VCLK pin:

High-level input voltage
Low-level input voltage

2.0

—

.2 V

V
V

≥

2.7V (Note)

< 2.7V (Note)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note)

Low-level output voltage

—

= 3 mA, V

= 2.5V (Note)

Low-level output voltage

—

= 6 mA, V

= 2.5V

Input leakage current

—

±1

=.1V to V

Output leakage current

—

±1

OUT

=.1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, DSCL or MSCL = 400 kHz

Standby current

CCS

—
—

200

= 3.0V, DSDA or MSDA = DSCL

or MSCL = V

= 5.5V, DSDA or MSDA = DSCL

or MSCL = V

CLK

= V

Note:

This parameter is periodically sampled and not 100% tested.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 3

24LC41A

TABLE 1-2:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS PORTS)

DDC Monitor Port (Bidirectional mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency (DSCL and
MSCL)

CLK

—

100

—

400

kHz

Clock high time (DSCL and
MSCL)

HIGH

4000

—

600

—

Clock low time (DSCL and
MSCL)

LOW

4700

—

1300

—

DSCL, DSDA, MSCL &
MSDA rise time

—

1000

—

300

(Note 1)

DSCL, DSDA, MSCL &
MSDA fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first clock
pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

min to V

max

—

250

20 + .1

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (DSCL, DSDA, MSCL
& MSDA pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, Vcc = 5.0V, Block mode
(Note 4)

DDC Monitor Port Transmit-only mode Parameters

Output valid from VCLK

VAA

—

2000

—

1000

VCLK high time

VHIGH

4000

—

600

—

VCLK low time

VLOW

4700

—

1300

—

VCLK setup time

VHST

—

VCLK hold time

SPVL

4000

—

600

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up
time

VPU

—

Input filter spike
suppression (VCLK pin)

SPV

—

100

—

100

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

The combined T

and V

HYS

specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 4



2003 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

DDC Monitor Port

2.1.1

TRANSMIT-ONLY MODE

The device will power-up in the Transmit-only mode
at address 00H. This mode supports a unidirectional
2-wire protocol for transmission of the contents of the
memory array.

2.1.2

INITIALIZATION PROCEDURE

After V

has stabilized, the device will be in the

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

SCL

SDA

VCLK

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

VCLK

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 5

24LC41A

2.1.3

BIDIRECTIONAL MODE

C™ bus, and starts to count

C bus, (Figure 2-3) it will switch to the in the

)

. In this protocol, a

2.2

Microcontroller Access Port

FIGURE 2-3:

SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE

FIGURE 2-4:

MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE

Transition mode with possibility to return to Transmit-only mode

Bidirectional

permanently

SCL

SDA

VCLK count = 1 2 n 0

VCLK

Transmit-only
mode

MODE

ACK

n < 128

TVHZ

SCL

SDA

VCLK

Transmit-only

MODE

Bidirectional

Recovery to Transmit-only mode

Bit8

(MSB of data in 00h)

VCLK count = 1 2 3 4 127 128

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 6



2003 Microchip Technology Inc.

FIGURE 2-5:

DISPLAY OPERATION PER DDC

STANDARD PROPOSED BY VESA

Communication

is idle

Is Vsync

present?

Send EDID continuously

using Vsync as clock

High-to-low

transition on

SCL?

Yes

Stop sending EDID.

Switch to DDC2 mode.

Display has

transition state

optional

Set Vsync counter = 0

Change on

VCLK lines?

SCL, SDA or

Yes

High - low

transition on SCL

Reset Vsync counter = 0

Yes

Valid

received?

DDC2 address

VCLK

cycle?

Yes

Increment VCLK counter

Yes

Switch back to DDC1

mode.

DDC2 communication

idle. Display waiting for

address byte.

DDC2B

address

received?

Yes

Receive DDC2B

command

Respond to DDC2B

command

Is display

Access.bus

Yes

Valid Access.bus

address?

Yes

See Access.bus

specification to determine

correct procedure.

Yes

Display Power-on

DDC Circuit Powered

from +5 volts

or start timer

Reset counter or timer

(if appropriate)

Counter=128 or

timer expired?

High-to-low

transition on

SCL?

Yes

Note 1: The base flowchart is copyright



1993, 1994, 1995 Video Electronic Standard Association (VESA) from

VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.

2: The dash box and text “The 24LC41A and ... inside dash box.” are added by Microchip Technology Inc.

3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC41A.

capable?

The 24LC41A was designed to comply to the
portion of flowchart inside dash box.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 7

24LC41A

3.0

BIDIRECTIONAL BUS
CHARACTERISTICS

Characteristics for the Bidirectional bus are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port The following bus pro-
tocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Start condition. All commands must be preceded by a
Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Stop condition. All operations must be ended with a
Stop condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

3.6

Device Addressing

Note:

The microcontroller access port and the
DDC Monitor Port (in Bidirectional mode)
will not generate any Acknowledge bits if
an internal programming cycle is in
progress.

Operation

Control Code

Block Select

R/W

Read

1010

B2B1B0

Write

1010

B2B1B0

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 8



2003 Microchip Technology Inc.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(

)

(B)

(D)

(C)

(

)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

MSCL

MSDA

MSCL

DSDA

STA

START

STOP

HYS

STO

MSCL

MSDA

DSCL

DSDA

STA

HIGH

STO

DAT

BUF

STA

LOW

MSCL

MSDA

OUT

R/W

READ/WRITE

START

SLAVE ADDRESS

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 9

24LC41A

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 10



2003 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

FIGURE 4-3:

VCLK WRITE ENABLE TIMING

S
T
A
R
T

S
T
O
P

BUS ACTIVITY
MASTER

SDA or

BUS ACTIVITY

A
C
K

CONTROL

BYTE

WORD

ADDRESS

DATA

MSDA LINE

VCLK

BUS ACTIVITY
MASTER

DSDA or

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA n

DATAn + 7

DATAn + 1

A
C
K

MSDA LINE

VCLK

SCL

SDA

VCLK

VHST

SPVL

STA

STO

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 1

24LC41A

Features

• Single supply with operation down to 2.5V
• Completely implements DDC1



/DDC2



interface

for monitor identification, including recovery to
DDC1

• Improved noise immunity
• Separate high speed 2-wire bus for

microcontroller access to 4K-bit Serial EEPROM

• Low-power CMOS technology
• 2 mA active current typical
• 20

A standby current typical at 5.5V

• Dual 2-wire serial interface bus, I

™

compatible

• Hardware write-protect for Microcontroller Access

Port

• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes (DDC port) or

16 bytes (4K Port)

• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• 1,000,000 erase/write cycles
• Data retention > 40 years
• 8-pin PDIP package
• Available for extended temperature ranges

Description

• Transmit-only mode for the DDC Monitor Port

• Bidirectional mode for the DDC Monitor Port

• Bidirectional, industry-standard 2-wire bus for the

4K Microcontroller Access Port

C bus. If

Package Type

Block Diagram

Pin Function Table

- Commercial (C):

+70°C

- Industrial (I):

-40

C to

+85

Name

Function

DSCL

Serial Clock for DDC Bidirectional mode
(DDC2)

DSDA

Serial Address and Data I/O(DDC Bus)

VCLK

Serial Clock for DDC Transmit-only mode
(DDC1)

MSCL

Serial clock for 4K-bit MCU port

MSDA

Serial Address and Data I/O for 4K-bit MCU port

MWP

Hardware write-protect for Microcontroller
Access Port

Ground

+2.5V to +5.5V power supply

24
LC
41
A

PDIP

DSCL

VCLK

MSDA

DSDA

Vcc

MWP

MSCL

EDID Table

1K-Bit

4K-Bit

Serial

EEPROM

MSDA

MSCL

DDC M

ito

r P

icr

ocon

ller

cess P

DSDA

VCLK

DSCL

1K/4K 2.5V Dual Mode, Dual Port I

C™ Serial EEPROM

DDC is a trademark of Video Electronics Standards Association.

C is a trademark of Philips Corporation.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 2



2003 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

......................................................................................................... -0.6V to V

+1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-65°C to +125°C

ESD protection on all pins

......................................................................................................................................................≥

4 kV

TABLE 1-1:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0°C to +70°C

Industrial (I):

=-40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

DSCL, DSDA, MSCL & MSDA pins:

High-level input voltage
Low-level input voltage

.7 V

—

.3 V

V
V

Input levels on VCLK pin:

High-level input voltage
Low-level input voltage

2.0

—

.2 V

V
V

≥

2.7V (Note)

< 2.7V (Note)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note)

Low-level output voltage

—

= 3 mA, V

= 2.5V (Note)

Low-level output voltage

—

= 6 mA, V

= 2.5V

Input leakage current

—

±1

=.1V to V

Output leakage current

—

±1

OUT

=.1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, DSCL or MSCL = 400 kHz

Standby current

CCS

—
—

200

= 3.0V, DSDA or MSDA = DSCL

or MSCL = V

= 5.5V, DSDA or MSDA = DSCL

or MSCL = V

CLK

= V

Note:

This parameter is periodically sampled and not 100% tested.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 3

24LC41A

TABLE 1-2:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS PORTS)

DDC Monitor Port (Bidirectional mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency (DSCL and
MSCL)

CLK

—

100

—

400

kHz

Clock high time (DSCL and
MSCL)

HIGH

4000

—

600

—

Clock low time (DSCL and
MSCL)

LOW

4700

—

1300

—

DSCL, DSDA, MSCL &
MSDA rise time

—

1000

—

300

(Note 1)

DSCL, DSDA, MSCL &
MSDA fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first clock
pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

min to V

max

—

250

20 + .1

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (DSCL, DSDA, MSCL
& MSDA pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, Vcc = 5.0V, Block mode
(Note 4)

DDC Monitor Port Transmit-only mode Parameters

Output valid from VCLK

VAA

—

2000

—

1000

VCLK high time

VHIGH

4000

—

600

—

VCLK low time

VLOW

4700

—

1300

—

VCLK setup time

VHST

—

VCLK hold time

SPVL

4000

—

600

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up
time

VPU

—

Input filter spike
suppression (VCLK pin)

SPV

—

100

—

100

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

The combined T

and V

HYS

specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 4



2003 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

DDC Monitor Port

2.1.1

TRANSMIT-ONLY MODE

The device will power-up in the Transmit-only mode
at address 00H. This mode supports a unidirectional
2-wire protocol for transmission of the contents of the
memory array.

2.1.2

INITIALIZATION PROCEDURE

After V

has stabilized, the device will be in the

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

SCL

SDA

VCLK

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

VCLK

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 5

24LC41A

2.1.3

BIDIRECTIONAL MODE

C™ bus, and starts to count

C bus, (Figure 2-3) it will switch to the in the

)

. In this protocol, a

2.2

Microcontroller Access Port

FIGURE 2-3:

SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE

FIGURE 2-4:

MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE

Transition mode with possibility to return to Transmit-only mode

Bidirectional

permanently

SCL

SDA

VCLK count = 1 2 n 0

VCLK

Transmit-only
mode

MODE

ACK

n < 128

TVHZ

SCL

SDA

VCLK

Transmit-only

MODE

Bidirectional

Recovery to Transmit-only mode

Bit8

(MSB of data in 00h)

VCLK count = 1 2 3 4 127 128

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 6



2003 Microchip Technology Inc.

FIGURE 2-5:

DISPLAY OPERATION PER DDC

STANDARD PROPOSED BY VESA

Communication

is idle

Is Vsync

present?

Send EDID continuously

using Vsync as clock

High-to-low

transition on

SCL?

Yes

Stop sending EDID.

Switch to DDC2 mode.

Display has

transition state

optional

Set Vsync counter = 0

Change on

VCLK lines?

SCL, SDA or

Yes

High - low

transition on SCL

Reset Vsync counter = 0

Yes

Valid

received?

DDC2 address

VCLK

cycle?

Yes

Increment VCLK counter

Yes

Switch back to DDC1

mode.

DDC2 communication

idle. Display waiting for

address byte.

DDC2B

address

received?

Yes

Receive DDC2B

command

Respond to DDC2B

command

Is display

Access.bus

Yes

Valid Access.bus

address?

Yes

See Access.bus

specification to determine

correct procedure.

Yes

Display Power-on

DDC Circuit Powered

from +5 volts

or start timer

Reset counter or timer

(if appropriate)

Counter=128 or

timer expired?

High-to-low

transition on

SCL?

Yes

Note 1: The base flowchart is copyright



1993, 1994, 1995 Video Electronic Standard Association (VESA) from

VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.

2: The dash box and text “The 24LC41A and ... inside dash box.” are added by Microchip Technology Inc.

3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC41A.

capable?

The 24LC41A was designed to comply to the
portion of flowchart inside dash box.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 7

24LC41A

3.0

BIDIRECTIONAL BUS
CHARACTERISTICS

Characteristics for the Bidirectional bus are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port The following bus pro-
tocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Start condition. All commands must be preceded by a
Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Stop condition. All operations must be ended with a
Stop condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

3.6

Device Addressing

Note:

The microcontroller access port and the
DDC Monitor Port (in Bidirectional mode)
will not generate any Acknowledge bits if
an internal programming cycle is in
progress.

Operation

Control Code

Block Select

R/W

Read

1010

B2B1B0

Write

1010

B2B1B0

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 8



2003 Microchip Technology Inc.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(

)

(B)

(D)

(C)

(

)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

MSCL

MSDA

MSCL

DSDA

STA

START

STOP

HYS

STO

MSCL

MSDA

DSCL

DSDA

STA

HIGH

STO

DAT

BUF

STA

LOW

MSCL

MSDA

OUT

R/W

READ/WRITE

START

SLAVE ADDRESS

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 9

24LC41A

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 10



2003 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

FIGURE 4-3:

VCLK WRITE ENABLE TIMING

S
T
A
R
T

S
T
O
P

BUS ACTIVITY
MASTER

SDA or

BUS ACTIVITY

A
C
K

CONTROL

BYTE

WORD

ADDRESS

DATA

MSDA LINE

VCLK

BUS ACTIVITY
MASTER

DSDA or

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA n

DATAn + 7

DATAn + 1

A
C
K

MSDA LINE

VCLK

SCL

SDA

VCLK

VHST

SPVL

STA

STO

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 1

24LC41A

Features

• Single supply with operation down to 2.5V
• Completely implements DDC1



/DDC2



interface

for monitor identification, including recovery to
DDC1

• Improved noise immunity
• Separate high speed 2-wire bus for

microcontroller access to 4K-bit Serial EEPROM

• Low-power CMOS technology
• 2 mA active current typical
• 20

A standby current typical at 5.5V

• Dual 2-wire serial interface bus, I

™

compatible

• Hardware write-protect for Microcontroller Access

Port

• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes (DDC port) or

16 bytes (4K Port)

• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• 1,000,000 erase/write cycles
• Data retention > 40 years
• 8-pin PDIP package
• Available for extended temperature ranges

Description

• Transmit-only mode for the DDC Monitor Port

• Bidirectional mode for the DDC Monitor Port

• Bidirectional, industry-standard 2-wire bus for the

4K Microcontroller Access Port

C bus. If

Package Type

Block Diagram

Pin Function Table

- Commercial (C):

+70°C

- Industrial (I):

-40

C to

+85

Name

Function

DSCL

Serial Clock for DDC Bidirectional mode
(DDC2)

DSDA

Serial Address and Data I/O(DDC Bus)

VCLK

Serial Clock for DDC Transmit-only mode
(DDC1)

MSCL

Serial clock for 4K-bit MCU port

MSDA

Serial Address and Data I/O for 4K-bit MCU port

MWP

Hardware write-protect for Microcontroller
Access Port

Ground

+2.5V to +5.5V power supply

24
LC
41
A

PDIP

DSCL

VCLK

MSDA

DSDA

Vcc

MWP

MSCL

EDID Table

1K-Bit

4K-Bit

Serial

EEPROM

MSDA

MSCL

DDC M

ito

r P

icr

ocon

ller

cess P

DSDA

VCLK

DSCL

1K/4K 2.5V Dual Mode, Dual Port I

C™ Serial EEPROM

DDC is a trademark of Video Electronics Standards Association.

C is a trademark of Philips Corporation.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 2



2003 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

......................................................................................................... -0.6V to V

+1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-65°C to +125°C

ESD protection on all pins

......................................................................................................................................................≥

4 kV

TABLE 1-1:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0°C to +70°C

Industrial (I):

=-40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

DSCL, DSDA, MSCL & MSDA pins:

High-level input voltage
Low-level input voltage

.7 V

—

.3 V

V
V

Input levels on VCLK pin:

High-level input voltage
Low-level input voltage

2.0

—

.2 V

V
V

≥

2.7V (Note)

< 2.7V (Note)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note)

Low-level output voltage

—

= 3 mA, V

= 2.5V (Note)

Low-level output voltage

—

= 6 mA, V

= 2.5V

Input leakage current

—

±1

=.1V to V

Output leakage current

—

±1

OUT

=.1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, DSCL or MSCL = 400 kHz

Standby current

CCS

—
—

200

= 3.0V, DSDA or MSDA = DSCL

or MSCL = V

= 5.5V, DSDA or MSDA = DSCL

or MSCL = V

CLK

= V

Note:

This parameter is periodically sampled and not 100% tested.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 3

24LC41A

TABLE 1-2:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS PORTS)

DDC Monitor Port (Bidirectional mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency (DSCL and
MSCL)

CLK

—

100

—

400

kHz

Clock high time (DSCL and
MSCL)

HIGH

4000

—

600

—

Clock low time (DSCL and
MSCL)

LOW

4700

—

1300

—

DSCL, DSDA, MSCL &
MSDA rise time

—

1000

—

300

(Note 1)

DSCL, DSDA, MSCL &
MSDA fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first clock
pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

min to V

max

—

250

20 + .1

250

(Note 1), C

≤

100 pF

Input filter spike suppres-
sion (DSCL, DSDA, MSCL
& MSDA pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

—

cycles

25°C, Vcc = 5.0V, Block mode
(Note 4)

DDC Monitor Port Transmit-only mode Parameters

Output valid from VCLK

VAA

—

2000

—

1000

VCLK high time

VHIGH

4000

—

600

—

VCLK low time

VLOW

4700

—

1300

—

VCLK setup time

VHST

—

VCLK hold time

SPVL

4000

—

600

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up
time

VPU

—

Input filter spike
suppression (VCLK pin)

SPV

—

100

—

100

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

The combined T

and V

HYS

specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 4



2003 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

DDC Monitor Port

2.1.1

TRANSMIT-ONLY MODE

The device will power-up in the Transmit-only mode
at address 00H. This mode supports a unidirectional
2-wire protocol for transmission of the contents of the
memory array.

2.1.2

INITIALIZATION PROCEDURE

After V

has stabilized, the device will be in the

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

SCL

SDA

VCLK

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

VCLK

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 5

24LC41A

2.1.3

BIDIRECTIONAL MODE

C™ bus, and starts to count

C bus, (Figure 2-3) it will switch to the in the

)

. In this protocol, a

2.2

Microcontroller Access Port

FIGURE 2-3:

SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE

FIGURE 2-4:

MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE

Transition mode with possibility to return to Transmit-only mode

Bidirectional

permanently

SCL

SDA

VCLK count = 1 2 n 0

VCLK

Transmit-only
mode

MODE

ACK

n < 128

TVHZ

SCL

SDA

VCLK

Transmit-only

MODE

Bidirectional

Recovery to Transmit-only mode

Bit8

(MSB of data in 00h)

VCLK count = 1 2 3 4 127 128

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 6



2003 Microchip Technology Inc.

FIGURE 2-5:

DISPLAY OPERATION PER DDC

STANDARD PROPOSED BY VESA

Communication

is idle

Is Vsync

present?

Send EDID continuously

using Vsync as clock

High-to-low

transition on

SCL?

Yes

Stop sending EDID.

Switch to DDC2 mode.

Display has

transition state

optional

Set Vsync counter = 0

Change on

VCLK lines?

SCL, SDA or

Yes

High - low

transition on SCL

Reset Vsync counter = 0

Yes

Valid

received?

DDC2 address

VCLK

cycle?

Yes

Increment VCLK counter

Yes

Switch back to DDC1

mode.

DDC2 communication

idle. Display waiting for

address byte.

DDC2B

address

received?

Yes

Receive DDC2B

command

Respond to DDC2B

command

Is display

Access.bus

Yes

Valid Access.bus

address?

Yes

See Access.bus

specification to determine

correct procedure.

Yes

Display Power-on

DDC Circuit Powered

from +5 volts

or start timer

Reset counter or timer

(if appropriate)

Counter=128 or

timer expired?

High-to-low

transition on

SCL?

Yes

Note 1: The base flowchart is copyright



1993, 1994, 1995 Video Electronic Standard Association (VESA) from

VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.

2: The dash box and text “The 24LC41A and ... inside dash box.” are added by Microchip Technology Inc.

3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC41A.

capable?

The 24LC41A was designed to comply to the
portion of flowchart inside dash box.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 7

24LC41A

3.0

BIDIRECTIONAL BUS
CHARACTERISTICS

Characteristics for the Bidirectional bus are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port The following bus pro-
tocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Start condition. All commands must be preceded by a
Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Stop condition. All operations must be ended with a
Stop condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

3.6

Device Addressing

Note:

The microcontroller access port and the
DDC Monitor Port (in Bidirectional mode)
will not generate any Acknowledge bits if
an internal programming cycle is in
progress.

Operation

Control Code

Block Select

R/W

Read

1010

B2B1B0

Write

1010

B2B1B0

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 8



2003 Microchip Technology Inc.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(

)

(B)

(D)

(C)

(

)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

MSCL

MSDA

MSCL

DSDA

STA

START

STOP

HYS

STO

MSCL

MSDA

DSCL

DSDA

STA

HIGH

STO

DAT

BUF

STA

LOW

MSCL

MSDA

OUT

R/W

READ/WRITE

START

SLAVE ADDRESS

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html



2003 Microchip Technology Inc.

DS21176D-page 9

24LC41A

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21176d-html.html

24LC41A

DS21176D-page 10



2003 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

FIGURE 4-3:

VCLK WRITE ENABLE TIMING

S
T
A
R
T

S
T
O
P

BUS ACTIVITY
MASTER

SDA or

BUS ACTIVITY

A
C
K

CONTROL

BYTE

WORD

ADDRESS

DATA

MSDA LINE

VCLK

BUS ACTIVITY
MASTER

DSDA or

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA n

DATAn + 7

DATAn + 1

A
C
K

MSDA LINE

VCLK

SCL

SDA

VCLK

VHST

SPVL

STA

STO

Maker

Microchip Technology Inc.

Datasheet PDF Download

24LC41A Data Sheet Datasheet

24LC41A 1K/4K 2.5V Dual Mode, Dual Port I2C Serial EEPROM

24LC41A 1K/4K 2.5V Dual Mode, Dual Port I2C Serial EEPROM