2011-2015 Microchip Technology Inc.
DS20002270E-page 1
24AA1026/24LC1026/24FC1026
Device Selection Table
Features
• Low-Power CMOS Technology:
- Read current 450 µA, maximum
- Standby current 5 µA, maximum
• 2-Wire Serial Interface, I
2
C Compatible
• Cascadable up to Four Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 128-Byte Page Write Buffer
• Hardware Write-Protect
• Electrostatic Discharge (ESD) Protection >4000V
• More than One Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC and SOIJ
• RoHS Compliant
• Temperature Ranges:
- Industrial (I):
-40
C to +85C
- Automotive (E): -40
C to +125C
Description
The Microchip Technology Incorporated
24AA1026/24LC1026/24FC1026 (24XX1026*) is a
128K x 8 (1024 Kbit) Serial Electrically Erasable
PROM, capable of operation across a broad voltage
range (1.7V to 5.5V).
It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device has both byte write and page
write capability of up to 128 bytes of data.
This device is capable of both random and sequential
reads. Reads may be sequential within address
boundaries 0000h to FFFFh and 10000h to 1FFFFh.
Functional address lines allow up to four devices on the
same data bus. This allows for up to 4 Mbits total
system EEPROM memory. This device is available in
the standard 8-pin PDIP, SOIC and SOIJ packages.
Package Type
Block Diagram
*24XX1026 is used in this document as a generic part
number for the 24AA1026/24LC1026/24FC1026
devices.
Part
Number
V
CC
Range
Max. Clock
Frequency
Temp.
Ranges
24AA1026
1.7V-5.5V
400 kHz
(
1)
I
24LC1026
2.5V-5.5V
400 kHz
(
2
)
I, E
24FC1026
1.8V-5.5V
1 MHz
(
3
)
I
Note 1:
100 kHz for V
CC
< 2.5V
2:
100 kHz for V
CC
< 4.5V (E-temp)
3:
400 kHz for V
CC
< 2.5V
NC
A1
A2
V
SS
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
24
X
X
1
02
6
8-Lead PDIP
8-Lead SOIC/SOIJ
NC
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24
X
X
1
02
6
HV Generator
EEPROM
Page Latches
YDEC
XDEC
Sense AMP
Memory
I/O
I/O
A1A2
SDA
SCL
V
CC
V
SS
WP
R/W Control
Array
Control
Logic
Control
Logic
1024K I
2
C Serial EEPROM
24AA1026/24LC1026/24FC1026
DS20002270E-page 2
2011-2015 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
.......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
TABLE 1-1:
DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V
T
A
= -40°C to +85°C
Automotive (E):
V
CC
= +2.5V to 5.5V
T
A
= -40°C to +125°C
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
D1
V
IH
High-Level Input Voltage
0.7 V
CC
—
V
D2
V
IL
Low-Level Input Voltage
—
0.3 V
CC
V
V
CC
2.5V
0.2 V
CC
V
V
CC
< 2.5V
D3
V
HYS
Hysteresis of Schmitt
Trigger Inputs
(SDA, SCL pins)
0.05 V
CC
—
V
V
CC
2.5V (
Note
)
D4
V
OL
Low-Level Output Voltage
—
0.40
V
I
OL
= 3.0 mA @ V
CC
= 4.5V
I
OL
= 2.1 mA @ V
CC
= 2.5V
D5
I
LI
Input Leakage Current
—
±1
µA
V
IN
= V
SS
or V
CC
V
IN
= V
SS
or V
CC
D6
I
LO
Output Leakage Current
—
±1
µA
V
OUT
= V
SS
or V
CC
D7
C
IN
,
C
OUT
Pin Capacitance
(all inputs/outputs)
—
10
pF
V
CC
= 5.0V (
Note
)
T
A
= 25°C, F
CLK
= 1 MHz
D8
I
CCREAD
Operating Current
—
450
µA
V
CC
= 5.5V, SCL = 400 kHz
I
CCWRITE
—
5
mA
V
CC
= 5.5V
D9
I
CCS
Standby Current
—
5
µA
SCL = SDA = V
CC
= 5.5V
A1 = A2 = WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
2011-2015 Microchip Technology Inc.
DS20002270E-page 3
24AA1026/24LC1026/24FC1026
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Automotive (E): Vcc = +2.5V to 5.5V T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
1
F
CLK
Clock Frequency
—
100
kHz
1.7V
V
CC
2.5V
—
100
kHz
2.5V
V
CC
4.5V, E-temp
—
400
kHz
2.5V
V
CC
5.5V
—
400
kHz
1.8V
V
CC
2.5V (24FC1026)
—
1000
kHz
2.5V
V
CC
5.5V (24FC1026)
2
T
HIGH
Clock High Time
4000
—
ns
1.7V
V
CC
2.5V
4000
—
ns
2.5V
V
CC
4.5V, E-temp
600
—
ns
2.5V
V
CC
5.5V
600
—
ns
1.8V
V
CC
2.5V (24FC1026)
500
—
ns
2.5V
V
CC
5.5V (24FC1026)
3
T
LOW
Clock Low Time
4700
—
ns
1.7V
V
CC
2.5V
4700
—
ns
2.5V
V
CC
4.5V, E-temp
1300
—
ns
2.5V
V
CC
5.5V
1300
—
ns
1.8V
V
CC
2.5V (24FC1026)
500
—
ns
2.5V
V
CC
5.5V (24FC1026)
4
T
R
SDA and SCL Rise Time
(
Note 1
)
—
1000
ns
1.7V
V
CC
2.5V
—
1000
ns
2.5V
V
CC
4.5V, E-temp
—
300
ns
2.5V
V
CC
5.5V
—
300
ns
1.8V
V
CC
2.5V (24FC1026)
—
300
ns
2.5V
V
CC
5.5V (24FC1026)
5
T
F
SDA and SCL Fall Time
(
Note 1
)
—
300
ns
All except 24FC1026
—
100
ns
1.8V
V
CC
5.5V (24FC1026)
6
T
HD
:
STA
Start Condition Hold Time
4000
—
ns
1.7V
V
CC
2.5V
4000
—
ns
2.5V
V
CC
4.5V, E-temp
600
—
ns
2.5V
V
CC
5.5V
600
—
ns
1.8V
V
CC
2.5V (24FC1026)
250
—
ns
2.5V
V
CC
5.5V (24FC1026)
7
T
SU
:
STA
Start Condition Setup
Time
4700
—
ns
1.7V
V
CC
2.5V
4700
—
ns
2.5V
V
CC
4.5V, E-temp
600
—
ns
2.5V
V
CC
5.5V
600
—
ns
1.8V
V
CC
2.5V (24FC1026)
250
—
ns
2.5V
V
CC
5.5V (24FC1026)
8
T
HD
:
DAT
Data Input Hold Time
0
—
ns
(
Note 2
)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
24AA1026/24LC1026/24FC1026
DS20002270E-page 4
2011-2015 Microchip Technology Inc.
9
T
SU
:
DAT
Data Input Setup Time
250
—
ns
1.7V
V
CC
2.5V
250
—
ns
2.5V
V
CC
4.5V, E-temp
100
—
ns
2.5V
V
CC
5.5V
100
—
ns
1.8V
V
CC
2.5V (24FC1026)
100
—
ns
2.5V
V
CC
5.5V (24FC1026)
10
T
SU
:
STO
Stop Condition Setup
Time
4000
—
ns
1.7V
V
CC
2.5V
4000
—
ns
2.5V
V
CC
4.5V, E-temp
600
—
ns
2.5V
V
CC
5.5V
600
—
ns
1.8V
V
CC
2.5V (24FC1026)
250
—
ns
2.5V
V
CC
5.5V (24FC1026)
11
T
SU
:
WP
WP Setup Time
4000
—
ns
1.7V
V
CC
2.5V
4000
—
ns
2.5V
V
CC
4.5V, E-temp
600
—
ns
2.5V
V
CC
5.5V
600
—
ns
1.8V
V
CC
2.5V (24FC1026)
600
—
ns
2.5V
V
CC
5.5V (24FC1026)
12
T
HD
:
WP
WP Hold Time
4700
—
ns
1.7V
V
CC
2.5V
4700
—
ns
2.5V
V
CC
4.5V, E-temp
1300
—
ns
2.5V
V
CC
5.5V
1300
—
ns
1.8V
V
CC
2.5V (24FC1026)
1300
—
ns
2.5V
V
CC
5.5V (24FC1026)
13
T
AA
Output Valid from Clock
(
Note 2
)
—
3500
ns
1.7V
V
CC
2.5V
—
3500
ns
2.5V
V
CC
4.5V, E-temp
—
900
ns
2.5V
V
CC
5.5V
—
900
ns
1.8V
V
CC
2.5V (24FC1026)
—
400
ns
2.5V
V
CC
5.5V (24FC1026)
14
T
BUF
Bus Free Time: bus time
must be free before a new
transmission can start
4700
—
ns
1.7V
V
CC
2.5V
4700
—
ns
2.5V
V
CC
4.5V, E-temp
1300
—
ns
2.5V
V
CC
5.5V
1300
—
ns
1.8V
V
CC
2.5V (24FC1026)
500
—
ns
2.5V
V
CC
5.5V (24FC1026)
15
T
SP
Input Filter Spike
Suppression
(SDA and SCL pins)
—
50
ns
All except 24FC1026 (
Notes 1
and
3
)
16
T
WC
Write Cycle Time (byte or
page)
—
5
ms
17
Endurance
1,000,000
—
cycles Page mode, 25°C, V
CC
= 5.5V (
Note 4
)
AC CHARACTERISTICS (Continued)
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Automotive (E): Vcc = +2.5V to 5.5V T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
2011-2015 Microchip Technology Inc.
DS20002270E-page 5
24AA1026/24LC1026/24FC1026
FIGURE 1-1:
BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
15
3
2
8
9
13
D3
4
10
11
12
14
24AA1026/24LC1026/24FC1026
DS20002270E-page 6
2011-2015 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in
Table 2-1
.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
A1, A2 Chip Address Inputs
The A1 and A2 inputs are used by the 24XX1026 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A1 and A2 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an
open-drain terminal, therefore, the SDA bus requires a
pull-up resistor to V
CC
(typical 10 k
for 100 kHz, 2 k
for 400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.4
Write-Protect (WP)
This pin must be connected to either V
SS
or V
CC
. If tied
to V
SS
, write operations are enabled. If tied to V
CC
,
write operations are inhibited, but read operations are
not affected.
3.0
FUNCTIONAL DESCRIPTION
The 24XX1026 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX1026 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated.
Name
PDIP
SOIC
SOIJ
Function
NC
1
1
1
Not Connected
A1
2
2
2
User Configurable Chip Select
A2
3
3
3
User Configurable Chip Select
V
SS
4
4
4
Ground
SDA
5
5
5
Serial Data
SCL
6
6
6
Serial Clock
WP
7
7
7
Write-Protect Input
V
CC
8
8
8
+1.7 to 5.5V (24AA1026)
+2.5 to 5.5V (24LC1026)
+1.8 to 5.5V (24FC1026)
2011-2015 Microchip Technology Inc.
DS20002270E-page 7
24AA1026/24LC1026/24FC1026
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (
Figure 4-1
).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
A device that acknowledges must pull-down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX1026) will leave the data line high to enable
the master to generate the Stop condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2:
ACKNOWLEDGE TIMING
Note:
The 24XX1026 does not generate any
Acknowledge bits if an internal
programming cycle is in progress,
however, the control byte that is being
polled must match the control byte used to
initiate the write cycle.
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCL
SDA
(A)
(B)
(D)
(D)
(C)
(A)
SCL
9
8
7
6
5
4
3
2
1
1
2
3
The transmitter must release the SDA line at this
point allowing the receiver to pull the SDA line low
to acknowledge the previous eight bits of data.
The receiver must release the SDA line at
this point so the transmitter can continue
sending data.
SDA
Acknowledge
Bit
Data from transmitter
Data from transmitter
24AA1026/24LC1026/24FC1026
DS20002270E-page 8
2011-2015 Microchip Technology Inc.
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (
Figure 5-1
).
The control byte consists of a 4-bit control code; for the
24XX1026, this is set as ‘1010’ binary for read and
write operations. The next two bits of the control byte
are the Chip Select bits (A2, A1). The Chip Select bits
allow the use of up to four 24XX1026 devices on the
same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2
and A1 pins for the device to respond. These bits are in
effect the two Most Significant bits (MSb) of the word
address. The next bit of the control byte is the block
select bit (B0). This bit acts as the A16 address bit for
accessing the entire array.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected, and when set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (
Figure 5-2
). The upper
address bits are transferred first, followed by the Least
Significant bits (LSb).
Following the Start condition, the 24XX1026 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24XX1026 will select a read
or write operation.
This device has an internal addressing boundary
limitation that is divided into two segments of 512K bits.
Block select bit ‘B0’ is used to control access to each
segment.
FIGURE 5-1:
CONTROL BYTE
FORMAT
5.1
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2 and A1 can be used to expand
the contiguous address space for up to 4 Mbit by
adding up to four 24XX1026’s on the same bus. In this
case, software can use A1 of the control byte as
address bit A17 and A2 as address bit A18. It is not
possible to sequentially read across device
boundaries.
Each device has internal addressing boundary
limitations. This divides each part into two segments of
512K bits. The block select bit ‘B0’ controls access to
each “half”.
Sequential read operations are limited to 512K blocks.
To read through four devices on the same bus, eight
random Read commands must be given.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
1
0
1
0
A2
A1
B0
S
ACK
R/W
Control Code
Chip
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
Select
Block
Select
Bit
1
0
1
0
A
2
A
1
B
0 R/W
A
11
A
10
A
9
A
7
A
0
A
8
•
•
•
•
•
•
A
12
Control Byte
Address High Byte
Address Low Byte
Control
Code
Chip
Select
Bits
A
13
A
14
Block
Select
Bit
A
15
2011-2015 Microchip Technology Inc.
DS20002270E-page 9
24AA1026/24LC1026/24FC1026
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the Start condition from the master, the
control code (four bits), the Chip Select (two bits), the
block select (one bit), and the R/W bit (which is a logic
low) are clocked onto the bus by the master transmitter.
This indicates to the addressed slave receiver that the
address high byte will follow after it has generated an
Acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the master is
the high-order byte of the word address and will be
written into the Address Pointer of the 24XX1026. The
next byte is the Least Significant Address Byte. After
receiving another Acknowledge signal from the
24XX1026, the master device will transmit the data
word to be written into the addressed memory location.
The 24XX1026 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and during this time, the 24XX1026 will not
generate Acknowledge signals as long as the control
byte being polled matches the control byte that was
used to initiate the write (
Figure 6-1
). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
6.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX1026 in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to 127 additional
bytes, which are temporarily stored in the on-chip page
buffer and will be written into memory after the master
has transmitted a Stop condition. After receipt of each
word, the seven lower Address Pointer bits are
internally incremented by one. If the master should
transmit more than 128 bytes prior to generating the
Stop condition, the address counter will roll over and
the previously received data will be overwritten. As with
the byte write operation, once the Stop condition is
received, an internal write cycle will begin (
Figure 6-2
).
If an attempt is made to write to the array with the WP
pin held high, the device will acknowledge the
command, but no write cycle will occur, no data will be
written and the device will immediately accept a new
command.
6.3
Write Protection
The WP pin allows the user to write-protect the entire
array (00000-1FFFF) when the pin is tied to V
CC
. If tied
to V
SS
the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(
Figure 1-1
). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note:
When doing a write of less than 128 bytes
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, for this reason
endurance is specified per page.
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of [page size – 1]. If
a Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
24AA1026/24LC1026/24FC1026
DS20002270E-page 10
2011-2015 Microchip Technology Inc.
FIGURE 6-1:
BYTE WRITE
FIGURE 6-2:
PAGE WRITE
Bus Activity
Master
SDA LINE
BUS ACTIVITY
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Data
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
S 1 0 1 0
0
A
2
A
1
B
0
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Data Byte 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte 127
A
C
K
S 1 0 1 0
0
A
2
A
1
B
0
P