2012-2015 Microchip Technology Inc.
DS20005142C-page 1
23A1024/23LC1024
Device Selection Table
Features
• SPI Bus Interface:
- SPI compatible
- SDI (dual) and SQI (quad) compatible
- 20 MHz Clock rate for all modes
• Low-Power CMOS Technology:
- Read Current: 3 mA at 5.5V, 20 MHz
- Standby Current: 4
A at +85°C
• Unlimited Read and Write Cycles
• Zero Write Time
• 128K x 8-bit Organization:
- 32-byte page
• Byte, Page and Sequential Mode for Reads and
Writes
• High Reliability
• Temperature Ranges Supported:
• RoHS Compliant
• 8 Lead SOIC, TSSOP and PDIP Packages
Pin Function Table
Description
The Microchip Technology Inc. 23A1024/23LC1024
are 1 Mbit Serial SRAM devices. The memory is
accessed via a simple Serial Peripheral Interface (SPI)
compatible serial bus. The bus signals required are a
clock input (SCK), a data in line (SI) and a data out line
(SO). Access to the device is controlled through a Chip
Select (CS) input. Additionally, SDI (Serial Dual
Interface) and SQI (Serial Quad Interface) is supported
if your application needs faster data rates.
This device also supports unlimited reads and writes to
the memory array.
The 23A1024/23LC1024 is available in standard
packages including 8-lead SOIC, PDIP and advanced
8-lead TSSOP.
Package Types (not to scale)
Part
Number
V
CC
Range
Temp.
Ranges
Dual I/O
(SDI)
Quad I/O
(SQI)
Max. Clock
Frequency
Packages
23A1024
1.7-2.2V
I, E
Yes
Yes
20 MHz
(1)
SN, ST, P
23LC1024
2.5-5.5V
I, E
Yes
Yes
20 MHz
(1)
SN, ST, P
Note 1:
16 MHz for E-temp.
- Industrial (I):
-40
C to +85C
- Automotive (E):
-40
C to +125C
Name
Function
CS
Chip Select Input Pin
SO/SIO1
Serial Output/SDI/SQI Pin
SIO2
SQI Pin
V
SS
Ground Pin
SI/SIO0
Serial Input/SDI/SQI Pin
SCK
Serial Clock Pin
HOLD/SIO3
Hold/SQI Pin
V
CC
Power Supply Pin
CS
SO/SIO1
SIO2
V
SS
V
CC
HOLD/SIO3
SCK
SI/SIO0
1
2
3
4
8
7
6
5
SOIC/TSSOP/PDIP
1Mbit SPI Serial SRAM with SDI and SQI Interface
23A1024/23LC1024
DS20005142C-page 2
2012-2015 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All Inputs and Outputs w.r.t. V
SS
........................................................................................................ -0.3V to V
CC
+0.3V
Storage Temperature...............................................................................................................................-65°C to +150°C
Ambient Temperature under Bias............................................................................................................-40°C to +125°C
TABLE 1-1:
DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C
Automotive (E): T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Typ.
(3)
Max.
Units
Test Conditions
D001
V
CC
Supply Voltage
1.7
—
2.2
V
23A1024
2.5
5.5
V
23LC1024
D002
V
IH
High-level Input
Voltage
0.7V
CC
—
V
CC
+ 0.3
V
D003
V
IL
Low-level Input
Voltage
-0.3
—
0.2 V
CC
V
23A1024
0.1 V
CC
V
23LC1024
D004
V
OL
Low-level Output
Voltage
—
—
0.2
V
I
OL
= 1 mA
D005
V
OH
High-level Output
Voltage
V
CC
- 0.5
—
—
V
I
OH
= -400
A
D006
I
LI
Input Leakage
Current
—
—
±1
A
CS = V
CC
, V
IN
= V
SS
OR V
CC
D007
I
LO
Output Leakage
Current
—
—
±1
A
CS = V
CC
, V
OUT
= V
SS
OR V
CC
D008
I
CC
Read Operating Current
—
1
10
mA
F
CLK
= 20 MHz; SO = O, 2.2V
3
10
mA
F
CLK
= 20 MHz; SO = O, 5.5V
D009
I
CCS
Standby Current
—
1
4
A
CS = V
CC
= 2.2V, Inputs tied to
V
CC
or V
SS
, I-Temp
—
12
A
CS = V
CC
= 2.2V, Inputs tied to
V
CC
or V
SS
, E-Temp
4
10
A
CS = V
CC
= 5.5V, Inputs tied to
V
CC
or V
SS
, I-Temp
—
20
A
CS = V
CC
= 5.5V, Inputs tied to
V
CC
or V
SS
, E-Temp
D010
C
INT
Input Capacitance
—
—
7
pF
V
CC
= 5.0V, f = 1 MHz, T
A
= 25°C
(
Note 1
)
D011
V
DR
RAM Data Retention
Voltage
—
1.0
—
V
(
Note 2
)
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
This is the limit to which V
CC
can be lowered without losing RAM data. This parameter is periodically
sampled and not 100% tested.
3:
Typical measurements taken at room temperature.
2012-2015 Microchip Technology Inc.
DS20005142C-page 3
23A1024/23LC1024
TABLE 1-3:
AC TEST CONDITIONS
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C
Automotive (E): T
A
= -40°C to +125°C
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
1
F
CLK
Clock Frequency
—
20
MHz
I-Temp
16
MHz
E-Temp
2
T
CSS
CS Setup Time
25
—
ns
I-Temp
32
—
ns
E-Temp
3
T
CSH
CS Hold Time
50
—
ns
4
T
CSD
CS Disable Time
25
—
ns
I-Temp
32
—
ns
E-Temp
5
T
SU
Data Setup Time
10
—
ns
6
T
HD
Data Hold Time
10
—
ns
7
T
R
CLK Rise Time
—
20
ns
(
Note 1
)
8
T
F
CLK Fall Time
—
20
ns
(
Note 1
)
9
T
HI
Clock High Time
25
—
ns
I-Temp
32
—
ns
E-Temp
10
T
LO
Clock Low Time
25
—
ns
I-Temp
32
—
ns
E-Temp
11
T
CLD
Clock Delay Time
25
—
ns
I-Temp
32
—
ns
E-Temp
12
T
V
Output Valid from Clock Low
—
25
ns
I-Temp
32
ns
E-Temp
13
T
HO
Output Hold Time
0
—
ns
(
Note 1
)
14
T
DIS
Output Disable Time
—
20
ns
15
T
HS
HOLD Setup Time
10
—
ns
16
T
HH
HOLD Hold Time
10
—
ns
17
T
HZ
HOLD Low to Output High-Z
10
—
ns
18
T
HV
HOLD High to Output Valid
—
50
ns
Note 1:
This parameter is periodically sampled and not 100% tested.
AC Waveform
Input Pulse Level
0.1 V
CC
to 0.9 V
CC
Input Rise/Fall Time
5 ns
C
L
= 30 pF
—
Timing Measurement Reference Level
Input
0.5 V
CC
Output
0.5 V
CC
23A1024/23LC1024
DS20005142C-page 4
2012-2015 Microchip Technology Inc.
FIGURE 1-1:
HOLD TIMING
FIGURE 1-2:
SERIAL INPUT TIMING (SPI MODE)
FIGURE 1-3:
SERIAL OUTPUT TIMING (SPI MODE)
CS
SCK
SO
SI
HOLD
16
15
15
16
18
17
Don’t Care
5
High-Impedance
n + 2
n + 1
n
n - 1
n
n + 2
n + 1
n
n
n - 1
CS
SCK
SI
SO
6
5
8
7
11
3
LSB in
MSB in
High-Impedance
2
4
CS
SCK
SO
10
9
12
MSB out
LSB out
3
14
Don’t Care
SI
13
2012-2015 Microchip Technology Inc.
DS20005142C-page 5
23A1024/23LC1024
2.0
FUNCTIONAL DESCRIPTION
2.1
Principles of Operation
The 23A1024/23LC1024 is an 1 Mbit Serial SRAM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC
®
microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
firmware to match the SPI protocol. In addition, the
23A1024/23LC1024 is capable of operation in SDI and
SQI modes. In SDI mode, the SI and SO data lines are
bidirectional, allowing the transfer of two bits per clock
pulse. In SQI mode, two additional data lines enable
the transfer of four bits per clock pulse.
The 23A1024/23LC1024 contains an 8-bit instruction
register. The device is accessed via the SI pin, with
data being clocked in on the rising edge of SCK. The
CS pin must be low for the entire operation.
Table 2-1
contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
2.2
Modes of Operation
The 23X1024 has three modes of operation that are
selected by setting bits 7 and 6 in the MODE register.
The modes of operation are Byte, Page and Burst.
Byte Operation – is selected when bits 7 and 6 in the
MODE register are set to 00. In this mode, the
read/write operations are limited to only one byte. The
Command followed by the 24-bit address is clocked into
the device and the data to/from the device is transferred
on the next eight clocks (
Figure 2-1
,
Figure 2-2
).
Page Operation – is selected when bits 7 and 6 in the
MODE register are set to 10. The 23X1024 has
4096 pages of 32 bytes. In this mode, the read and write
operations are limited to within the addressed page (the
address is automatically incremented internally). If the
data being read or written reaches the page boundary,
then the internal address counter will increment to the
start of the page (
Figure 2-3
,
Figure 2-4
).
Sequential Operation – is selected when bits 7 and 6
in the MODE register are set to 01. Sequential
operation allows the entire array to be written to and
read from. The internal address counter is automatically
incremented and page boundaries are ignored. When
the internal address counter reaches the end of the
array, the address counter will roll over to 0x00000
(
Figure 2-5
,
Figure 2-6
).
2.3
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ
instruction is transmitted to the
23A1024/23LC1024 followed by the 24-bit address,
with the first seven MSB’s of the address being “don’t
care” bits. After the correct READ instruction and
address are sent, the data stored in the memory at the
selected address is shifted out on the SO pin.
If operating in Sequential mode, the data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
Address Pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached (1FFFFh),
the address counter rolls over to address 00000h,
allowing the read cycle to be continued indefinitely.
The read operation is terminated by raising the CS
pin.
2.4
Write Sequence
Prior to any attempt to write data to the
23A1024/23LC1024, the device must be selected by
bringing CS low.
Once the device is selected, the Write command can
be started by issuing a WRITE instruction, followed by
the 24-bit address, with the first seven MSB’s of the
address being “don’t care” bits, and then the data to be
written. A write is terminated by the CS being brought
high.
If operating in Page mode, after the initial data byte is
shifted in, additional bytes can be shifted into the
device. The Address Pointer is automatically
incremented. This operation can continue for the entire
page (32 bytes) before data will start to be overwritten.
If operating in Sequential mode, after the initial data
byte is shifted in, additional bytes can be clocked into
the device. The internal Address Pointer is
automatically incremented. When the Address Pointer
reaches the highest address (1FFFFh), the address
counter rolls over to (00000h). This allows the
operation to continue indefinitely, however, previous
data will be overwritten.
23A1024/23LC1024
DS20005142C-page 6
2012-2015 Microchip Technology Inc.
FIGURE 2-1:
BYTE READ SEQUENCE (SPI MODE)
FIGURE 2-2:
BYTE WRITE SEQUENCE (SPI MODE)
TABLE 2-1:
INSTRUCTION SET
Instruction Name
Instruction Format
Hex
Code
Description
READ
0000 0011
0x03
Read data from memory array beginning at selected address
WRITE
0000 0010
0x02
Write data to memory array beginning at selected address
EDIO
0011 1011
0x3B
Enter Dual I/O access (enter SDI bus mode)
EQIO
0011 1000
0x38
Enter Quad I/O access (enter SQI bus mode)
RSTIO
1111 1111
0xFF
Reset Dual and Quad I/O access (revert to SPI bus mode)
RDMR
0000 0101
0x05
Read Mode Register
WRMR
0000 0001
0x01
Write Mode Register
SO
SI
SCK
CS
0
2
3
4
5
6
7
8
9 10 11
29 30 31 32 33 34 35 36 37 38 39
1
0
1
0
0
0
0
0
1
23 22 21 20
2
1
0
7
6
5
4
3
2
1
0
Instruction
24-bit Address
Data Out
High-Impedance
SO
SI
CS
9 10 11
29 30 31 32 33 34 35 36 37 38 39
0
0
0
0
0
0
0
1
23 22 21 20
2
1
0
7
6
5
4
3
2
1
0
Instruction
24-bit Address
Data Byte
High-Impedance
SCK
0
2
3
4
5
6
7
1
8
2012-2015 Microchip Technology Inc.
DS20005142C-page 7
23A1024/23LC1024
FIGURE 2-3:
PAGE READ SEQUENCE (SPI MODE)
FIGURE 2-4:
PAGE WRITE SEQUENCE (SPI MODE)
7
6
5
4
3
2
1
0
Page X, Word Y
SI
CS
9 10 11
29 30 31 32 33 34 35 36 37 38 39
23 22 21 20
2
1
0
24-bit Address
SCK
0
2
3
4
5
6
7
1
8
SO
CS
7
6
5
4
3
2
1
0
Page X, Word 0
SCK
40
42 43 44 45 46 47
41
7
6
5
4
3
2
1
0
Page X, Word 31
7
6
5
4
3
2
1
0
Page X, Word Y+1
Page X, Word Y
SO
High-Impedance
SI
0
1
0
0
0
0
0
1
Instruction
SI
CS
9 10 11
29 30 31 32 33 34 35 36 37 38 39
23 22 21 20
2
1
0
7
6
5
4
3
2
1
0
24-bit Address
SCK
0
2
3
4
5
6
7
1
8
CS
SI
7
6
5
4
3
2
1
0
Page X, Word 0
7
6
5
4
3
2
1
0
Page X, Word 31
7
6
5
4
3
2
1
0
Page X, Word Y+1
Page X, Word Y
Page X, Word Y
SCK
40
42 43 44 45 46 47
41
0
0
0
0
0
0
0
1
Instruction
SO
High-Impedance
SO
High-Impedance
23A1024/23LC1024
DS20005142C-page 8
2012-2015 Microchip Technology Inc.
FIGURE 2-5:
SEQUENTIAL READ SEQUENCE (SPI MODE)
SI
CS
9 10 11
29 30 31 32 33 34 35 36 37 38 39
23 22 21 20
2
1
0
7
6
5
4
3
2
1
0
Instruction
24-bit Address
Page X, Word Y
SCK
0
2
3
4
5
6
7
1
8
SO
CS
7
6
5
4
3
2
1
0
Page X+1, Word 1
SCK
7
6
5
4
3
2
1
0
Page X+1, Word 0
7
6
5
4
3
2
1
0
Page X, Word 31
SO
CS
7
6
5
4
3
2
1
0
Page X+n, Word 31
SCK
7
6
5
4
3
2
1
0
Page X+n, Word 1
7
6
5
4
3
2
1
0
Page X+1, Word 31
SO
SI
SI
0
1
0
0
0
0
0
1
2012-2015 Microchip Technology Inc.
DS20005142C-page 9
23A1024/23LC1024
FIGURE 2-6:
SEQUENTIAL WRITE SEQUENCE (SPI MODE)
SI
CS
9 10 11
29 30 31 32 33 34 35 36 37 38 39
0
0
0
0
0
0
0
1
23 22 21 20
2
1
0
7
6
5
4
3
2
1
0
Instruction
24-bit Address
Data Byte 1
SCK
0
2
3
4
5
6
7
1
8
SI
CS
49 50 51
54 55
7
6
5
4
3
2
1
0
Data Byte n
SCK
40
42 43 44 45 46 47
41
48
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
1
0
Data Byte 2
52 53
SO
High-Impedance
SO
High-Impedance
23A1024/23LC1024
DS20005142C-page 10
2012-2015 Microchip Technology Inc.
2.5
Read Mode Register Instruction
(RDMR)
The Read Mode Register instruction (RDMR) provides
access to the MODE register. The MODE register may
be read at any time. The MODE register is formatted as
follows:
TABLE 2-2:
MODE REGISTER
The mode bits indicate the operating mode of the
SRAM. The possible modes of operation are:
0 0
= Byte mode
1 0
= Page mode
0 1
= Sequential mode (default operation)
1 1
= Reserved
Bits 0 through 5 are reserved and should always be set
to ‘0’.
See
Figure 2-7
for the RDMR timing sequence.
FIGURE 2-7:
READ MODE REGISTER TIMING SEQUENCE (RDMR)
7
6
5
4
3
2
1
0
W/R
W/R
–
–
–
–
–
–
MODE
MODE
0
0
0
0
0
0
W/R = writable/readable
SO
SI
CS
9
10
11
12
13
14
15
1
1
0
0
0
0
0
0
7
6
5
4
2
1
0
Instruction
Data from MODE Register
High-Impedance
SCK
0
2
3
4
5
6
7
1
8
3