21163E.book | Datasheet Lookup

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

2004 Microchip Technology Inc.

DS21163E-page 1

FEATURES

• Voltage operating range: 4.5V to 5.5V

- Maximum write current 3 mA at 5.5V
- Standby current 1

A typical at 5.0V

• 2-wire serial interface bus, I



compatible

• 100 kHz and 400 kHz compatibility
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Hardware write protect
• 1,000,000 Erase/Write cycles guaranteed
• 32-byte page or byte write modes available
• Schmitt trigger filtered inputs for noise suppres-

sion

• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the

same bus for up to 256K bits total memory

• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges

DESCRIPTION

The Microchip Technology Inc. 24C32A is a 4K x 8
(32K bit) Serial Electrically Erasable PROM. It has
been developed for advanced, low power applications
such as personal communications or data acquisition.
The 24C32A also has a page-write capability of up to
32 bytes of data. The 24C32A is capable of both ran-
dom and sequential reads up to the 32K boundary.
Functional address lines allow up to eight 24C32A
devices on the same bus, for up to 256K bits address
space. Advanced CMOS technology and broad voltage
range make this device ideal for low-power/low-volt-
age, nonvolatile code and data applications. The
24C32A is available in the standard 8-pin plastic DIP
and both 150 mil and 200 mil SOIC packaging.

- Commercial (C):

0°C to

70°C

- Industrial (I):

-40°C to

+85°C

- Automotive (E):

-40°C to +125°C

PACKAGE TYPES

BLOCK DIAGRAM

24
C

Vss

Vcc

SCL

SDA

Vss

Vcc

SCL

SDA

PDIP

SOIC

24
C

32A

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

I/O

A0 A1 A2

24C32A

32K 5.0V I

™

Serial EEPROM

C is a trademark of Philips Corporation.

Obsolete Device

Please use 24LC32A.

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24C32A

DS21163E-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL
CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins

..................................................≥

4 kV

*Notice: Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

A0,A1,A2

User Configurable Chip Selects

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

Write Protect Input

+4.5V to 5.5V Power Supply

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

Vcc = +4.5V to 5.5V
Commercial (C): Tamb =

0°C to

+70°C

Industrial (I):

Tamb = -40°C to

+85°C

Automotive(E): Tamb

= -40°C to +125°C

Parameter

Symbol

Min

Typ

Max

Units

Conditions

A0, A1, A2, SCL , SDA and WP
pins:

High level input voltage

.7 V

—

Low level input voltage

—

.3 Vcc

Hysteresis of Schmitt Trigger
inputs

HYS

.05

—

(Note)

Low level output voltage

—

.40

= 3.0 mA

Input leakage current

-10

= .1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance
(all inputs/outputs)

, C

OUT

—

= 5.0V (Note)

Tamb = 25°C, F

= 1 MHz

Operating current

Write

—

= 5.5V, SCL = 400 kHz

Read

—

0.5

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

A SCL = SDA = V

= 5.5V

WP = V

, A0, A1, A2 = V

Note:

This parameter is periodically sampled and not 100% tested.

SCL

SDA

STA

STO

HYS

START

STOP

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2004 Microchip Technology Inc.

DS21163E-page 3

24C32A

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Vcc = 4.5-5.5

Units

Remarks

Min

Max

Clock frequency

CLK

—

100

kHz

Clock high time

HIGH

4000

—

Clock low time

LOW

4700

—

SDA and SCL rise time

—

1000

(Note 1)

SDA and SCL fall time

—

300

(Note 1)

START condition hold time

STA

4000

—

After this period the first clock
pulse is generated

START condition setup time

STA

4700

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

STOP condition setup time

STO

4000

—

Output valid from clock

—

3500

(Note 2)

Bus free time

BUF

4700

—

Time the bus must be free before
a new transmission can start

Output fall time from V

min to

max

—

250

(Note 1), C

≤

100 pF

Input filter spike suppression
(SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Endurance

—

cycles

25°C, Vcc = 5.0V, Block Mode
(Note 4)

Note 1: Not 100% tested. C

= Total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to Schmitt trigger inputs which provide improved noise

and spike suppression. This eliminates the need for a Ti specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

SCL

SDA
IN

SDA

OUT

STA

HIGH

STO

DAT

BUF

STA

LOW

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24C32A

DS21163E-page 4

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2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

The 24C32A supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the Serial Clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C32A works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.

A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24C32A) will leave the data line HIGH to
enable the master to generate the STOP condition.

Note:

The 24C32A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(C)

(A)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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2004 Microchip Technology Inc.

DS21163E-page 5

24C32A

3.6

Device Addressing

A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code; for the 24C32A this is
set as 1010 binary for read and write (R/W) operations.
The next three bits of the control byte are the device
select bits (A2, A1, A0). They are used by the master
device to select which of the eight devices are to be
accessed. These bits are in effect the three most signif-
icant bits of the word address. The last bit of the control
byte defines the operation to be performed. When set
to a one a read operation is selected, and when set to
a zero a write operation is selected. The next two bytes
received define the address of the first data byte
(Figure 3-3). Because only A11...A0 are used, the
upper four address bits must be zeros. The most signif-
icant bit of the most significant byte of the address is
transferred first.

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

R/W

READ/WRITE

START

SLAVE ADDRESS

Following the start condition, the 24C32A monitors the
SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24C32A will select a read or
write operation.

Operation

Control

Code

Device Select

R/W

Read

1010

Device Address

Write

1010

Device Address

FIGURE 3-3:

ADDRESS SEQUENCE BIT ASSIGNMENTS

0 R/W

•

SLAVE

ADDRESS

DEVICE

SELECT

BUS

CONTROL BYTE

ADDRESS BYTE 1

ADDRESS BYTE 0

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24C32A

DS21163E-page 6

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2004 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

Following the start condition from the master, the con-
trol code (four bits), the device select (three bits), and
the R/W bit which is a logic low are clocked onto the bus
by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow after it has generated an acknowl-
edge bit during the ninth clock cycle. Therefore, the
next byte transmitted by the master is the high-order
byte of the word address and will be written into the
address pointer of the 24C32A. The next byte is the
least significant address byte. After receiving another
acknowledge signal from the 24C32A the master
device will transmit the data word to be written into the
addressed memory location.

The 24C32A acknowledges again and the master gen-
erates a stop condition. This initiates the internal write
cycle, and during this time the 24C32A will not gener-
ate acknowledge signals (Figure 4-1).

4.2

Page Write

The write control byte, word address and the first data
byte are transmitted to the 24C32A in the same way as
in a byte write. But instead of generating a stop condi-
tion, the master transmits up to 32 bytes which are tem-
porarily stored in the on-chip page buffer and will be
written into memory after the master has transmitted a
stop condition. After receipt of each word, the five lower
address pointer bits are internally incremented by one.
If the master should transmit more than 32 bytes prior
to generating the stop condition, the address counter
will roll over and the previously received data will be
overwritten. As with the byte write operation, once the
stop condition is received, an internal write cycle will
begin. (Figure 4-2).

Note:

Page write operations are limited to writing
bytes within a single physical page, regard-
less of the number of bytes actually being
written. Physical page boundaries start at
addresses that are integer multiples of the
page buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

DATA

A
C
K

S
T
O
P

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

DATA BYTE 0

A
C
K

S
T
O
P

DATA BYTE 31

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2004 Microchip Technology Inc.

DS21163E-page 7

24C32A

5.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. Acknowledge
Polling (ACK) can be initiated immediately. This
involves the master sending a start condition followed
by the control byte for a write command (R/W = 0). If the
device is still busy with the write cycle, then NO ACK
will be returned. If the cycle is complete, then the
device will return the ACK and the master can then pro-
ceed with the next read or write command. See
Figure 5-1 for flow diagram.

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

6.0

READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.

6.1

Current Address Read

The 24C32A contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n (n is
any legal address), the next current address read oper-
ation would access data from address n + 1. Upon
receipt of the slave address with R/W bit set to one, the
24C32A issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24C32A discontinues transmission (Figure 6-1).

6.2

Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C32A as part of a write operation (R/W bit set to
zero). After the word address is sent, the master gen-
erates a start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal address pointer is set. Then the master issues the
control byte again but with the R/W bit set to a one. The
24C32A will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24C32A to discontinue transmission
(Figure 6-2).

FIGURE 6-1:

CURRENT ADDRESS READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL BYTE

DATA BYTE

S
T
O
P

A
C
K

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24C32A

DS21163E-page 8



2004 Microchip Technology Inc.

6.3

Contiguous Addressing Across
Multiple Devices

The device select bits A2, A1, A0 can be used to
expand the contiguous address space for up to 256K
bits by adding up to eight 24C32A's on the same bus.
In this case, software can use A0 of the control byte as
address bit A12, A1 as address bit A13, and A2 as
address bit A14.

6.4

Sequential Read

Sequential reads are initiated in the same way as a ran-
dom read except that after the 24C32A transmits the
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24C32A to transmit the
next sequentially addressed 8-bit word (Figure 6-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition.

To provide sequential reads the 24C32A contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The internal address pointer will
automatically roll over from address 0FFF to address
000 if the master acknowledges the byte received from
the array address 0FFF.

FIGURE 6-2:

RANDOM READ

FIGURE 6-3:

SEQUENTIAL READ

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

S
T
O
P

A
C
K

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

CONTROL

BYTE

DATA

BYTE

A
C
K

S
T
A
R
T

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

A
C
K

DATA n

DATA n + 1

DATA n + 2

DATA n + x

S
T
O
P

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2004 Microchip Technology Inc.

DS21163E-page 9

24C32A

7.0

PIN DESCRIPTIONS

7.1

A0, A1, A2 Chip Address Inputs

The A0..A2 inputs are used by the 24C32A for multiple
device operation and conform to the 2-wire bus stan-
dard. The levels applied to these pins define the
address block occupied by the device in the address
map. A particular device is selected by transmitting the
corresponding bits (A2, A1, A0) in the control byte
(Figure 3-3).

7.2

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

(typical 10K

Ω

for 100 kHz, 2 K

Ω

for

400 kHz)

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.

7.3

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

7.4

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-FFF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

8.0

NOISE PROTECTION

The SCL and SDA inputs have filter circuits which sup-
press noise spikes to ensure proper device operation
even on a noisy bus. All I/O lines incorporate Schmitt
triggers for 400 kHz (Fast Mode) compatibility.

9.0

POWER MANAGEMENT

This design incorporates a power standby mode when
the device is not in use and automatically powers off
after the normal termination of any operation when a
stop bit is received and all internal functions are com-
plete. This includes any error conditions, i.e., not
receiving an acknowledge or stop condition per the
two-wire bus specification. The device also incorpo-
rates V

monitor circuitry to prevent inadvertent writes

(data corruption) during low-voltage conditions. The
V

monitor circuitry is powered off when the device is

in standby mode in order to further reduce power con-
sumption.

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24C32A

24C32A Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Package:

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body, EIAJ standard)

SM = Plastic SOIC (207 mil Body, EIAJ standard)

Temperature

Blank =

C to +70

Range:

= -40

C to +85

E = -40

C to +125

Device:

24C32A

32K I

C Serial EEPROM (100 kHz, 400 kHz)

24C32AT

32K I

C Serial EEPROM (Tape and Reel)

24C32A

DS21163E-page 10



2004 Microchip Technology Inc.

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

2004 Microchip Technology Inc.

DS21163E-page 1

FEATURES

• Voltage operating range: 4.5V to 5.5V

- Maximum write current 3 mA at 5.5V
- Standby current 1

A typical at 5.0V

• 2-wire serial interface bus, I



compatible

sion

• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the

same bus for up to 256K bits total memory

• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges

DESCRIPTION

- Commercial (C):

0°C to

70°C

- Industrial (I):

-40°C to

+85°C

- Automotive (E):

-40°C to +125°C

PACKAGE TYPES

BLOCK DIAGRAM

24
C

Vss

Vcc

SCL

SDA

Vss

Vcc

SCL

SDA

PDIP

SOIC

24
C

32A

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

I/O

A0 A1 A2

24C32A

32K 5.0V I

™

Serial EEPROM

C is a trademark of Philips Corporation.

Obsolete Device

Please use 24LC32A.

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24C32A

DS21163E-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL
CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

..................................................≥

4 kV

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

A0,A1,A2

User Configurable Chip Selects

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

Write Protect Input

+4.5V to 5.5V Power Supply

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

Vcc = +4.5V to 5.5V
Commercial (C): Tamb =

0°C to

+70°C

Industrial (I):

Tamb = -40°C to

+85°C

Automotive(E): Tamb

= -40°C to +125°C

Parameter

Symbol

Min

Typ

Max

Units

Conditions

A0, A1, A2, SCL , SDA and WP
pins:

High level input voltage

.7 V

—

Low level input voltage

—

.3 Vcc

Hysteresis of Schmitt Trigger
inputs

HYS

.05

—

(Note)

Low level output voltage

—

.40

= 3.0 mA

Input leakage current

-10

= .1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance
(all inputs/outputs)

, C

OUT

—

= 5.0V (Note)

Tamb = 25°C, F

= 1 MHz

Operating current

Write

—

= 5.5V, SCL = 400 kHz

Read

—

0.5

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

A SCL = SDA = V

= 5.5V

WP = V

, A0, A1, A2 = V

Note:

This parameter is periodically sampled and not 100% tested.

SCL

SDA

STA

STO

HYS

START

STOP

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

2004 Microchip Technology Inc.

DS21163E-page 3

24C32A

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Vcc = 4.5-5.5

Units

Remarks

Min

Max

Clock frequency

CLK

—

100

kHz

Clock high time

HIGH

4000

—

Clock low time

LOW

4700

—

SDA and SCL rise time

—

1000

(Note 1)

SDA and SCL fall time

—

300

(Note 1)

START condition hold time

STA

4000

—

After this period the first clock
pulse is generated

START condition setup time

STA

4700

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

STOP condition setup time

STO

4000

—

Output valid from clock

—

3500

(Note 2)

Bus free time

BUF

4700

—

Time the bus must be free before
a new transmission can start

Output fall time from V

min to

max

—

250

(Note 1), C

≤

100 pF

Input filter spike suppression
(SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Endurance

—

cycles

25°C, Vcc = 5.0V, Block Mode
(Note 4)

Note 1: Not 100% tested. C

= Total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to Schmitt trigger inputs which provide improved noise

and spike suppression. This eliminates the need for a Ti specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

SCL

SDA
IN

SDA

OUT

STA

HIGH

STO

DAT

BUF

STA

LOW

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24C32A

DS21163E-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

Note:

The 24C32A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(C)

(A)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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

2004 Microchip Technology Inc.

DS21163E-page 5

24C32A

3.6

Device Addressing

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

R/W

READ/WRITE

START

SLAVE ADDRESS

Operation

Control

Code

Device Select

R/W

Read

1010

Device Address

Write

1010

Device Address

FIGURE 3-3:

ADDRESS SEQUENCE BIT ASSIGNMENTS

0 R/W

•

SLAVE

ADDRESS

DEVICE

SELECT

BUS

CONTROL BYTE

ADDRESS BYTE 1

ADDRESS BYTE 0

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24C32A

DS21163E-page 6



2004 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

DATA

A
C
K

S
T
O
P

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

DATA BYTE 0

A
C
K

S
T
O
P

DATA BYTE 31

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

2004 Microchip Technology Inc.

DS21163E-page 7

24C32A

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

6.0

READ OPERATION

6.1

Current Address Read

6.2

Random Read

FIGURE 6-1:

CURRENT ADDRESS READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL BYTE

DATA BYTE

S
T
O
P

A
C
K

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24C32A

DS21163E-page 8



2004 Microchip Technology Inc.

6.3

Contiguous Addressing Across
Multiple Devices

6.4

Sequential Read

FIGURE 6-2:

RANDOM READ

FIGURE 6-3:

SEQUENTIAL READ

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

S
T
O
P

A
C
K

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

CONTROL

BYTE

DATA

BYTE

A
C
K

S
T
A
R
T

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

A
C
K

DATA n

DATA n + 1

DATA n + 2

DATA n + x

S
T
O
P

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

2004 Microchip Technology Inc.

DS21163E-page 9

24C32A

7.0

PIN DESCRIPTIONS

7.1

A0, A1, A2 Chip Address Inputs

7.2

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

(typical 10K

Ω

for 100 kHz, 2 K

Ω

for

400 kHz)

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.

7.3

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

7.4

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-FFF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

8.0

NOISE PROTECTION

9.0

POWER MANAGEMENT

monitor circuitry to prevent inadvertent writes

(data corruption) during low-voltage conditions. The
V

monitor circuitry is powered off when the device is

in standby mode in order to further reduce power con-
sumption.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21163E-html.html

24C32A

24C32A Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

Sales and Support

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Package:

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body, EIAJ standard)

SM = Plastic SOIC (207 mil Body, EIAJ standard)

Temperature

Blank =

C to +70

Range:

= -40

C to +85

E = -40

C to +125

Device:

24C32A

32K I

C Serial EEPROM (100 kHz, 400 kHz)

24C32AT

32K I

C Serial EEPROM (Tape and Reel)

24C32A

DS21163E-page 10



2004 Microchip Technology Inc.

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

2004 Microchip Technology Inc.

DS21163E-page 1

FEATURES

• Voltage operating range: 4.5V to 5.5V

- Maximum write current 3 mA at 5.5V
- Standby current 1

A typical at 5.0V

• 2-wire serial interface bus, I



compatible

sion

• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the

same bus for up to 256K bits total memory

• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges

DESCRIPTION

- Commercial (C):

0°C to

70°C

- Industrial (I):

-40°C to

+85°C

- Automotive (E):

-40°C to +125°C

PACKAGE TYPES

BLOCK DIAGRAM

24
C

Vss

Vcc

SCL

SDA

Vss

Vcc

SCL

SDA

PDIP

SOIC

24
C

32A

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

I/O

A0 A1 A2

24C32A

32K 5.0V I

™

Serial EEPROM

C is a trademark of Philips Corporation.

Obsolete Device

Please use 24LC32A.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21163E-html.html

24C32A

DS21163E-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL
CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

..................................................≥

4 kV

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

A0,A1,A2

User Configurable Chip Selects

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

Write Protect Input

+4.5V to 5.5V Power Supply

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

Vcc = +4.5V to 5.5V
Commercial (C): Tamb =

0°C to

+70°C

Industrial (I):

Tamb = -40°C to

+85°C

Automotive(E): Tamb

= -40°C to +125°C

Parameter

Symbol

Min

Typ

Max

Units

Conditions

A0, A1, A2, SCL , SDA and WP
pins:

High level input voltage

.7 V

—

Low level input voltage

—

.3 Vcc

Hysteresis of Schmitt Trigger
inputs

HYS

.05

—

(Note)

Low level output voltage

—

.40

= 3.0 mA

Input leakage current

-10

= .1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance
(all inputs/outputs)

, C

OUT

—

= 5.0V (Note)

Tamb = 25°C, F

= 1 MHz

Operating current

Write

—

= 5.5V, SCL = 400 kHz

Read

—

0.5

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

A SCL = SDA = V

= 5.5V

WP = V

, A0, A1, A2 = V

Note:

This parameter is periodically sampled and not 100% tested.

SCL

SDA

STA

STO

HYS

START

STOP

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

2004 Microchip Technology Inc.

DS21163E-page 3

24C32A

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Vcc = 4.5-5.5

Units

Remarks

Min

Max

Clock frequency

CLK

—

100

kHz

Clock high time

HIGH

4000

—

Clock low time

LOW

4700

—

SDA and SCL rise time

—

1000

(Note 1)

SDA and SCL fall time

—

300

(Note 1)

START condition hold time

STA

4000

—

After this period the first clock
pulse is generated

START condition setup time

STA

4700

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

STOP condition setup time

STO

4000

—

Output valid from clock

—

3500

(Note 2)

Bus free time

BUF

4700

—

Time the bus must be free before
a new transmission can start

Output fall time from V

min to

max

—

250

(Note 1), C

≤

100 pF

Input filter spike suppression
(SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Endurance

—

cycles

25°C, Vcc = 5.0V, Block Mode
(Note 4)

Note 1: Not 100% tested. C

= Total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to Schmitt trigger inputs which provide improved noise

and spike suppression. This eliminates the need for a Ti specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

SCL

SDA
IN

SDA

OUT

STA

HIGH

STO

DAT

BUF

STA

LOW

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21163E-html.html

24C32A

DS21163E-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

Note:

The 24C32A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(C)

(A)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21163E-html.html



2004 Microchip Technology Inc.

DS21163E-page 5

24C32A

3.6

Device Addressing

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

R/W

READ/WRITE

START

SLAVE ADDRESS

Operation

Control

Code

Device Select

R/W

Read

1010

Device Address

Write

1010

Device Address

FIGURE 3-3:

ADDRESS SEQUENCE BIT ASSIGNMENTS

0 R/W

•

SLAVE

ADDRESS

DEVICE

SELECT

BUS

CONTROL BYTE

ADDRESS BYTE 1

ADDRESS BYTE 0

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24C32A

DS21163E-page 6



2004 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

DATA

A
C
K

S
T
O
P

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

DATA BYTE 0

A
C
K

S
T
O
P

DATA BYTE 31

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

2004 Microchip Technology Inc.

DS21163E-page 7

24C32A

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

6.0

READ OPERATION

6.1

Current Address Read

6.2

Random Read

FIGURE 6-1:

CURRENT ADDRESS READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL BYTE

DATA BYTE

S
T
O
P

A
C
K

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21163E-html.html

24C32A

DS21163E-page 8



2004 Microchip Technology Inc.

6.3

Contiguous Addressing Across
Multiple Devices

6.4

Sequential Read

FIGURE 6-2:

RANDOM READ

FIGURE 6-3:

SEQUENTIAL READ

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

S
T
O
P

A
C
K

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

CONTROL

BYTE

DATA

BYTE

A
C
K

S
T
A
R
T

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

A
C
K

DATA n

DATA n + 1

DATA n + 2

DATA n + x

S
T
O
P

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21163E-html.html



2004 Microchip Technology Inc.

DS21163E-page 9

24C32A

7.0

PIN DESCRIPTIONS

7.1

A0, A1, A2 Chip Address Inputs

7.2

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

(typical 10K

Ω

for 100 kHz, 2 K

Ω

for

400 kHz)

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.

7.3

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

7.4

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-FFF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

8.0

NOISE PROTECTION

9.0

POWER MANAGEMENT

monitor circuitry to prevent inadvertent writes

(data corruption) during low-voltage conditions. The
V

monitor circuitry is powered off when the device is

in standby mode in order to further reduce power con-
sumption.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21163E-html.html

24C32A

24C32A Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

Sales and Support

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Package:

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body, EIAJ standard)

SM = Plastic SOIC (207 mil Body, EIAJ standard)

Temperature

Blank =

C to +70

Range:

= -40

C to +85

E = -40

C to +125

Device:

24C32A

32K I

C Serial EEPROM (100 kHz, 400 kHz)

24C32AT

32K I

C Serial EEPROM (Tape and Reel)

24C32A

DS21163E-page 10



2004 Microchip Technology Inc.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21163E-html.html



2004 Microchip Technology Inc.

DS21163E-page 1

FEATURES

• Voltage operating range: 4.5V to 5.5V

- Maximum write current 3 mA at 5.5V
- Standby current 1

A typical at 5.0V

• 2-wire serial interface bus, I



compatible

sion

• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the

same bus for up to 256K bits total memory

• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges

DESCRIPTION

- Commercial (C):

0°C to

70°C

- Industrial (I):

-40°C to

+85°C

- Automotive (E):

-40°C to +125°C

PACKAGE TYPES

BLOCK DIAGRAM

24
C

Vss

Vcc

SCL

SDA

Vss

Vcc

SCL

SDA

PDIP

SOIC

24
C

32A

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

I/O

A0 A1 A2

24C32A

32K 5.0V I

™

Serial EEPROM

C is a trademark of Philips Corporation.

Obsolete Device

Please use 24LC32A.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21163E-html.html

24C32A

DS21163E-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL
CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

..................................................≥

4 kV

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

A0,A1,A2

User Configurable Chip Selects

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

Write Protect Input

+4.5V to 5.5V Power Supply

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

Vcc = +4.5V to 5.5V
Commercial (C): Tamb =

0°C to

+70°C

Industrial (I):

Tamb = -40°C to

+85°C

Automotive(E): Tamb

= -40°C to +125°C

Parameter

Symbol

Min

Typ

Max

Units

Conditions

A0, A1, A2, SCL , SDA and WP
pins:

High level input voltage

.7 V

—

Low level input voltage

—

.3 Vcc

Hysteresis of Schmitt Trigger
inputs

HYS

.05

—

(Note)

Low level output voltage

—

.40

= 3.0 mA

Input leakage current

-10

= .1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance
(all inputs/outputs)

, C

OUT

—

= 5.0V (Note)

Tamb = 25°C, F

= 1 MHz

Operating current

Write

—

= 5.5V, SCL = 400 kHz

Read

—

0.5

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

A SCL = SDA = V

= 5.5V

WP = V

, A0, A1, A2 = V

Note:

This parameter is periodically sampled and not 100% tested.

SCL

SDA

STA

STO

HYS

START

STOP

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2004 Microchip Technology Inc.

DS21163E-page 3

24C32A

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Vcc = 4.5-5.5

Units

Remarks

Min

Max

Clock frequency

CLK

—

100

kHz

Clock high time

HIGH

4000

—

Clock low time

LOW

4700

—

SDA and SCL rise time

—

1000

(Note 1)

SDA and SCL fall time

—

300

(Note 1)

START condition hold time

STA

4000

—

After this period the first clock
pulse is generated

START condition setup time

STA

4700

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

STOP condition setup time

STO

4000

—

Output valid from clock

—

3500

(Note 2)

Bus free time

BUF

4700

—

Time the bus must be free before
a new transmission can start

Output fall time from V

min to

max

—

250

(Note 1), C

≤

100 pF

Input filter spike suppression
(SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Endurance

—

cycles

25°C, Vcc = 5.0V, Block Mode
(Note 4)

Note 1: Not 100% tested. C

= Total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to Schmitt trigger inputs which provide improved noise

and spike suppression. This eliminates the need for a Ti specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

SCL

SDA
IN

SDA

OUT

STA

HIGH

STO

DAT

BUF

STA

LOW

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24C32A

DS21163E-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

Note:

The 24C32A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(C)

(A)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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

2004 Microchip Technology Inc.

DS21163E-page 5

24C32A

3.6

Device Addressing

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

R/W

READ/WRITE

START

SLAVE ADDRESS

Operation

Control

Code

Device Select

R/W

Read

1010

Device Address

Write

1010

Device Address

FIGURE 3-3:

ADDRESS SEQUENCE BIT ASSIGNMENTS

0 R/W

•

SLAVE

ADDRESS

DEVICE

SELECT

BUS

CONTROL BYTE

ADDRESS BYTE 1

ADDRESS BYTE 0

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24C32A

DS21163E-page 6



2004 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

DATA

A
C
K

S
T
O
P

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

DATA BYTE 0

A
C
K

S
T
O
P

DATA BYTE 31

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

2004 Microchip Technology Inc.

DS21163E-page 7

24C32A

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

6.0

READ OPERATION

6.1

Current Address Read

6.2

Random Read

FIGURE 6-1:

CURRENT ADDRESS READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL BYTE

DATA BYTE

S
T
O
P

A
C
K

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24C32A

DS21163E-page 8



2004 Microchip Technology Inc.

6.3

Contiguous Addressing Across
Multiple Devices

6.4

Sequential Read

FIGURE 6-2:

RANDOM READ

FIGURE 6-3:

SEQUENTIAL READ

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

S
T
O
P

A
C
K

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

CONTROL

BYTE

DATA

BYTE

A
C
K

S
T
A
R
T

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

A
C
K

DATA n

DATA n + 1

DATA n + 2

DATA n + x

S
T
O
P

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2004 Microchip Technology Inc.

DS21163E-page 9

24C32A

7.0

PIN DESCRIPTIONS

7.1

A0, A1, A2 Chip Address Inputs

7.2

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

(typical 10K

Ω

for 100 kHz, 2 K

Ω

for

400 kHz)

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.

7.3

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

7.4

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-FFF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

8.0

NOISE PROTECTION

9.0

POWER MANAGEMENT

monitor circuitry to prevent inadvertent writes

(data corruption) during low-voltage conditions. The
V

monitor circuitry is powered off when the device is

in standby mode in order to further reduce power con-
sumption.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21163E-html.html

24C32A

24C32A Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

Sales and Support

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Package:

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body, EIAJ standard)

SM = Plastic SOIC (207 mil Body, EIAJ standard)

Temperature

Blank =

C to +70

Range:

= -40

C to +85

E = -40

C to +125

Device:

24C32A

32K I

C Serial EEPROM (100 kHz, 400 kHz)

24C32AT

32K I

C Serial EEPROM (Tape and Reel)

24C32A

DS21163E-page 10



2004 Microchip Technology Inc.

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

2004 Microchip Technology Inc.

DS21163E-page 1

FEATURES

• Voltage operating range: 4.5V to 5.5V

- Maximum write current 3 mA at 5.5V
- Standby current 1

A typical at 5.0V

• 2-wire serial interface bus, I



compatible

sion

• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the

same bus for up to 256K bits total memory

• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges

DESCRIPTION

- Commercial (C):

0°C to

70°C

- Industrial (I):

-40°C to

+85°C

- Automotive (E):

-40°C to +125°C

PACKAGE TYPES

BLOCK DIAGRAM

24
C

Vss

Vcc

SCL

SDA

Vss

Vcc

SCL

SDA

PDIP

SOIC

24
C

32A

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

I/O

A0 A1 A2

24C32A

32K 5.0V I

™

Serial EEPROM

C is a trademark of Philips Corporation.

Obsolete Device

Please use 24LC32A.

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24C32A

DS21163E-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL
CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

..................................................≥

4 kV

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

A0,A1,A2

User Configurable Chip Selects

Ground

SDA

Serial Address/Data I/O

SCL

Serial Clock

Write Protect Input

+4.5V to 5.5V Power Supply

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

Vcc = +4.5V to 5.5V
Commercial (C): Tamb =

0°C to

+70°C

Industrial (I):

Tamb = -40°C to

+85°C

Automotive(E): Tamb

= -40°C to +125°C

Parameter

Symbol

Min

Typ

Max

Units

Conditions

A0, A1, A2, SCL , SDA and WP
pins:

High level input voltage

.7 V

—

Low level input voltage

—

.3 Vcc

Hysteresis of Schmitt Trigger
inputs

HYS

.05

—

(Note)

Low level output voltage

—

.40

= 3.0 mA

Input leakage current

-10

= .1V to V

Output leakage current

-10

OUT

= .1V to V

Pin capacitance
(all inputs/outputs)

, C

OUT

—

= 5.0V (Note)

Tamb = 25°C, F

= 1 MHz

Operating current

Write

—

= 5.5V, SCL = 400 kHz

Read

—

0.5

= 5.5V, SCL = 400 kHz

Standby current

CCS

—

A SCL = SDA = V

= 5.5V

WP = V

, A0, A1, A2 = V

Note:

This parameter is periodically sampled and not 100% tested.

SCL

SDA

STA

STO

HYS

START

STOP

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2004 Microchip Technology Inc.

DS21163E-page 3

24C32A

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

Vcc = 4.5-5.5

Units

Remarks

Min

Max

Clock frequency

CLK

—

100

kHz

Clock high time

HIGH

4000

—

Clock low time

LOW

4700

—

SDA and SCL rise time

—

1000

(Note 1)

SDA and SCL fall time

—

300

(Note 1)

START condition hold time

STA

4000

—

After this period the first clock
pulse is generated

START condition setup time

STA

4700

—

Only relevant for repeated
START condition

Data input hold time

DAT

—

Data input setup time

DAT

250

—

STOP condition setup time

STO

4000

—

Output valid from clock

—

3500

(Note 2)

Bus free time

BUF

4700

—

Time the bus must be free before
a new transmission can start

Output fall time from V

min to

max

—

250

(Note 1), C

≤

100 pF

Input filter spike suppression
(SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Endurance

—

cycles

25°C, Vcc = 5.0V, Block Mode
(Note 4)

Note 1: Not 100% tested. C

= Total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

specifications are due to Schmitt trigger inputs which provide improved noise

and spike suppression. This eliminates the need for a Ti specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

SCL

SDA
IN

SDA

OUT

STA

HIGH

STO

DAT

BUF

STA

LOW

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24C32A

DS21163E-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

Note:

The 24C32A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(C)

(A)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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

2004 Microchip Technology Inc.

DS21163E-page 5

24C32A

3.6

Device Addressing

FIGURE 3-2:

CONTROL BYTE
ALLOCATION

R/W

READ/WRITE

START

SLAVE ADDRESS

Operation

Control

Code

Device Select

R/W

Read

1010

Device Address

Write

1010

Device Address

FIGURE 3-3:

ADDRESS SEQUENCE BIT ASSIGNMENTS

0 R/W

•

SLAVE

ADDRESS

DEVICE

SELECT

BUS

CONTROL BYTE

ADDRESS BYTE 1

ADDRESS BYTE 0

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24C32A

DS21163E-page 6



2004 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

4.2

Page Write

Note:

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

DATA

A
C
K

S
T
O
P

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

DATA BYTE 0

A
C
K

S
T
O
P

DATA BYTE 31

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

2004 Microchip Technology Inc.

DS21163E-page 7

24C32A

5.0

ACKNOWLEDGE POLLING

FIGURE 5-1:

ACKNOWLEDGE POLLING
FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

6.0

READ OPERATION

6.1

Current Address Read

6.2

Random Read

FIGURE 6-1:

CURRENT ADDRESS READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL BYTE

DATA BYTE

S
T
O
P

A
C
K

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24C32A

DS21163E-page 8



2004 Microchip Technology Inc.

6.3

Contiguous Addressing Across
Multiple Devices

6.4

Sequential Read

FIGURE 6-2:

RANDOM READ

FIGURE 6-3:

SEQUENTIAL READ

0 0 0 0

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

S
T
O
P

A
C
K

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

CONTROL

BYTE

DATA

BYTE

A
C
K

S
T
A
R
T

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

A
C
K

DATA n

DATA n + 1

DATA n + 2

DATA n + x

S
T
O
P

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

2004 Microchip Technology Inc.

DS21163E-page 9

24C32A

7.0

PIN DESCRIPTIONS

7.1

A0, A1, A2 Chip Address Inputs

7.2

SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

(typical 10K

Ω

for 100 kHz, 2 K

Ω

for

400 kHz)

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.

7.3

SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

7.4

This pin must be connected to either V

or V

If tied to V

, normal memory operation is enabled

(read/write the entire memory 000-FFF).

If tied to V

, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

8.0

NOISE PROTECTION

9.0

POWER MANAGEMENT

monitor circuitry to prevent inadvertent writes

(data corruption) during low-voltage conditions. The
V

monitor circuitry is powered off when the device is

in standby mode in order to further reduce power con-
sumption.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21163E-html.html

24C32A

24C32A Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

Sales and Support

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Package:

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body, EIAJ standard)

SM = Plastic SOIC (207 mil Body, EIAJ standard)

Temperature

Blank =

C to +70

Range:

= -40

C to +85

E = -40

C to +125

Device:

24C32A

32K I

C Serial EEPROM (100 kHz, 400 kHz)

24C32AT

32K I

C Serial EEPROM (Tape and Reel)

24C32A

DS21163E-page 10



2004 Microchip Technology Inc.

Maker

Microchip Technology Inc.

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