21140F.book | Datasheet Lookup

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2004 Microchip Technology Inc.

DS21140F-page 1

24LC41

Features

• Single supply with operation down to 2.5V

• Completely implements DDC1



/DDC2



interface

for monitor identification

• Separate high speed 2-wire bus for

microcontroller access to 4K-bit Serial EEPROM

• Low-power CMOS technology

• 2 mA active current typical

• 20

A standby current typical at 5.5V

• Dual 2-wire serial interface bus

• Hardware write-protect for both ports

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 8 bytes (DDC port) or

16 bytes (4K Port)

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• 1,000,000 erase/write cycles ensured

• Data retention > 40 years

• 8-pin PDIP package

• Available for extended temperature ranges

Description

The Microchip Technology Inc. 24LC41 is a dual-port
128 x 8 and 512 x 8-bit Electrically Erasable PROM
(EEPROM). This device is designed for use in applica-
tions requiring storage and serial transmission of
configuration and control information. Three modes of
operation have been implemented:

• Transmit-only mode for the DDC Monitor Port

• Bidirectional mode for the DDC Monitor Port

• Bidirectional, industry-standard 2-wire bus for the

4K Microcontroller Access Port

Upon power-up, the DDC Monitor Port will be in the
Transmit-only mode, repeatedly sending a serial bit
stream of the entire memory array contents, clocked by
the VCLK/DWP pin. A valid high-to-low transition on
the DSCL pin will cause the device to enter the Bidirec-
tional mode, with byte-selectable read/write capability
of the memory array. The 4K-bit microcontroller port is
completely independent of the DDC port, therefore, it
can be accessed continuously by a microcontroller
without interrupting DDC transmission activity. The
24LC41 is available in a standard 8-pin PDIP package
in both commercial and industrial temperature ranges.

Package Type

Block Diagram

- Commercial (C):

0°C to

+70°C

- Industrial (I):

-40°C to

+85°C

24L

DSCL

VCLK/DWP

MSDA

DSDA

MWP

MSCL

PDIP

EDID Table

1K Bit

4K Bit

Serial

EEPROM

MSDA

MSCL

MWP

DSDA

VCLK/DWP

DSCL

r P

icr

ontr

lle

r A

cce

ss P

1K/4K 2.5V Dual Mode, Dual Port I

™

Serial EEPROM

Obsolete Device

C is a registered trademark of Philips Corporation.

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24LC41

DS21140F-page 2

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2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

......................................................................................................... -0.6V to V

+1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-65°C to +125°C

ESD protection on all pins

......................................................................................................................................................≥

4 kV

TABLE 1-1:

DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0°C to +70°C

Industrial (I):

= -40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

DSCL, DSDA, MSCL & MSDA pins:

High-level input voltage
Low-level input voltage

.7 V

—

.3 V

V
V

Input levels on VCLK/DWP pin:

High-level input voltage
Low-level input voltage

2.0

—

.2 V

V
V

≥

2.7V (Note)

< 2.7V (Note)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note)

Low-level output voltage

—

= 3 mA, V

= 2.5V (Note)

Low-level output voltage

—

= 6 mA, V

= 2.5V

Input leakage current

—

±1

= .1V to V

Output leakage current

—

±1

OUT

= .1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, DSCL or

MSCL = 400 kHz

Standby current

CCS

—
—

200

= 3.0V, DSDA or

MSDA = DSCL or MSCL = V

= 5.5V, DSDA or

MSDA = DSCL or MSCL = V

CLK

= V

Note:

This parameter is periodically sampled and not 100% tested.

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2004 Microchip Technology Inc.

DS21140F-page 3

24LC41

TABLE 1-2:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER
ACCESS PORTS)

DDC Monitor Port (Bidirectional Mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency
(DSCL and MSCL)

CLK

—

100

—

400

kHz

Clock high time
(DSCL and MSCL)

HIGH

4000

—

600

—

Clock low time
(DSCL and MSCL)

LOW

4700

—

1300

—

DSCL, DSDA, MSCL and
MSDA rise time

—

1000

—

300

(Note 1)

DSCL, DSDA, MSCL and
MSDA fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first
clock pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

min to V

max

—

250

20 + .1

250

(Note 1), C

≤

100 pF

Input filter spike
suppression (DSCL, DSDA,
MSCL and MSDA pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

DDC Monitor Port Transmit-Only Mode Parameters

Output valid from VCLK/
DWP

VAA

—

2000

—

1000

VCLK/DWP high time

VHIGH

4000

—

600

—

VCLK/DWP low time

VLOW

4700

—

1300

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up
time

VPU

—

Endurance

—

cycles

25°C, Vcc = 5.0V, Block
mode (Note 4)

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of Start or Stop
conditions.

The combined T

and V

HYS

specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ model which can be obtained from our web site.

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24LC41

DS21140F-page 4

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2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

DDC Monitor Port

The DDC Monitor Port operates in two modes, the
Transmit-only mode and the Bidirectional mode. There
is a separate 2-wire protocol to support each mode,
each having a separate clock input and sharing a
common data line (DSDA). The device enters the
Transmit-only mode upon power-up. In this mode, the
device transmits data bits on the DSDA pin in response
to a clock signal on the VCLK/DWP pin. The device will
remain in this mode until a valid high-to-low transition is
placed on the DSCL input. When a valid transition on
DSCL is recognized, the device will switch into the
Bidirectional mode. The only way to switch the device
back to the Transmit-only mode is to remove power
from the device.

2.2

Transmit-Only Mode

The device will power-up in the Transmit-only mode.
This mode supports a unidirectional 2-wire protocol for
transmission of the contents of the memory array. This
device requires that it be initialized prior to valid data
being sent in the Transmit-only mode (Section 2.3

“Initialization Procedure”). In this mode, data is
transmitted on the DSDA pin in 8-bit bytes, each
followed by a ninth, null bit (Figure 2-1). The clock
source for the Transmit-only mode is provided on the
VCLK/DWP pin, and a data bit is output on the rising
edge on this pin. The eight bits in each byte are trans-
mitted by Most Significant bit first. Each byte within the
memory array will be output in sequence. When the last
byte in the memory array is transmitted, the output will
wrap around to the first location and continue. The
Bidirectional mode Clock (DSCL) pin must be held high
for the device to remain in the Transmit-only mode.

2.3

Initialization Procedure

After V

has stabilized, the device will be in the

Transmit-only mode. Nine clock cycles on the VCLK/
DWP pin must be given to the device for it to perform
internal sychronization. During this period, the DSDA
pin will be in a high-impedance state. On the rising
edge of the tenth clock cycle, the device will output the
first valid data bit which will be the Most Significant bit
of a byte. The device will power-up at an indeterminate
byte address (Figure 2-2).

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

DSCL

DSDA

VCLK/DWP

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

VCLK/DWP

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2004 Microchip Technology Inc.

DS21140F-page 5

24LC41

2.3.1

BIDIRECTIONAL MODE

The DDC Monitor Port can be switched into the
Bidirectional mode (Figure 2-3) by applying a valid
high-to-low transition on the Bidirectional mode Clock
(DSCL). When the device has been switched into the
Bidirectional mode, the VCLK/DWP input is disre-
garded, with the exception that a logic high level is
required to enable write capability. This mode supports
a 2-wire bidirectional data transmission protocol. In this
protocol, a device that sends data on the bus is defined
to be the transmitter, and a device that receives data
from the bus is defined to be the receiver. The bus must
be controlled by a master device that generates the
Bidirectional mode Clock (DSCL), controls access to
the bus and generates the Start and Stop conditions,
while the DDC Monitor Port acts as the slave. Both
master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.

2.4

Microcontroller Access Port

The Microcontroller Access Port supports a bidirec-
tional 2-wire bus and data transmission protocol. A
device that sends data onto the bus is defined as
transmitter, and a device receiving data as receiver.
The bus has to be controlled by a master device which
generates the serial clock (MSCL), controls the bus
access, and generates the Start and Stop conditions,
while the Microcontroller Access Port works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.

FIGURE 2-3:

MODE TRANSITION

DSCL

DSDA

VCLK/DWP

Bidirectional Mode

VHZ

Transmit-only Mode

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24LC41

DS21140F-page 6

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2004 Microchip Technology Inc.

3.0

BIDIRECTIONAL BUS
CHARACTERISTICS

Characteristics for the bidirectional bus are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port The following bus
protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Start condition. All commands must be preceded by a
Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Stop condition. All operations must be ended with a
Stop condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first in first
out fashion.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the
DSDA or MSDA line during the Acknowledge clock
pulse in such a way that the DSDA or MSDA line is
stable low during the high period of the acknowledge
related clock pulse. Of course, setup and hold times
must be taken into account. A master must signal an
end of data to the slave by not generating an Acknowl-
edge bit on the last byte that has been clocked out of
the slave. In this case, the slave must leave the data
line high to enable the master to generate the Stop
condition.

3.6

Device Addressing

A control byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit control code. This
control code is set as 1010 for both read and write oper-
ations and is the same for both the DDC Monitor Port
and Microcontroller Access Port. The next three bits of
the control byte are block select bits (B1, B2 and B0).
All three of these bits are don’t care bits for the DDC
Monitor Port. The B2 and B1 bits are don’t care bits for
the Microcontroller Access Port, and the B0 bit is used
by the Microcontroller Access Port to select which of
the two 256 word blocks of memory are to be accessed
(Figure 3-4). The B0 bit is effectively the Most Signifi-
cant bit of the word address. The last bit of the control
byte defines the operation to be performed. When set
to one, a read operation is selected; when set to zero,
a write operation is selected. Following the Start condi-
tion, the device monitors the DSDA or MSDA bus
checking the device type identifier being transmitted,
upon a 1010 code the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the device will select a read or a
write operation. The DDC Monitor Port and Microcon-
troller Access Port can be accessed simultaneously
because they are completely independent of one
another.

Note:

The microcontroller access port and the
DDC Monitor Port (in Bidirectional mode)
will not generate any Acknowledge bits if
an internal programming cycle is in
progress.

Operation

Control Code

Chip Select

R/W

Read

1010

XXB0

Write

1010

XXB0

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2004 Microchip Technology Inc.

DS21140F-page 7

24LC41

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(

)

(B)

(D)

(C)

(

)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

MSCL

MSDA

MSCL

DSDA

STA

Start

Stop

HYS

STO

MSCL

MSDA

DSCL

DSDA

STA

HIGH

STO

DAT

BUF

STA

LOW

MSCL

MSDA

OUT

X = Don’t care. B0 is don’t care for DDC Monitor Port, but is used by the Microcontroller Access Port to select which of the two 256
word blocks of memory are to be accessed.

R/W

READ/WRITE

Start

SLAVE ADDRESS

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24LC41

DS21140F-page 8

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2004 Microchip Technology Inc.

4.0

WRITE OPERATION

Write operations are identical for the DDC Monitor Port
(when in Bidirectional mode) and the Microcontroller
Access Port, with the exception of the VCLK/DWP and
MWP pins noted in the next sections. Data can be
written using either a Byte Write or Page Write
command. Write commands for the DDC Monitor Port
and the Microcontroller Access Port are completely
independent of one another.

4.1

Byte Write

Following the Start signal from the master, the slave
address (4-bits), the Chip Select bits (3-bits) and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be
written into the address pointer of the port. After
receiving another Acknowledge signal from the port,
the master device will transmit the data word to be
written into the addressed memory location. The port
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle, and
during this time, the port will not generate Acknowledge
signals (Figure 4-1).

For the DDC Monitor Port it is required that VCLK/DWP
be held at a logic high level in order to program the
device. This applies to byte write and page write
operation. Note that VCLK/DWP can go low while the
device is in its self-timed program operation and not
affect programming.

For the Microcontroller Access Port, the MWP pin must
be held to V

during the entire write operation.

4.2

Page Write

The write control byte, word address, and the first data
byte are transmitted to the port in the same way as in a
byte write. But, instead of generating a Stop condition,
the master transmits up to eight data bytes to the DDC
Monitor Port or 16 bytes to the Microcontroller Access
Port, which are temporarily stored in the on-chip page
buffer and will be written into the memory after the
master has transmitted a Stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order 5-bits of the word address remains
constant. If the master should transmit more than eight
words to the DDC Monitor Port or 16 words to the
Microcontroller Access Port prior to generating the Stop
condition, the address counter will roll over and the
previously received data will be overwritten. As with the
byte write operation, once the Stop condition is
received an internal write cycle will begin (Figure 4-2).

For the DDC Monitor Port, it is required thatVCLK/
DWP be held at a logic high level in order to program
the device. This applies to byte write and page write
operation. Note that VCLK/DWP can go low while the
device is in its self-timed program operation and not
affect programming.

For the Microcontroller Access Port, the MWP pin must
be held to V

during the entire write operation..

Note:

Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multi-
ples of the page buffer size (or ‘page size’)
and end at addresses that are integer
multiples of [page size - 1]. If a Page Write
command attempts to write across a
physical page boundary, the result is that
the data wraps around to the beginning of
the current page (overwriting data
previously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.

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2004 Microchip Technology Inc.

DS21140F-page 9

24LC41

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

S
T
A
R
T

S
T
O
P

Bus Activity
Master

SDA or

Bus Activity

A
C
K

Control

Byte

Word

Address

Data

MSDA Line

VCLK

SDA LINE

S
T
A
R
T

Control

Byte

Word

Address

Data n

Data n + 15

S
T
O
P

A
C
K

Data n + 1

VCLK/DWP

Bus Activity
Master

Bus Activity

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DS21140F-page 10

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2004 Microchip Technology Inc.

5.0

ACKNOWLEDGE POLLING

Acknowledge polling can be done for both the DDC
Monitor Port (when in Bidirectional mode) and the
Microcontroller Access Port.

Since the port will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize but
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W =

). If the device is still

busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
read or write command. See Figure 5-1 for the flow
diagram.

FIGURE 5-1:

ACKNOWLEDGE
POLLING FLOW

6.0

WRITE PROTECTION

6.1

DDC Monitor Port

When using the DDC Monitor Port in the Bidirectional
mode, the VCLK/DWP pin operates as the write-protect
control pin. Setting VCLK/DWP high allows normal
write operations, while setting VCLK/DWP low
prevents writing to any location in the array. Connecting
the VCLK/DWP pin to V

would allow the DDC Moni-

tor Port to operate as a serial ROM, although this
configuration would prevent using the device in the
Transmit-only mode.

6.2

Microcontroller Access Port

The Microcontroller Access Port can be used as a
serial ROM when the MWP pin is connected to V

Programming will be inhibited and the entire memory
associated with the Microcontroller Access Port will be
write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W =

Did Device

Acknowledge

(ACK =

Operation

YES

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2004 Microchip Technology Inc.

DS21140F-page 1

24LC41

Features

• Single supply with operation down to 2.5V

• Completely implements DDC1



/DDC2



interface

for monitor identification

• Separate high speed 2-wire bus for

microcontroller access to 4K-bit Serial EEPROM

• Low-power CMOS technology

• 2 mA active current typical

• 20

A standby current typical at 5.5V

• Dual 2-wire serial interface bus

• Hardware write-protect for both ports

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 8 bytes (DDC port) or

16 bytes (4K Port)

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• 1,000,000 erase/write cycles ensured

• Data retention > 40 years

• 8-pin PDIP package

• Available for extended temperature ranges

Description

• Transmit-only mode for the DDC Monitor Port

• Bidirectional mode for the DDC Monitor Port

• Bidirectional, industry-standard 2-wire bus for the

4K Microcontroller Access Port

Package Type

Block Diagram

- Commercial (C):

0°C to

+70°C

- Industrial (I):

-40°C to

+85°C

24L

DSCL

VCLK/DWP

MSDA

DSDA

MWP

MSCL

PDIP

EDID Table

1K Bit

4K Bit

Serial

EEPROM

MSDA

MSCL

MWP

DSDA

VCLK/DWP

DSCL

r P

icr

ontr

lle

r A

cce

ss P

1K/4K 2.5V Dual Mode, Dual Port I

™

Serial EEPROM

Obsolete Device

C is a registered trademark of Philips Corporation.

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2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

......................................................................................................... -0.6V to V

+1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-65°C to +125°C

ESD protection on all pins

......................................................................................................................................................≥

4 kV

TABLE 1-1:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0°C to +70°C

Industrial (I):

= -40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

DSCL, DSDA, MSCL & MSDA pins:

High-level input voltage
Low-level input voltage

.7 V

—

.3 V

V
V

Input levels on VCLK/DWP pin:

High-level input voltage
Low-level input voltage

2.0

—

.2 V

V
V

≥

2.7V (Note)

< 2.7V (Note)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note)

Low-level output voltage

—

= 3 mA, V

= 2.5V (Note)

Low-level output voltage

—

= 6 mA, V

= 2.5V

Input leakage current

—

±1

= .1V to V

Output leakage current

—

±1

OUT

= .1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, DSCL or

MSCL = 400 kHz

Standby current

CCS

—
—

200

= 3.0V, DSDA or

MSDA = DSCL or MSCL = V

= 5.5V, DSDA or

MSDA = DSCL or MSCL = V

CLK

= V

Note:

This parameter is periodically sampled and not 100% tested.

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2004 Microchip Technology Inc.

DS21140F-page 3

24LC41

TABLE 1-2:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER
ACCESS PORTS)

DDC Monitor Port (Bidirectional Mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency
(DSCL and MSCL)

CLK

—

100

—

400

kHz

Clock high time
(DSCL and MSCL)

HIGH

4000

—

600

—

Clock low time
(DSCL and MSCL)

LOW

4700

—

1300

—

DSCL, DSDA, MSCL and
MSDA rise time

—

1000

—

300

(Note 1)

DSCL, DSDA, MSCL and
MSDA fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first
clock pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

min to V

max

—

250

20 + .1

250

(Note 1), C

≤

100 pF

Input filter spike
suppression (DSCL, DSDA,
MSCL and MSDA pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

DDC Monitor Port Transmit-Only Mode Parameters

Output valid from VCLK/
DWP

VAA

—

2000

—

1000

VCLK/DWP high time

VHIGH

4000

—

600

—

VCLK/DWP low time

VLOW

4700

—

1300

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up
time

VPU

—

Endurance

—

cycles

25°C, Vcc = 5.0V, Block
mode (Note 4)

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

The combined T

and V

HYS

specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ model which can be obtained from our web site.

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24LC41

DS21140F-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

DDC Monitor Port

2.2

Transmit-Only Mode

2.3

Initialization Procedure

After V

has stabilized, the device will be in the

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

DSCL

DSDA

VCLK/DWP

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

VCLK/DWP

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2004 Microchip Technology Inc.

DS21140F-page 5

24LC41

2.3.1

BIDIRECTIONAL MODE

2.4

Microcontroller Access Port

FIGURE 2-3:

MODE TRANSITION

DSCL

DSDA

VCLK/DWP

Bidirectional Mode

VHZ

Transmit-only Mode

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24LC41

DS21140F-page 6



2004 Microchip Technology Inc.

3.0

BIDIRECTIONAL BUS
CHARACTERISTICS

Characteristics for the bidirectional bus are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port The following bus
protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Start condition. All commands must be preceded by a
Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Stop condition. All operations must be ended with a
Stop condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

3.6

Device Addressing

Note:

The microcontroller access port and the
DDC Monitor Port (in Bidirectional mode)
will not generate any Acknowledge bits if
an internal programming cycle is in
progress.

Operation

Control Code

Chip Select

R/W

Read

1010

XXB0

Write

1010

XXB0

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2004 Microchip Technology Inc.

DS21140F-page 7

24LC41

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(

)

(B)

(D)

(C)

(

)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

MSCL

MSDA

MSCL

DSDA

STA

Start

Stop

HYS

STO

MSCL

MSDA

DSCL

DSDA

STA

HIGH

STO

DAT

BUF

STA

LOW

MSCL

MSDA

OUT

X = Don’t care. B0 is don’t care for DDC Monitor Port, but is used by the Microcontroller Access Port to select which of the two 256
word blocks of memory are to be accessed.

R/W

READ/WRITE

Start

SLAVE ADDRESS

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24LC41

DS21140F-page 8



2004 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

For the Microcontroller Access Port, the MWP pin must
be held to V

during the entire write operation.

4.2

Page Write

For the Microcontroller Access Port, the MWP pin must
be held to V

during the entire write operation..

Note:

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

2004 Microchip Technology Inc.

DS21140F-page 9

24LC41

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

S
T
A
R
T

S
T
O
P

Bus Activity
Master

SDA or

Bus Activity

A
C
K

Control

Byte

Word

Address

Data

MSDA Line

VCLK

SDA LINE

S
T
A
R
T

Control

Byte

Word

Address

Data n

Data n + 15

S
T
O
P

A
C
K

Data n + 1

VCLK/DWP

Bus Activity
Master

Bus Activity

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24LC41

DS21140F-page 10



2004 Microchip Technology Inc.

5.0

ACKNOWLEDGE POLLING

Acknowledge polling can be done for both the DDC
Monitor Port (when in Bidirectional mode) and the
Microcontroller Access Port.

). If the device is still

FIGURE 5-1:

ACKNOWLEDGE
POLLING FLOW

6.0

WRITE PROTECTION

6.1

DDC Monitor Port

would allow the DDC Moni-

tor Port to operate as a serial ROM, although this
configuration would prevent using the device in the
Transmit-only mode.

6.2

Microcontroller Access Port

The Microcontroller Access Port can be used as a
serial ROM when the MWP pin is connected to V

Programming will be inhibited and the entire memory
associated with the Microcontroller Access Port will be
write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W =

Did Device

Acknowledge

(ACK =

Operation

YES

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

2004 Microchip Technology Inc.

DS21140F-page 1

24LC41

Features

• Single supply with operation down to 2.5V

• Completely implements DDC1



/DDC2



interface

for monitor identification

• Separate high speed 2-wire bus for

microcontroller access to 4K-bit Serial EEPROM

• Low-power CMOS technology

• 2 mA active current typical

• 20

A standby current typical at 5.5V

• Dual 2-wire serial interface bus

• Hardware write-protect for both ports

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 8 bytes (DDC port) or

16 bytes (4K Port)

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• 1,000,000 erase/write cycles ensured

• Data retention > 40 years

• 8-pin PDIP package

• Available for extended temperature ranges

Description

• Transmit-only mode for the DDC Monitor Port

• Bidirectional mode for the DDC Monitor Port

• Bidirectional, industry-standard 2-wire bus for the

4K Microcontroller Access Port

Package Type

Block Diagram

- Commercial (C):

0°C to

+70°C

- Industrial (I):

-40°C to

+85°C

24L

DSCL

VCLK/DWP

MSDA

DSDA

MWP

MSCL

PDIP

EDID Table

1K Bit

4K Bit

Serial

EEPROM

MSDA

MSCL

MWP

DSDA

VCLK/DWP

DSCL

r P

icr

ontr

lle

r A

cce

ss P

1K/4K 2.5V Dual Mode, Dual Port I

™

Serial EEPROM

Obsolete Device

C is a registered trademark of Philips Corporation.

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24LC41

DS21140F-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

......................................................................................................... -0.6V to V

+1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-65°C to +125°C

ESD protection on all pins

......................................................................................................................................................≥

4 kV

TABLE 1-1:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0°C to +70°C

Industrial (I):

= -40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

DSCL, DSDA, MSCL & MSDA pins:

High-level input voltage
Low-level input voltage

.7 V

—

.3 V

V
V

Input levels on VCLK/DWP pin:

High-level input voltage
Low-level input voltage

2.0

—

.2 V

V
V

≥

2.7V (Note)

< 2.7V (Note)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note)

Low-level output voltage

—

= 3 mA, V

= 2.5V (Note)

Low-level output voltage

—

= 6 mA, V

= 2.5V

Input leakage current

—

±1

= .1V to V

Output leakage current

—

±1

OUT

= .1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, DSCL or

MSCL = 400 kHz

Standby current

CCS

—
—

200

= 3.0V, DSDA or

MSDA = DSCL or MSCL = V

= 5.5V, DSDA or

MSDA = DSCL or MSCL = V

CLK

= V

Note:

This parameter is periodically sampled and not 100% tested.

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2004 Microchip Technology Inc.

DS21140F-page 3

24LC41

TABLE 1-2:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER
ACCESS PORTS)

DDC Monitor Port (Bidirectional Mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency
(DSCL and MSCL)

CLK

—

100

—

400

kHz

Clock high time
(DSCL and MSCL)

HIGH

4000

—

600

—

Clock low time
(DSCL and MSCL)

LOW

4700

—

1300

—

DSCL, DSDA, MSCL and
MSDA rise time

—

1000

—

300

(Note 1)

DSCL, DSDA, MSCL and
MSDA fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first
clock pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

min to V

max

—

250

20 + .1

250

(Note 1), C

≤

100 pF

Input filter spike
suppression (DSCL, DSDA,
MSCL and MSDA pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

DDC Monitor Port Transmit-Only Mode Parameters

Output valid from VCLK/
DWP

VAA

—

2000

—

1000

VCLK/DWP high time

VHIGH

4000

—

600

—

VCLK/DWP low time

VLOW

4700

—

1300

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up
time

VPU

—

Endurance

—

cycles

25°C, Vcc = 5.0V, Block
mode (Note 4)

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

The combined T

and V

HYS

specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ model which can be obtained from our web site.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21140F-html.html

24LC41

DS21140F-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

DDC Monitor Port

2.2

Transmit-Only Mode

2.3

Initialization Procedure

After V

has stabilized, the device will be in the

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

DSCL

DSDA

VCLK/DWP

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

VCLK/DWP

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2004 Microchip Technology Inc.

DS21140F-page 5

24LC41

2.3.1

BIDIRECTIONAL MODE

2.4

Microcontroller Access Port

FIGURE 2-3:

MODE TRANSITION

DSCL

DSDA

VCLK/DWP

Bidirectional Mode

VHZ

Transmit-only Mode

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24LC41

DS21140F-page 6



2004 Microchip Technology Inc.

3.0

BIDIRECTIONAL BUS
CHARACTERISTICS

Characteristics for the bidirectional bus are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port The following bus
protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Start condition. All commands must be preceded by a
Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Stop condition. All operations must be ended with a
Stop condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

3.6

Device Addressing

Note:

The microcontroller access port and the
DDC Monitor Port (in Bidirectional mode)
will not generate any Acknowledge bits if
an internal programming cycle is in
progress.

Operation

Control Code

Chip Select

R/W

Read

1010

XXB0

Write

1010

XXB0

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

2004 Microchip Technology Inc.

DS21140F-page 7

24LC41

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(

)

(B)

(D)

(C)

(

)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

MSCL

MSDA

MSCL

DSDA

STA

Start

Stop

HYS

STO

MSCL

MSDA

DSCL

DSDA

STA

HIGH

STO

DAT

BUF

STA

LOW

MSCL

MSDA

OUT

X = Don’t care. B0 is don’t care for DDC Monitor Port, but is used by the Microcontroller Access Port to select which of the two 256
word blocks of memory are to be accessed.

R/W

READ/WRITE

Start

SLAVE ADDRESS

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24LC41

DS21140F-page 8



2004 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

For the Microcontroller Access Port, the MWP pin must
be held to V

during the entire write operation.

4.2

Page Write

For the Microcontroller Access Port, the MWP pin must
be held to V

during the entire write operation..

Note:

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

2004 Microchip Technology Inc.

DS21140F-page 9

24LC41

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

S
T
A
R
T

S
T
O
P

Bus Activity
Master

SDA or

Bus Activity

A
C
K

Control

Byte

Word

Address

Data

MSDA Line

VCLK

SDA LINE

S
T
A
R
T

Control

Byte

Word

Address

Data n

Data n + 15

S
T
O
P

A
C
K

Data n + 1

VCLK/DWP

Bus Activity
Master

Bus Activity

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24LC41

DS21140F-page 10



2004 Microchip Technology Inc.

5.0

ACKNOWLEDGE POLLING

Acknowledge polling can be done for both the DDC
Monitor Port (when in Bidirectional mode) and the
Microcontroller Access Port.

). If the device is still

FIGURE 5-1:

ACKNOWLEDGE
POLLING FLOW

6.0

WRITE PROTECTION

6.1

DDC Monitor Port

would allow the DDC Moni-

tor Port to operate as a serial ROM, although this
configuration would prevent using the device in the
Transmit-only mode.

6.2

Microcontroller Access Port

The Microcontroller Access Port can be used as a
serial ROM when the MWP pin is connected to V

Programming will be inhibited and the entire memory
associated with the Microcontroller Access Port will be
write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W =

Did Device

Acknowledge

(ACK =

Operation

YES

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

2004 Microchip Technology Inc.

DS21140F-page 1

24LC41

Features

• Single supply with operation down to 2.5V

• Completely implements DDC1



/DDC2



interface

for monitor identification

• Separate high speed 2-wire bus for

microcontroller access to 4K-bit Serial EEPROM

• Low-power CMOS technology

• 2 mA active current typical

• 20

A standby current typical at 5.5V

• Dual 2-wire serial interface bus

• Hardware write-protect for both ports

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 8 bytes (DDC port) or

16 bytes (4K Port)

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• 1,000,000 erase/write cycles ensured

• Data retention > 40 years

• 8-pin PDIP package

• Available for extended temperature ranges

Description

• Transmit-only mode for the DDC Monitor Port

• Bidirectional mode for the DDC Monitor Port

• Bidirectional, industry-standard 2-wire bus for the

4K Microcontroller Access Port

Package Type

Block Diagram

- Commercial (C):

0°C to

+70°C

- Industrial (I):

-40°C to

+85°C

24L

DSCL

VCLK/DWP

MSDA

DSDA

MWP

MSCL

PDIP

EDID Table

1K Bit

4K Bit

Serial

EEPROM

MSDA

MSCL

MWP

DSDA

VCLK/DWP

DSCL

r P

icr

ontr

lle

r A

cce

ss P

1K/4K 2.5V Dual Mode, Dual Port I

™

Serial EEPROM

Obsolete Device

C is a registered trademark of Philips Corporation.

/var/www/html/datasheet/sites/default/files/pdfhtml_dummy/21140F-html.html

24LC41

DS21140F-page 2



2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

......................................................................................................... -0.6V to V

+1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-65°C to +125°C

ESD protection on all pins

......................................................................................................................................................≥

4 kV

TABLE 1-1:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0°C to +70°C

Industrial (I):

= -40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

DSCL, DSDA, MSCL & MSDA pins:

High-level input voltage
Low-level input voltage

.7 V

—

.3 V

V
V

Input levels on VCLK/DWP pin:

High-level input voltage
Low-level input voltage

2.0

—

.2 V

V
V

≥

2.7V (Note)

< 2.7V (Note)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note)

Low-level output voltage

—

= 3 mA, V

= 2.5V (Note)

Low-level output voltage

—

= 6 mA, V

= 2.5V

Input leakage current

—

±1

= .1V to V

Output leakage current

—

±1

OUT

= .1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, DSCL or

MSCL = 400 kHz

Standby current

CCS

—
—

200

= 3.0V, DSDA or

MSDA = DSCL or MSCL = V

= 5.5V, DSDA or

MSDA = DSCL or MSCL = V

CLK

= V

Note:

This parameter is periodically sampled and not 100% tested.

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2004 Microchip Technology Inc.

DS21140F-page 3

24LC41

TABLE 1-2:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER
ACCESS PORTS)

DDC Monitor Port (Bidirectional Mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency
(DSCL and MSCL)

CLK

—

100

—

400

kHz

Clock high time
(DSCL and MSCL)

HIGH

4000

—

600

—

Clock low time
(DSCL and MSCL)

LOW

4700

—

1300

—

DSCL, DSDA, MSCL and
MSDA rise time

—

1000

—

300

(Note 1)

DSCL, DSDA, MSCL and
MSDA fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first
clock pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

min to V

max

—

250

20 + .1

250

(Note 1), C

≤

100 pF

Input filter spike
suppression (DSCL, DSDA,
MSCL and MSDA pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

DDC Monitor Port Transmit-Only Mode Parameters

Output valid from VCLK/
DWP

VAA

—

2000

—

1000

VCLK/DWP high time

VHIGH

4000

—

600

—

VCLK/DWP low time

VLOW

4700

—

1300

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up
time

VPU

—

Endurance

—

cycles

25°C, Vcc = 5.0V, Block
mode (Note 4)

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

The combined T

and V

HYS

specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ model which can be obtained from our web site.

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DS21140F-page 4

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2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

DDC Monitor Port

2.2

Transmit-Only Mode

2.3

Initialization Procedure

After V

has stabilized, the device will be in the

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

DSCL

DSDA

VCLK/DWP

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

VCLK/DWP

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2004 Microchip Technology Inc.

DS21140F-page 5

24LC41

2.3.1

BIDIRECTIONAL MODE

2.4

Microcontroller Access Port

FIGURE 2-3:

MODE TRANSITION

DSCL

DSDA

VCLK/DWP

Bidirectional Mode

VHZ

Transmit-only Mode

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DS21140F-page 6

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2004 Microchip Technology Inc.

3.0

BIDIRECTIONAL BUS
CHARACTERISTICS

Characteristics for the bidirectional bus are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port The following bus
protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Start condition. All commands must be preceded by a
Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Stop condition. All operations must be ended with a
Stop condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

3.6

Device Addressing

Note:

The microcontroller access port and the
DDC Monitor Port (in Bidirectional mode)
will not generate any Acknowledge bits if
an internal programming cycle is in
progress.

Operation

Control Code

Chip Select

R/W

Read

1010

XXB0

Write

1010

XXB0

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2004 Microchip Technology Inc.

DS21140F-page 7

24LC41

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(

)

(B)

(D)

(C)

(

)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

MSCL

MSDA

MSCL

DSDA

STA

Start

Stop

HYS

STO

MSCL

MSDA

DSCL

DSDA

STA

HIGH

STO

DAT

BUF

STA

LOW

MSCL

MSDA

OUT

X = Don’t care. B0 is don’t care for DDC Monitor Port, but is used by the Microcontroller Access Port to select which of the two 256
word blocks of memory are to be accessed.

R/W

READ/WRITE

Start

SLAVE ADDRESS

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DS21140F-page 8

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2004 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

For the Microcontroller Access Port, the MWP pin must
be held to V

during the entire write operation.

4.2

Page Write

For the Microcontroller Access Port, the MWP pin must
be held to V

during the entire write operation..

Note:

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2004 Microchip Technology Inc.

DS21140F-page 9

24LC41

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

S
T
A
R
T

S
T
O
P

Bus Activity
Master

SDA or

Bus Activity

A
C
K

Control

Byte

Word

Address

Data

MSDA Line

VCLK

SDA LINE

S
T
A
R
T

Control

Byte

Word

Address

Data n

Data n + 15

S
T
O
P

A
C
K

Data n + 1

VCLK/DWP

Bus Activity
Master

Bus Activity

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DS21140F-page 10

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2004 Microchip Technology Inc.

5.0

ACKNOWLEDGE POLLING

Acknowledge polling can be done for both the DDC
Monitor Port (when in Bidirectional mode) and the
Microcontroller Access Port.

). If the device is still

FIGURE 5-1:

ACKNOWLEDGE
POLLING FLOW

6.0

WRITE PROTECTION

6.1

DDC Monitor Port

would allow the DDC Moni-

tor Port to operate as a serial ROM, although this
configuration would prevent using the device in the
Transmit-only mode.

6.2

Microcontroller Access Port

The Microcontroller Access Port can be used as a
serial ROM when the MWP pin is connected to V

Programming will be inhibited and the entire memory
associated with the Microcontroller Access Port will be
write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W =

Did Device

Acknowledge

(ACK =

Operation

YES

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2004 Microchip Technology Inc.

DS21140F-page 1

24LC41

Features

• Single supply with operation down to 2.5V

• Completely implements DDC1



/DDC2



interface

for monitor identification

• Separate high speed 2-wire bus for

microcontroller access to 4K-bit Serial EEPROM

• Low-power CMOS technology

• 2 mA active current typical

• 20

A standby current typical at 5.5V

• Dual 2-wire serial interface bus

• Hardware write-protect for both ports

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 8 bytes (DDC port) or

16 bytes (4K Port)

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• 1,000,000 erase/write cycles ensured

• Data retention > 40 years

• 8-pin PDIP package

• Available for extended temperature ranges

Description

• Transmit-only mode for the DDC Monitor Port

• Bidirectional mode for the DDC Monitor Port

• Bidirectional, industry-standard 2-wire bus for the

4K Microcontroller Access Port

Package Type

Block Diagram

- Commercial (C):

0°C to

+70°C

- Industrial (I):

-40°C to

+85°C

24L

DSCL

VCLK/DWP

MSDA

DSDA

MWP

MSCL

PDIP

EDID Table

1K Bit

4K Bit

Serial

EEPROM

MSDA

MSCL

MWP

DSDA

VCLK/DWP

DSCL

r P

icr

ontr

lle

r A

cce

ss P

1K/4K 2.5V Dual Mode, Dual Port I

™

Serial EEPROM

Obsolete Device

C is a registered trademark of Philips Corporation.

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DS21140F-page 2

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2004 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Absolute Maximum Ratings

(†)

.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

......................................................................................................... -0.6V to V

+1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-65°C to +125°C

ESD protection on all pins

......................................................................................................................................................≥

4 kV

TABLE 1-1:

DC CHARACTERISTICS

= +2.5V to 5.5V

Commercial (C): T

= 0°C to +70°C

Industrial (I):

= -40°C to +85°C

Parameter

Symbol

Min

Max

Units

Conditions

DSCL, DSDA, MSCL & MSDA pins:

High-level input voltage
Low-level input voltage

.7 V

—

.3 V

V
V

Input levels on VCLK/DWP pin:

High-level input voltage
Low-level input voltage

2.0

—

.2 V

V
V

≥

2.7V (Note)

< 2.7V (Note)

Hysteresis of Schmitt Trigger inputs

HYS

.05 V

—

(Note)

Low-level output voltage

—

= 3 mA, V

= 2.5V (Note)

Low-level output voltage

—

= 6 mA, V

= 2.5V

Input leakage current

—

±1

= .1V to V

Output leakage current

—

±1

OUT

= .1V to V

Pin capacitance (all inputs/outputs)

, C

OUT

—

= 5.0V (Note),

= 25

C, F

CLK

= 1 MHz

Operating current

Write

Read

—
—

3
1

mA
mA

= 5.5V, DSCL or

MSCL = 400 kHz

Standby current

CCS

—
—

200

= 3.0V, DSDA or

MSDA = DSCL or MSCL = V

= 5.5V, DSDA or

MSDA = DSCL or MSCL = V

CLK

= V

Note:

This parameter is periodically sampled and not 100% tested.

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2004 Microchip Technology Inc.

DS21140F-page 3

24LC41

TABLE 1-2:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER
ACCESS PORTS)

DDC Monitor Port (Bidirectional Mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency
(DSCL and MSCL)

CLK

—

100

—

400

kHz

Clock high time
(DSCL and MSCL)

HIGH

4000

—

600

—

Clock low time
(DSCL and MSCL)

LOW

4700

—

1300

—

DSCL, DSDA, MSCL and
MSDA rise time

—

1000

—

300

(Note 1)

DSCL, DSDA, MSCL and
MSDA fall time

—

300

—

300

(Note 1)

Start condition hold time

STA

4000

—

600

—

After this period the first
clock pulse is generated

Start condition setup time

STA

4700

—

600

—

Only relevant for repeated
Start condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

Stop condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free
before a new transmission
can start

Output fall time from V

min to V

max

—

250

20 + .1

250

(Note 1), C

≤

100 pF

Input filter spike
suppression (DSCL, DSDA,
MSCL and MSDA pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

DDC Monitor Port Transmit-Only Mode Parameters

Output valid from VCLK/
DWP

VAA

—

2000

—

1000

VCLK/DWP high time

VHIGH

4000

—

600

—

VCLK/DWP low time

VLOW

4700

—

1300

—

Mode transition time

VHZ

—

500

—

500

Transmit-only power-up
time

VPU

—

Endurance

—

cycles

25°C, Vcc = 5.0V, Block
mode (Note 4)

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

The combined T

and V

HYS

specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ model which can be obtained from our web site.

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24LC41

DS21140F-page 4



2004 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

DDC Monitor Port

2.2

Transmit-Only Mode

2.3

Initialization Procedure

After V

has stabilized, the device will be in the

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

DSCL

DSDA

VCLK/DWP

VAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

VLOW

VHIGH

VAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

VPU

SCL

SDA

VCLK/DWP

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2004 Microchip Technology Inc.

DS21140F-page 5

24LC41

2.3.1

BIDIRECTIONAL MODE

2.4

Microcontroller Access Port

FIGURE 2-3:

MODE TRANSITION

DSCL

DSDA

VCLK/DWP

Bidirectional Mode

VHZ

Transmit-only Mode

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DS21140F-page 6



2004 Microchip Technology Inc.

3.0

BIDIRECTIONAL BUS
CHARACTERISTICS

Characteristics for the bidirectional bus are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port The following bus
protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Start condition. All commands must be preceded by a
Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Stop condition. All operations must be ended with a
Stop condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

3.5

Acknowledge

3.6

Device Addressing

Note:

The microcontroller access port and the
DDC Monitor Port (in Bidirectional mode)
will not generate any Acknowledge bits if
an internal programming cycle is in
progress.

Operation

Control Code

Chip Select

R/W

Read

1010

XXB0

Write

1010

XXB0

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2004 Microchip Technology Inc.

DS21140F-page 7

24LC41

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 3-2:

BUS TIMING START/STOP

FIGURE 3-3:

BUS TIMING DATA

FIGURE 3-4:

CONTROL BYTE ALLOCATION

DSCL

DSDA

(

)

(B)

(D)

(C)

(

)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

MSCL

MSDA

MSCL

DSDA

STA

Start

Stop

HYS

STO

MSCL

MSDA

DSCL

DSDA

STA

HIGH

STO

DAT

BUF

STA

LOW

MSCL

MSDA

OUT

X = Don’t care. B0 is don’t care for DDC Monitor Port, but is used by the Microcontroller Access Port to select which of the two 256
word blocks of memory are to be accessed.

R/W

READ/WRITE

Start

SLAVE ADDRESS

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DS21140F-page 8

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2004 Microchip Technology Inc.

4.0

WRITE OPERATION

4.1

Byte Write

For the Microcontroller Access Port, the MWP pin must
be held to V

during the entire write operation.

4.2

Page Write

For the Microcontroller Access Port, the MWP pin must
be held to V

during the entire write operation..

Note:

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2004 Microchip Technology Inc.

DS21140F-page 9

24LC41

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

S
T
A
R
T

S
T
O
P

Bus Activity
Master

SDA or

Bus Activity

A
C
K

Control

Byte

Word

Address

Data

MSDA Line

VCLK

SDA LINE

S
T
A
R
T

Control

Byte

Word

Address

Data n

Data n + 15

S
T
O
P

A
C
K

Data n + 1

VCLK/DWP

Bus Activity
Master

Bus Activity

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24LC41

DS21140F-page 10



2004 Microchip Technology Inc.

5.0

ACKNOWLEDGE POLLING

Acknowledge polling can be done for both the DDC
Monitor Port (when in Bidirectional mode) and the
Microcontroller Access Port.

). If the device is still

FIGURE 5-1:

ACKNOWLEDGE
POLLING FLOW

6.0

WRITE PROTECTION

6.1

DDC Monitor Port

would allow the DDC Moni-

tor Port to operate as a serial ROM, although this
configuration would prevent using the device in the
Transmit-only mode.

6.2

Microcontroller Access Port

The Microcontroller Access Port can be used as a
serial ROM when the MWP pin is connected to V

Programming will be inhibited and the entire memory
associated with the Microcontroller Access Port will be
write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W =

Did Device

Acknowledge

(ACK =

Operation

YES

Maker

Microchip Technology Inc.

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