2004 Microchip Technology Inc.
DS21093I-page 1
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
- 5
µ
A standby current typical at 3.0V
• Organized as eight blocks of 256 bytes
(8 x 256 x 8)
• 2-wire serial interface bus, I
2
C™ compatible
• Functional address inputs for cascading up to
8 devices
• Schmitt trigger, filtered inputs for noise
suppression
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 Erase/Write cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead SOIC packages
• Available temperature ranges:
DESCRIPTION
The Microchip Technology Inc. 24LC164 is a cascad-
able 16 Kbit Electrically Erasable PROM (EEPROM).
The device is organized as eight blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low voltage
design permits operation down to 2.5 volts with standby
and active currents of only 5
µ
A and 1 mA respectively.
The 24LC164 also has a page-write capability for up to
16 bytes of data. The 24LC164 is available in the stan-
dard 8-pin DIP and 8-lead surface mount SOIC pack-
ages.
The three select pins, A0, A1 and A2, function as chip
select inputs and allow up to eight devices to share a
common bus, for up to 128 Kbits total system
EEPROM.
PACKAGE TYPES
BLOCK DIAGRAM
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
24
LC
16
4
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24
L
C
16
4
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
PDIP
SOIC
HV GENERATOR
EEPROM ARRAY
(8 x 256 x 8)
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
WP
SDA
SCL
V
CC
V
SS
A2 A1 A0
16K 2.5V Cascadable I
2
C
™
Serial EEPROM
24LC164
I
2
C is a trademark of Philips Corporation.
Obsolete Device
24LC164
DS21093I-page 2
2004 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.3V to V
CC
+1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins
..................................................≥
4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
TABLE 1-2:
DC CHARACTERISTICS
FIGURE 1-1:
BUS TIMING START/STOP
Name
Function
V
SS
Ground
SDA
Serial Address/Data I/O
SCL
Serial Clock
WP
Write Protect Input
V
CC
+2.5V to 5.5V Power Supply
A0, A1, A2
Chip Address Inputs
V
CC
= +2.5V to +5.5V
Commercial (C):
T
AMB
=
0°C to +70°C
Industrial (I):
T
AMB
= -40°C to +85°C
Parameter
Symbol
Min.
Max.
Units
Conditions
WP, SCL and SDA pins:
High level input voltage
V
IH
.7 V
CC
—
V
—
Low level input voltage
V
IL
—
.3 V
CC
V
—
Hysteresis of Schmitt trigger
inputs
V
HYS
.05 V
CC
—
V
(Note)
Low level output voltage
V
OL
—
.40
V
I
OL
= 3.0 mA, V
CC
= 2.5V
Input leakage current
I
LI
-10
10
µ
A
V
IN
= 0.1V to V
CC
Output leakage current
I
LO
-10
10
µΑ
V
OUT
= 0.1V to V
CC
Pin capacitance
(all inputs/outputs)
C
IN
, C
OUT
—
10
pF
V
CC
= 5.0V (Note)
T
AMB
= 25°C, F
CLK
= 1MHz
Operating current
I
CC
Write
I
CC
Read
—
—
3
1
mA
mA
V
CC
= 5.5V, SCL = 400 kHz
Standby current
I
CCS
—
—
30
100
µΑ
µΑ
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
A0 = A1 = A2 = WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
T
SU
:
STA
T
HD
:
STA
V
HYS
T
SU
:
STO
START
STOP
SCL
SDA
2004 Microchip Technology Inc.
DS21093I-page 3
24LC164
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
STANDARD
MODE
V
CC
= 4.5V - 5.5V
FAST MODE
Units
Remarks
Min.
Max.
Min.
Max.
Clock frequency
F
CLK
—
100
—
400
kHz
—
Clock high time
T
HIGH
4000
—
600
—
ns
—
Clock low time
T
LOW
4700
—
1300
—
ns
—
SDA and SCL rise time
T
R
—
1000
—
300
ns
(Note 1)
SDA and SCL fall time
T
F
—
300
—
300
ns
(Note 1)
START condition hold time
T
HD
:
STA
4000
—
600
—
ns
After this period the first
clock pulse is generated
START condition setup time
T
SU
:
STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
—
0
—
ns
—
Data input setup time
T
SU
:
DAT
250
—
100
—
ns
—
STOP condition setup time
T
SU
:
STO
4000
—
600
—
ns
—
Output valid from clock
T
AA
—
3500
—
900
ns
(Note 2)
Bus free time
T
BUF
4700
—
1300
—
ns
Time the bus must be free
before a new transmission
can start
Output fall time from V
IH
min
to V
IL
max
T
OF
—
250
20 + 0.1
Cb
250
ns
(Note 1), C
B
≤
100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
T
SP
—
50
—
50
ns
(Note 3)
Write cycle time
T
WR
—
10
—
10
ms
Byte or Page mode
Endurance
—
1M
—
1M
—
cycles 25°C, V
CC
= 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on Microchip’s website at
www.microchip.com.
SCL
SDA
IN
SDA
OUT
T
SU
:
STA
T
SP
T
AA
T
F
T
LOW
T
HIGH
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
R
24LC164
DS21093I-page 4
2004 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24LC164 supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter and if receiving
data, as receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions, while the 24LC164 works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit..
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24LC164) will leave the data line
HIGH to enable the master to generate the STOP con-
dition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24LC164 does not generate any
acknowledge bits if an internal pro-
gramming cycle is in progress.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
2004 Microchip Technology Inc.
DS21093I-page 5
24LC164
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The first bit is
always a one. The next three bits of the control byte
are the device select bits (A2, A1, A0). They are used
to select which of the eight devices are to be accessed.
The A1 bit must be the inverse of the A1 device select
pin.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect
the three most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one, a read operation is
selected. When set to ‘
0
’ a write operation is selected.
Following the start condition, the 24LC164 looks for the
slave address for the device selected. Depending on
the state of the R/W bit, the 24LC164 will select a read
or write operation.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
4.0
WRITE OPERATION
4.1
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic LOW, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC164. After
receiving another acknowledge signal from the
24LC164, the master device will transmit the data word
to be written into the addressed memory location. The
24LC164 acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle. During this time the 24LC164 will not generate
acknowledge signals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC164 in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 16 data bytes to the
24LC164 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
Operation
Control Code
Block Select
R/W
Read
1
A2 A1 A0
Block Address
1
Write
1
A2 A1 A0
Block Address
0
SLAVE ADDRESS
1
A2
A1
A0
B2
B1
B0
R/W
A
START
READ/WRITE
MSB
LSB
Note:
Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write com-
mand attempts to write across a physi-
cal page boundary, the result is that the
data wraps around to the beginning of
the current page (overwriting data pre-
viously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for
the application software to prevent
page write operations that would
attempt to cross a page boundary.
24LC164
DS21093I-page 6
2004 Microchip Technology Inc.
FIGURE 4-1:
BYTE WRITE
FIGURE 4-2:
PAGE WRITE
S
P
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
A
C
K
A
C
K
CONTROL
BYTE
WORD
ADDRESS
DATA
1
A
2
A
1
A
0
B
2
B
1
B
0
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
DATA (n)
DATA (n + 15)
DATA (n + 1)
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
2
A
1
A
0
B
2
B
1
B
0
2004 Microchip Technology Inc.
DS21093I-page 7
24LC164
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W =
0
). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
6.0
WRITE PROTECTION
The 24LC164 can be used as a serial ROM when the
WP pin is connected to V
CC
. Programming will be
inhibited and the entire memory will be write-protected.
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to ‘
1
’. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1
Current Address Read
The 24LC164 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n +
1
. Upon receipt of the slave address
with R/W bit set to ‘
1
’, the 24LC164 issues an acknowl-
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer but does generate a stop
condition and the 24LC164 discontinues transmission
(Figure 7-1).
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC164 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a ‘
1
’. The 24LC164 will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC164 dis-
continues transmission (Figure 7-2).
7.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC164 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC164 to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC164 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows an entire device memory contents to be serially
read during one operation.
7.4
Noise Protection
The 24LC164 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24LC164
DS21093I-page 8
2004 Microchip Technology Inc.
FIGURE 7-1:
CURRENT ADDRESS READ
FIGURE 7-2:
RANDOM READ
FIGURE 7-3:
SEQUENTIAL READ
8.0
PIN DESCRIPTIONS
8.1
SDA Serial Address/Data Input/
Output
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pul-
lup resistor to V
CC
(typical 10k
Ω
for 100 kHz, 2k
Ω
for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3
WP
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC164 as a
serial ROM when WP is enabled (tied to V
CC
).
8.4
A0, A1, A2
These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24LC164 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight 24LC164s may be connected to the same
bus. These pins must be connected to either V
SS
or
V
CC
.
CONTROL
A
C
K
S
T
A
R
T
S
T
O
P
DATA (n)
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
N
O
S 1 A2 A1A0B2 B1B0
BYTE
P
S
P
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
A
C
K
WORD
ADDRESS (n)
CONTROL
BYTE
S
T
A
R
T
DATA (n)
A
C
K
A
C
K
N
O
A
C
K
1 A2 A1A0B2B1B0
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
A
C
K
N
O
A
C
K
DATA (n)
DATA (n + 1)
DATA (n + 2)
DATA (n + X)
A
C
K
A
C
K
A
C
K
Note:
The level on A1 is compared to the
inverse of the slave address.
2004 Microchip Technology Inc.
DS21093I-page 9
24LC164
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead PDIP (300 mil)
Example
8-Lead SOIC (150 mil)
Example
Legend: XX...X
Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
Week code (week of January 1 is week ‘01’)
NNN
Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
XXXXXXXX
XXXXXNNN
YYWW
24LC164
XXXXXNNN
XXXXXXXX
XXXXYYWW
NNN
24LC164
XXXX0025
NNN
0025
24LC164
DS21093I-page 10
2004 Microchip Technology Inc.
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
MIN
NOM
MAX
Number of Pins
n
8
8
Pitch
p
.100
2.54
Top to Seating Plane
A
.140
.155
.170
3.56
3.94
4.32
Molded Package Thickness
A2
.115
.130
.145
2.92
3.30
3.68
Base to Seating Plane
A1
.015
0.38
Shoulder to Shoulder Width
E
.300
.313
.325
7.62
7.94
8.26
Molded Package Width
E1
.240
.250
.260
6.10
6.35
6.60
Overall Length
D
.360
.373
.385
9.14
9.46
9.78
Tip to Seating Plane
L
.125
.130
.135
3.18
3.30
3.43
Lead Thickness
c
.008
.012
.015
0.20
0.29
0.38
Upper Lead Width
B1
.045
.058
.070
1.14
1.46
1.78
Lower Lead Width
B
.014
.018
.022
0.36
0.46
0.56
Overall Row Spacing
§
eB
.310
.370
.430
7.87
9.40
10.92
Mold Draft Angle Top
α
5
10
15
5
10
15
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
2004 Microchip Technology Inc.
DS21093I-page 1
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
- 5
µ
A standby current typical at 3.0V
• Organized as eight blocks of 256 bytes
(8 x 256 x 8)
• 2-wire serial interface bus, I
2
C™ compatible
• Functional address inputs for cascading up to
8 devices
• Schmitt trigger, filtered inputs for noise
suppression
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 Erase/Write cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead SOIC packages
• Available temperature ranges:
DESCRIPTION
The Microchip Technology Inc. 24LC164 is a cascad-
able 16 Kbit Electrically Erasable PROM (EEPROM).
The device is organized as eight blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low voltage
design permits operation down to 2.5 volts with standby
and active currents of only 5
µ
A and 1 mA respectively.
The 24LC164 also has a page-write capability for up to
16 bytes of data. The 24LC164 is available in the stan-
dard 8-pin DIP and 8-lead surface mount SOIC pack-
ages.
The three select pins, A0, A1 and A2, function as chip
select inputs and allow up to eight devices to share a
common bus, for up to 128 Kbits total system
EEPROM.
PACKAGE TYPES
BLOCK DIAGRAM
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
24
LC
16
4
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24
L
C
16
4
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
PDIP
SOIC
HV GENERATOR
EEPROM ARRAY
(8 x 256 x 8)
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
WP
SDA
SCL
V
CC
V
SS
A2 A1 A0
16K 2.5V Cascadable I
2
C
™
Serial EEPROM
24LC164
I
2
C is a trademark of Philips Corporation.
Obsolete Device
24LC164
DS21093I-page 2
2004 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.3V to V
CC
+1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins
..................................................≥
4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
TABLE 1-2:
DC CHARACTERISTICS
FIGURE 1-1:
BUS TIMING START/STOP
Name
Function
V
SS
Ground
SDA
Serial Address/Data I/O
SCL
Serial Clock
WP
Write Protect Input
V
CC
+2.5V to 5.5V Power Supply
A0, A1, A2
Chip Address Inputs
V
CC
= +2.5V to +5.5V
Commercial (C):
T
AMB
=
0°C to +70°C
Industrial (I):
T
AMB
= -40°C to +85°C
Parameter
Symbol
Min.
Max.
Units
Conditions
WP, SCL and SDA pins:
High level input voltage
V
IH
.7 V
CC
—
V
—
Low level input voltage
V
IL
—
.3 V
CC
V
—
Hysteresis of Schmitt trigger
inputs
V
HYS
.05 V
CC
—
V
(Note)
Low level output voltage
V
OL
—
.40
V
I
OL
= 3.0 mA, V
CC
= 2.5V
Input leakage current
I
LI
-10
10
µ
A
V
IN
= 0.1V to V
CC
Output leakage current
I
LO
-10
10
µΑ
V
OUT
= 0.1V to V
CC
Pin capacitance
(all inputs/outputs)
C
IN
, C
OUT
—
10
pF
V
CC
= 5.0V (Note)
T
AMB
= 25°C, F
CLK
= 1MHz
Operating current
I
CC
Write
I
CC
Read
—
—
3
1
mA
mA
V
CC
= 5.5V, SCL = 400 kHz
Standby current
I
CCS
—
—
30
100
µΑ
µΑ
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
A0 = A1 = A2 = WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
T
SU
:
STA
T
HD
:
STA
V
HYS
T
SU
:
STO
START
STOP
SCL
SDA
2004 Microchip Technology Inc.
DS21093I-page 3
24LC164
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
STANDARD
MODE
V
CC
= 4.5V - 5.5V
FAST MODE
Units
Remarks
Min.
Max.
Min.
Max.
Clock frequency
F
CLK
—
100
—
400
kHz
—
Clock high time
T
HIGH
4000
—
600
—
ns
—
Clock low time
T
LOW
4700
—
1300
—
ns
—
SDA and SCL rise time
T
R
—
1000
—
300
ns
(Note 1)
SDA and SCL fall time
T
F
—
300
—
300
ns
(Note 1)
START condition hold time
T
HD
:
STA
4000
—
600
—
ns
After this period the first
clock pulse is generated
START condition setup time
T
SU
:
STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
—
0
—
ns
—
Data input setup time
T
SU
:
DAT
250
—
100
—
ns
—
STOP condition setup time
T
SU
:
STO
4000
—
600
—
ns
—
Output valid from clock
T
AA
—
3500
—
900
ns
(Note 2)
Bus free time
T
BUF
4700
—
1300
—
ns
Time the bus must be free
before a new transmission
can start
Output fall time from V
IH
min
to V
IL
max
T
OF
—
250
20 + 0.1
Cb
250
ns
(Note 1), C
B
≤
100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
T
SP
—
50
—
50
ns
(Note 3)
Write cycle time
T
WR
—
10
—
10
ms
Byte or Page mode
Endurance
—
1M
—
1M
—
cycles 25°C, V
CC
= 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on Microchip’s website at
www.microchip.com.
SCL
SDA
IN
SDA
OUT
T
SU
:
STA
T
SP
T
AA
T
F
T
LOW
T
HIGH
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
R
24LC164
DS21093I-page 4
2004 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24LC164 supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter and if receiving
data, as receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions, while the 24LC164 works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit..
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24LC164) will leave the data line
HIGH to enable the master to generate the STOP con-
dition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24LC164 does not generate any
acknowledge bits if an internal pro-
gramming cycle is in progress.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
2004 Microchip Technology Inc.
DS21093I-page 5
24LC164
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The first bit is
always a one. The next three bits of the control byte
are the device select bits (A2, A1, A0). They are used
to select which of the eight devices are to be accessed.
The A1 bit must be the inverse of the A1 device select
pin.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect
the three most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one, a read operation is
selected. When set to ‘
0
’ a write operation is selected.
Following the start condition, the 24LC164 looks for the
slave address for the device selected. Depending on
the state of the R/W bit, the 24LC164 will select a read
or write operation.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
4.0
WRITE OPERATION
4.1
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic LOW, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC164. After
receiving another acknowledge signal from the
24LC164, the master device will transmit the data word
to be written into the addressed memory location. The
24LC164 acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle. During this time the 24LC164 will not generate
acknowledge signals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC164 in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 16 data bytes to the
24LC164 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
Operation
Control Code
Block Select
R/W
Read
1
A2 A1 A0
Block Address
1
Write
1
A2 A1 A0
Block Address
0
SLAVE ADDRESS
1
A2
A1
A0
B2
B1
B0
R/W
A
START
READ/WRITE
MSB
LSB
Note:
Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write com-
mand attempts to write across a physi-
cal page boundary, the result is that the
data wraps around to the beginning of
the current page (overwriting data pre-
viously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for
the application software to prevent
page write operations that would
attempt to cross a page boundary.
24LC164
DS21093I-page 6
2004 Microchip Technology Inc.
FIGURE 4-1:
BYTE WRITE
FIGURE 4-2:
PAGE WRITE
S
P
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
A
C
K
A
C
K
CONTROL
BYTE
WORD
ADDRESS
DATA
1
A
2
A
1
A
0
B
2
B
1
B
0
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
DATA (n)
DATA (n + 15)
DATA (n + 1)
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
2
A
1
A
0
B
2
B
1
B
0
2004 Microchip Technology Inc.
DS21093I-page 7
24LC164
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W =
0
). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
6.0
WRITE PROTECTION
The 24LC164 can be used as a serial ROM when the
WP pin is connected to V
CC
. Programming will be
inhibited and the entire memory will be write-protected.
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to ‘
1
’. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1
Current Address Read
The 24LC164 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n +
1
. Upon receipt of the slave address
with R/W bit set to ‘
1
’, the 24LC164 issues an acknowl-
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer but does generate a stop
condition and the 24LC164 discontinues transmission
(Figure 7-1).
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC164 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a ‘
1
’. The 24LC164 will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC164 dis-
continues transmission (Figure 7-2).
7.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC164 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC164 to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC164 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows an entire device memory contents to be serially
read during one operation.
7.4
Noise Protection
The 24LC164 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24LC164
DS21093I-page 8
2004 Microchip Technology Inc.
FIGURE 7-1:
CURRENT ADDRESS READ
FIGURE 7-2:
RANDOM READ
FIGURE 7-3:
SEQUENTIAL READ
8.0
PIN DESCRIPTIONS
8.1
SDA Serial Address/Data Input/
Output
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pul-
lup resistor to V
CC
(typical 10k
Ω
for 100 kHz, 2k
Ω
for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3
WP
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC164 as a
serial ROM when WP is enabled (tied to V
CC
).
8.4
A0, A1, A2
These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24LC164 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight 24LC164s may be connected to the same
bus. These pins must be connected to either V
SS
or
V
CC
.
CONTROL
A
C
K
S
T
A
R
T
S
T
O
P
DATA (n)
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
N
O
S 1 A2 A1A0B2 B1B0
BYTE
P
S
P
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
A
C
K
WORD
ADDRESS (n)
CONTROL
BYTE
S
T
A
R
T
DATA (n)
A
C
K
A
C
K
N
O
A
C
K
1 A2 A1A0B2B1B0
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
A
C
K
N
O
A
C
K
DATA (n)
DATA (n + 1)
DATA (n + 2)
DATA (n + X)
A
C
K
A
C
K
A
C
K
Note:
The level on A1 is compared to the
inverse of the slave address.
2004 Microchip Technology Inc.
DS21093I-page 9
24LC164
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead PDIP (300 mil)
Example
8-Lead SOIC (150 mil)
Example
Legend: XX...X
Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
Week code (week of January 1 is week ‘01’)
NNN
Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
XXXXXXXX
XXXXXNNN
YYWW
24LC164
XXXXXNNN
XXXXXXXX
XXXXYYWW
NNN
24LC164
XXXX0025
NNN
0025
24LC164
DS21093I-page 10
2004 Microchip Technology Inc.
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
MIN
NOM
MAX
Number of Pins
n
8
8
Pitch
p
.100
2.54
Top to Seating Plane
A
.140
.155
.170
3.56
3.94
4.32
Molded Package Thickness
A2
.115
.130
.145
2.92
3.30
3.68
Base to Seating Plane
A1
.015
0.38
Shoulder to Shoulder Width
E
.300
.313
.325
7.62
7.94
8.26
Molded Package Width
E1
.240
.250
.260
6.10
6.35
6.60
Overall Length
D
.360
.373
.385
9.14
9.46
9.78
Tip to Seating Plane
L
.125
.130
.135
3.18
3.30
3.43
Lead Thickness
c
.008
.012
.015
0.20
0.29
0.38
Upper Lead Width
B1
.045
.058
.070
1.14
1.46
1.78
Lower Lead Width
B
.014
.018
.022
0.36
0.46
0.56
Overall Row Spacing
§
eB
.310
.370
.430
7.87
9.40
10.92
Mold Draft Angle Top
α
5
10
15
5
10
15
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
2004 Microchip Technology Inc.
DS21093I-page 1
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
- 5
µ
A standby current typical at 3.0V
• Organized as eight blocks of 256 bytes
(8 x 256 x 8)
• 2-wire serial interface bus, I
2
C™ compatible
• Functional address inputs for cascading up to
8 devices
• Schmitt trigger, filtered inputs for noise
suppression
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 Erase/Write cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead SOIC packages
• Available temperature ranges:
DESCRIPTION
The Microchip Technology Inc. 24LC164 is a cascad-
able 16 Kbit Electrically Erasable PROM (EEPROM).
The device is organized as eight blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low voltage
design permits operation down to 2.5 volts with standby
and active currents of only 5
µ
A and 1 mA respectively.
The 24LC164 also has a page-write capability for up to
16 bytes of data. The 24LC164 is available in the stan-
dard 8-pin DIP and 8-lead surface mount SOIC pack-
ages.
The three select pins, A0, A1 and A2, function as chip
select inputs and allow up to eight devices to share a
common bus, for up to 128 Kbits total system
EEPROM.
PACKAGE TYPES
BLOCK DIAGRAM
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
24
LC
16
4
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24
L
C
16
4
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
PDIP
SOIC
HV GENERATOR
EEPROM ARRAY
(8 x 256 x 8)
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
WP
SDA
SCL
V
CC
V
SS
A2 A1 A0
16K 2.5V Cascadable I
2
C
™
Serial EEPROM
24LC164
I
2
C is a trademark of Philips Corporation.
Obsolete Device
24LC164
DS21093I-page 2
2004 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.3V to V
CC
+1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins
..................................................≥
4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
TABLE 1-2:
DC CHARACTERISTICS
FIGURE 1-1:
BUS TIMING START/STOP
Name
Function
V
SS
Ground
SDA
Serial Address/Data I/O
SCL
Serial Clock
WP
Write Protect Input
V
CC
+2.5V to 5.5V Power Supply
A0, A1, A2
Chip Address Inputs
V
CC
= +2.5V to +5.5V
Commercial (C):
T
AMB
=
0°C to +70°C
Industrial (I):
T
AMB
= -40°C to +85°C
Parameter
Symbol
Min.
Max.
Units
Conditions
WP, SCL and SDA pins:
High level input voltage
V
IH
.7 V
CC
—
V
—
Low level input voltage
V
IL
—
.3 V
CC
V
—
Hysteresis of Schmitt trigger
inputs
V
HYS
.05 V
CC
—
V
(Note)
Low level output voltage
V
OL
—
.40
V
I
OL
= 3.0 mA, V
CC
= 2.5V
Input leakage current
I
LI
-10
10
µ
A
V
IN
= 0.1V to V
CC
Output leakage current
I
LO
-10
10
µΑ
V
OUT
= 0.1V to V
CC
Pin capacitance
(all inputs/outputs)
C
IN
, C
OUT
—
10
pF
V
CC
= 5.0V (Note)
T
AMB
= 25°C, F
CLK
= 1MHz
Operating current
I
CC
Write
I
CC
Read
—
—
3
1
mA
mA
V
CC
= 5.5V, SCL = 400 kHz
Standby current
I
CCS
—
—
30
100
µΑ
µΑ
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
A0 = A1 = A2 = WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
T
SU
:
STA
T
HD
:
STA
V
HYS
T
SU
:
STO
START
STOP
SCL
SDA
2004 Microchip Technology Inc.
DS21093I-page 3
24LC164
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
STANDARD
MODE
V
CC
= 4.5V - 5.5V
FAST MODE
Units
Remarks
Min.
Max.
Min.
Max.
Clock frequency
F
CLK
—
100
—
400
kHz
—
Clock high time
T
HIGH
4000
—
600
—
ns
—
Clock low time
T
LOW
4700
—
1300
—
ns
—
SDA and SCL rise time
T
R
—
1000
—
300
ns
(Note 1)
SDA and SCL fall time
T
F
—
300
—
300
ns
(Note 1)
START condition hold time
T
HD
:
STA
4000
—
600
—
ns
After this period the first
clock pulse is generated
START condition setup time
T
SU
:
STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
—
0
—
ns
—
Data input setup time
T
SU
:
DAT
250
—
100
—
ns
—
STOP condition setup time
T
SU
:
STO
4000
—
600
—
ns
—
Output valid from clock
T
AA
—
3500
—
900
ns
(Note 2)
Bus free time
T
BUF
4700
—
1300
—
ns
Time the bus must be free
before a new transmission
can start
Output fall time from V
IH
min
to V
IL
max
T
OF
—
250
20 + 0.1
Cb
250
ns
(Note 1), C
B
≤
100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
T
SP
—
50
—
50
ns
(Note 3)
Write cycle time
T
WR
—
10
—
10
ms
Byte or Page mode
Endurance
—
1M
—
1M
—
cycles 25°C, V
CC
= 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on Microchip’s website at
www.microchip.com.
SCL
SDA
IN
SDA
OUT
T
SU
:
STA
T
SP
T
AA
T
F
T
LOW
T
HIGH
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
R
24LC164
DS21093I-page 4
2004 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24LC164 supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter and if receiving
data, as receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions, while the 24LC164 works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit..
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24LC164) will leave the data line
HIGH to enable the master to generate the STOP con-
dition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24LC164 does not generate any
acknowledge bits if an internal pro-
gramming cycle is in progress.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
2004 Microchip Technology Inc.
DS21093I-page 5
24LC164
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The first bit is
always a one. The next three bits of the control byte
are the device select bits (A2, A1, A0). They are used
to select which of the eight devices are to be accessed.
The A1 bit must be the inverse of the A1 device select
pin.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect
the three most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one, a read operation is
selected. When set to ‘
0
’ a write operation is selected.
Following the start condition, the 24LC164 looks for the
slave address for the device selected. Depending on
the state of the R/W bit, the 24LC164 will select a read
or write operation.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
4.0
WRITE OPERATION
4.1
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic LOW, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC164. After
receiving another acknowledge signal from the
24LC164, the master device will transmit the data word
to be written into the addressed memory location. The
24LC164 acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle. During this time the 24LC164 will not generate
acknowledge signals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC164 in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 16 data bytes to the
24LC164 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
Operation
Control Code
Block Select
R/W
Read
1
A2 A1 A0
Block Address
1
Write
1
A2 A1 A0
Block Address
0
SLAVE ADDRESS
1
A2
A1
A0
B2
B1
B0
R/W
A
START
READ/WRITE
MSB
LSB
Note:
Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write com-
mand attempts to write across a physi-
cal page boundary, the result is that the
data wraps around to the beginning of
the current page (overwriting data pre-
viously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for
the application software to prevent
page write operations that would
attempt to cross a page boundary.
24LC164
DS21093I-page 6
2004 Microchip Technology Inc.
FIGURE 4-1:
BYTE WRITE
FIGURE 4-2:
PAGE WRITE
S
P
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
A
C
K
A
C
K
CONTROL
BYTE
WORD
ADDRESS
DATA
1
A
2
A
1
A
0
B
2
B
1
B
0
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
DATA (n)
DATA (n + 15)
DATA (n + 1)
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
2
A
1
A
0
B
2
B
1
B
0
2004 Microchip Technology Inc.
DS21093I-page 7
24LC164
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W =
0
). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
6.0
WRITE PROTECTION
The 24LC164 can be used as a serial ROM when the
WP pin is connected to V
CC
. Programming will be
inhibited and the entire memory will be write-protected.
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to ‘
1
’. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1
Current Address Read
The 24LC164 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n +
1
. Upon receipt of the slave address
with R/W bit set to ‘
1
’, the 24LC164 issues an acknowl-
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer but does generate a stop
condition and the 24LC164 discontinues transmission
(Figure 7-1).
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC164 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a ‘
1
’. The 24LC164 will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC164 dis-
continues transmission (Figure 7-2).
7.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC164 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC164 to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC164 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows an entire device memory contents to be serially
read during one operation.
7.4
Noise Protection
The 24LC164 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24LC164
DS21093I-page 8
2004 Microchip Technology Inc.
FIGURE 7-1:
CURRENT ADDRESS READ
FIGURE 7-2:
RANDOM READ
FIGURE 7-3:
SEQUENTIAL READ
8.0
PIN DESCRIPTIONS
8.1
SDA Serial Address/Data Input/
Output
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pul-
lup resistor to V
CC
(typical 10k
Ω
for 100 kHz, 2k
Ω
for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3
WP
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC164 as a
serial ROM when WP is enabled (tied to V
CC
).
8.4
A0, A1, A2
These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24LC164 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight 24LC164s may be connected to the same
bus. These pins must be connected to either V
SS
or
V
CC
.
CONTROL
A
C
K
S
T
A
R
T
S
T
O
P
DATA (n)
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
N
O
S 1 A2 A1A0B2 B1B0
BYTE
P
S
P
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
A
C
K
WORD
ADDRESS (n)
CONTROL
BYTE
S
T
A
R
T
DATA (n)
A
C
K
A
C
K
N
O
A
C
K
1 A2 A1A0B2B1B0
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
A
C
K
N
O
A
C
K
DATA (n)
DATA (n + 1)
DATA (n + 2)
DATA (n + X)
A
C
K
A
C
K
A
C
K
Note:
The level on A1 is compared to the
inverse of the slave address.
2004 Microchip Technology Inc.
DS21093I-page 9
24LC164
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead PDIP (300 mil)
Example
8-Lead SOIC (150 mil)
Example
Legend: XX...X
Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
Week code (week of January 1 is week ‘01’)
NNN
Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
XXXXXXXX
XXXXXNNN
YYWW
24LC164
XXXXXNNN
XXXXXXXX
XXXXYYWW
NNN
24LC164
XXXX0025
NNN
0025
24LC164
DS21093I-page 10
2004 Microchip Technology Inc.
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
MIN
NOM
MAX
Number of Pins
n
8
8
Pitch
p
.100
2.54
Top to Seating Plane
A
.140
.155
.170
3.56
3.94
4.32
Molded Package Thickness
A2
.115
.130
.145
2.92
3.30
3.68
Base to Seating Plane
A1
.015
0.38
Shoulder to Shoulder Width
E
.300
.313
.325
7.62
7.94
8.26
Molded Package Width
E1
.240
.250
.260
6.10
6.35
6.60
Overall Length
D
.360
.373
.385
9.14
9.46
9.78
Tip to Seating Plane
L
.125
.130
.135
3.18
3.30
3.43
Lead Thickness
c
.008
.012
.015
0.20
0.29
0.38
Upper Lead Width
B1
.045
.058
.070
1.14
1.46
1.78
Lower Lead Width
B
.014
.018
.022
0.36
0.46
0.56
Overall Row Spacing
§
eB
.310
.370
.430
7.87
9.40
10.92
Mold Draft Angle Top
α
5
10
15
5
10
15
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
2004 Microchip Technology Inc.
DS21093I-page 1
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
- 5
µ
A standby current typical at 3.0V
• Organized as eight blocks of 256 bytes
(8 x 256 x 8)
• 2-wire serial interface bus, I
2
C™ compatible
• Functional address inputs for cascading up to
8 devices
• Schmitt trigger, filtered inputs for noise
suppression
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 Erase/Write cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead SOIC packages
• Available temperature ranges:
DESCRIPTION
The Microchip Technology Inc. 24LC164 is a cascad-
able 16 Kbit Electrically Erasable PROM (EEPROM).
The device is organized as eight blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low voltage
design permits operation down to 2.5 volts with standby
and active currents of only 5
µ
A and 1 mA respectively.
The 24LC164 also has a page-write capability for up to
16 bytes of data. The 24LC164 is available in the stan-
dard 8-pin DIP and 8-lead surface mount SOIC pack-
ages.
The three select pins, A0, A1 and A2, function as chip
select inputs and allow up to eight devices to share a
common bus, for up to 128 Kbits total system
EEPROM.
PACKAGE TYPES
BLOCK DIAGRAM
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
24
LC
16
4
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24
L
C
16
4
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
PDIP
SOIC
HV GENERATOR
EEPROM ARRAY
(8 x 256 x 8)
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
WP
SDA
SCL
V
CC
V
SS
A2 A1 A0
16K 2.5V Cascadable I
2
C
™
Serial EEPROM
24LC164
I
2
C is a trademark of Philips Corporation.
Obsolete Device
24LC164
DS21093I-page 2
2004 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.3V to V
CC
+1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins
..................................................≥
4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
TABLE 1-2:
DC CHARACTERISTICS
FIGURE 1-1:
BUS TIMING START/STOP
Name
Function
V
SS
Ground
SDA
Serial Address/Data I/O
SCL
Serial Clock
WP
Write Protect Input
V
CC
+2.5V to 5.5V Power Supply
A0, A1, A2
Chip Address Inputs
V
CC
= +2.5V to +5.5V
Commercial (C):
T
AMB
=
0°C to +70°C
Industrial (I):
T
AMB
= -40°C to +85°C
Parameter
Symbol
Min.
Max.
Units
Conditions
WP, SCL and SDA pins:
High level input voltage
V
IH
.7 V
CC
—
V
—
Low level input voltage
V
IL
—
.3 V
CC
V
—
Hysteresis of Schmitt trigger
inputs
V
HYS
.05 V
CC
—
V
(Note)
Low level output voltage
V
OL
—
.40
V
I
OL
= 3.0 mA, V
CC
= 2.5V
Input leakage current
I
LI
-10
10
µ
A
V
IN
= 0.1V to V
CC
Output leakage current
I
LO
-10
10
µΑ
V
OUT
= 0.1V to V
CC
Pin capacitance
(all inputs/outputs)
C
IN
, C
OUT
—
10
pF
V
CC
= 5.0V (Note)
T
AMB
= 25°C, F
CLK
= 1MHz
Operating current
I
CC
Write
I
CC
Read
—
—
3
1
mA
mA
V
CC
= 5.5V, SCL = 400 kHz
Standby current
I
CCS
—
—
30
100
µΑ
µΑ
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
A0 = A1 = A2 = WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
T
SU
:
STA
T
HD
:
STA
V
HYS
T
SU
:
STO
START
STOP
SCL
SDA
2004 Microchip Technology Inc.
DS21093I-page 3
24LC164
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
STANDARD
MODE
V
CC
= 4.5V - 5.5V
FAST MODE
Units
Remarks
Min.
Max.
Min.
Max.
Clock frequency
F
CLK
—
100
—
400
kHz
—
Clock high time
T
HIGH
4000
—
600
—
ns
—
Clock low time
T
LOW
4700
—
1300
—
ns
—
SDA and SCL rise time
T
R
—
1000
—
300
ns
(Note 1)
SDA and SCL fall time
T
F
—
300
—
300
ns
(Note 1)
START condition hold time
T
HD
:
STA
4000
—
600
—
ns
After this period the first
clock pulse is generated
START condition setup time
T
SU
:
STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
—
0
—
ns
—
Data input setup time
T
SU
:
DAT
250
—
100
—
ns
—
STOP condition setup time
T
SU
:
STO
4000
—
600
—
ns
—
Output valid from clock
T
AA
—
3500
—
900
ns
(Note 2)
Bus free time
T
BUF
4700
—
1300
—
ns
Time the bus must be free
before a new transmission
can start
Output fall time from V
IH
min
to V
IL
max
T
OF
—
250
20 + 0.1
Cb
250
ns
(Note 1), C
B
≤
100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
T
SP
—
50
—
50
ns
(Note 3)
Write cycle time
T
WR
—
10
—
10
ms
Byte or Page mode
Endurance
—
1M
—
1M
—
cycles 25°C, V
CC
= 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on Microchip’s website at
www.microchip.com.
SCL
SDA
IN
SDA
OUT
T
SU
:
STA
T
SP
T
AA
T
F
T
LOW
T
HIGH
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
R
24LC164
DS21093I-page 4
2004 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24LC164 supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter and if receiving
data, as receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions, while the 24LC164 works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit..
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24LC164) will leave the data line
HIGH to enable the master to generate the STOP con-
dition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24LC164 does not generate any
acknowledge bits if an internal pro-
gramming cycle is in progress.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
2004 Microchip Technology Inc.
DS21093I-page 5
24LC164
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The first bit is
always a one. The next three bits of the control byte
are the device select bits (A2, A1, A0). They are used
to select which of the eight devices are to be accessed.
The A1 bit must be the inverse of the A1 device select
pin.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect
the three most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one, a read operation is
selected. When set to ‘
0
’ a write operation is selected.
Following the start condition, the 24LC164 looks for the
slave address for the device selected. Depending on
the state of the R/W bit, the 24LC164 will select a read
or write operation.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
4.0
WRITE OPERATION
4.1
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic LOW, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC164. After
receiving another acknowledge signal from the
24LC164, the master device will transmit the data word
to be written into the addressed memory location. The
24LC164 acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle. During this time the 24LC164 will not generate
acknowledge signals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC164 in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 16 data bytes to the
24LC164 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
Operation
Control Code
Block Select
R/W
Read
1
A2 A1 A0
Block Address
1
Write
1
A2 A1 A0
Block Address
0
SLAVE ADDRESS
1
A2
A1
A0
B2
B1
B0
R/W
A
START
READ/WRITE
MSB
LSB
Note:
Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write com-
mand attempts to write across a physi-
cal page boundary, the result is that the
data wraps around to the beginning of
the current page (overwriting data pre-
viously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for
the application software to prevent
page write operations that would
attempt to cross a page boundary.
24LC164
DS21093I-page 6
2004 Microchip Technology Inc.
FIGURE 4-1:
BYTE WRITE
FIGURE 4-2:
PAGE WRITE
S
P
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
A
C
K
A
C
K
CONTROL
BYTE
WORD
ADDRESS
DATA
1
A
2
A
1
A
0
B
2
B
1
B
0
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
DATA (n)
DATA (n + 15)
DATA (n + 1)
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
2
A
1
A
0
B
2
B
1
B
0
2004 Microchip Technology Inc.
DS21093I-page 7
24LC164
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W =
0
). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
6.0
WRITE PROTECTION
The 24LC164 can be used as a serial ROM when the
WP pin is connected to V
CC
. Programming will be
inhibited and the entire memory will be write-protected.
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to ‘
1
’. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1
Current Address Read
The 24LC164 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n +
1
. Upon receipt of the slave address
with R/W bit set to ‘
1
’, the 24LC164 issues an acknowl-
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer but does generate a stop
condition and the 24LC164 discontinues transmission
(Figure 7-1).
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC164 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a ‘
1
’. The 24LC164 will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC164 dis-
continues transmission (Figure 7-2).
7.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC164 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC164 to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC164 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows an entire device memory contents to be serially
read during one operation.
7.4
Noise Protection
The 24LC164 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24LC164
DS21093I-page 8
2004 Microchip Technology Inc.
FIGURE 7-1:
CURRENT ADDRESS READ
FIGURE 7-2:
RANDOM READ
FIGURE 7-3:
SEQUENTIAL READ
8.0
PIN DESCRIPTIONS
8.1
SDA Serial Address/Data Input/
Output
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pul-
lup resistor to V
CC
(typical 10k
Ω
for 100 kHz, 2k
Ω
for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3
WP
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC164 as a
serial ROM when WP is enabled (tied to V
CC
).
8.4
A0, A1, A2
These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24LC164 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight 24LC164s may be connected to the same
bus. These pins must be connected to either V
SS
or
V
CC
.
CONTROL
A
C
K
S
T
A
R
T
S
T
O
P
DATA (n)
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
N
O
S 1 A2 A1A0B2 B1B0
BYTE
P
S
P
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
A
C
K
WORD
ADDRESS (n)
CONTROL
BYTE
S
T
A
R
T
DATA (n)
A
C
K
A
C
K
N
O
A
C
K
1 A2 A1A0B2B1B0
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
A
C
K
N
O
A
C
K
DATA (n)
DATA (n + 1)
DATA (n + 2)
DATA (n + X)
A
C
K
A
C
K
A
C
K
Note:
The level on A1 is compared to the
inverse of the slave address.
2004 Microchip Technology Inc.
DS21093I-page 9
24LC164
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead PDIP (300 mil)
Example
8-Lead SOIC (150 mil)
Example
Legend: XX...X
Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
Week code (week of January 1 is week ‘01’)
NNN
Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
XXXXXXXX
XXXXXNNN
YYWW
24LC164
XXXXXNNN
XXXXXXXX
XXXXYYWW
NNN
24LC164
XXXX0025
NNN
0025
24LC164
DS21093I-page 10
2004 Microchip Technology Inc.
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
MIN
NOM
MAX
Number of Pins
n
8
8
Pitch
p
.100
2.54
Top to Seating Plane
A
.140
.155
.170
3.56
3.94
4.32
Molded Package Thickness
A2
.115
.130
.145
2.92
3.30
3.68
Base to Seating Plane
A1
.015
0.38
Shoulder to Shoulder Width
E
.300
.313
.325
7.62
7.94
8.26
Molded Package Width
E1
.240
.250
.260
6.10
6.35
6.60
Overall Length
D
.360
.373
.385
9.14
9.46
9.78
Tip to Seating Plane
L
.125
.130
.135
3.18
3.30
3.43
Lead Thickness
c
.008
.012
.015
0.20
0.29
0.38
Upper Lead Width
B1
.045
.058
.070
1.14
1.46
1.78
Lower Lead Width
B
.014
.018
.022
0.36
0.46
0.56
Overall Row Spacing
§
eB
.310
.370
.430
7.87
9.40
10.92
Mold Draft Angle Top
α
5
10
15
5
10
15
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
2004 Microchip Technology Inc.
DS21093I-page 1
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
- 5
µ
A standby current typical at 3.0V
• Organized as eight blocks of 256 bytes
(8 x 256 x 8)
• 2-wire serial interface bus, I
2
C™ compatible
• Functional address inputs for cascading up to
8 devices
• Schmitt trigger, filtered inputs for noise
suppression
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 Erase/Write cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead SOIC packages
• Available temperature ranges:
DESCRIPTION
The Microchip Technology Inc. 24LC164 is a cascad-
able 16 Kbit Electrically Erasable PROM (EEPROM).
The device is organized as eight blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low voltage
design permits operation down to 2.5 volts with standby
and active currents of only 5
µ
A and 1 mA respectively.
The 24LC164 also has a page-write capability for up to
16 bytes of data. The 24LC164 is available in the stan-
dard 8-pin DIP and 8-lead surface mount SOIC pack-
ages.
The three select pins, A0, A1 and A2, function as chip
select inputs and allow up to eight devices to share a
common bus, for up to 128 Kbits total system
EEPROM.
PACKAGE TYPES
BLOCK DIAGRAM
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
24
LC
16
4
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24
L
C
16
4
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
PDIP
SOIC
HV GENERATOR
EEPROM ARRAY
(8 x 256 x 8)
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
WP
SDA
SCL
V
CC
V
SS
A2 A1 A0
16K 2.5V Cascadable I
2
C
™
Serial EEPROM
24LC164
I
2
C is a trademark of Philips Corporation.
Obsolete Device
24LC164
DS21093I-page 2
2004 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.3V to V
CC
+1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins
..................................................≥
4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
TABLE 1-2:
DC CHARACTERISTICS
FIGURE 1-1:
BUS TIMING START/STOP
Name
Function
V
SS
Ground
SDA
Serial Address/Data I/O
SCL
Serial Clock
WP
Write Protect Input
V
CC
+2.5V to 5.5V Power Supply
A0, A1, A2
Chip Address Inputs
V
CC
= +2.5V to +5.5V
Commercial (C):
T
AMB
=
0°C to +70°C
Industrial (I):
T
AMB
= -40°C to +85°C
Parameter
Symbol
Min.
Max.
Units
Conditions
WP, SCL and SDA pins:
High level input voltage
V
IH
.7 V
CC
—
V
—
Low level input voltage
V
IL
—
.3 V
CC
V
—
Hysteresis of Schmitt trigger
inputs
V
HYS
.05 V
CC
—
V
(Note)
Low level output voltage
V
OL
—
.40
V
I
OL
= 3.0 mA, V
CC
= 2.5V
Input leakage current
I
LI
-10
10
µ
A
V
IN
= 0.1V to V
CC
Output leakage current
I
LO
-10
10
µΑ
V
OUT
= 0.1V to V
CC
Pin capacitance
(all inputs/outputs)
C
IN
, C
OUT
—
10
pF
V
CC
= 5.0V (Note)
T
AMB
= 25°C, F
CLK
= 1MHz
Operating current
I
CC
Write
I
CC
Read
—
—
3
1
mA
mA
V
CC
= 5.5V, SCL = 400 kHz
Standby current
I
CCS
—
—
30
100
µΑ
µΑ
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
A0 = A1 = A2 = WP = V
SS
Note:
This parameter is periodically sampled and not 100% tested.
T
SU
:
STA
T
HD
:
STA
V
HYS
T
SU
:
STO
START
STOP
SCL
SDA
2004 Microchip Technology Inc.
DS21093I-page 3
24LC164
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
STANDARD
MODE
V
CC
= 4.5V - 5.5V
FAST MODE
Units
Remarks
Min.
Max.
Min.
Max.
Clock frequency
F
CLK
—
100
—
400
kHz
—
Clock high time
T
HIGH
4000
—
600
—
ns
—
Clock low time
T
LOW
4700
—
1300
—
ns
—
SDA and SCL rise time
T
R
—
1000
—
300
ns
(Note 1)
SDA and SCL fall time
T
F
—
300
—
300
ns
(Note 1)
START condition hold time
T
HD
:
STA
4000
—
600
—
ns
After this period the first
clock pulse is generated
START condition setup time
T
SU
:
STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
—
0
—
ns
—
Data input setup time
T
SU
:
DAT
250
—
100
—
ns
—
STOP condition setup time
T
SU
:
STO
4000
—
600
—
ns
—
Output valid from clock
T
AA
—
3500
—
900
ns
(Note 2)
Bus free time
T
BUF
4700
—
1300
—
ns
Time the bus must be free
before a new transmission
can start
Output fall time from V
IH
min
to V
IL
max
T
OF
—
250
20 + 0.1
Cb
250
ns
(Note 1), C
B
≤
100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
T
SP
—
50
—
50
ns
(Note 3)
Write cycle time
T
WR
—
10
—
10
ms
Byte or Page mode
Endurance
—
1M
—
1M
—
cycles 25°C, V
CC
= 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on Microchip’s website at
www.microchip.com.
SCL
SDA
IN
SDA
OUT
T
SU
:
STA
T
SP
T
AA
T
F
T
LOW
T
HIGH
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
R
24LC164
DS21093I-page 4
2004 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24LC164 supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter and if receiving
data, as receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions, while the 24LC164 works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit..
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24LC164) will leave the data line
HIGH to enable the master to generate the STOP con-
dition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24LC164 does not generate any
acknowledge bits if an internal pro-
gramming cycle is in progress.
SCL
SDA
(A)
(B)
(D)
(D)
(A)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
2004 Microchip Technology Inc.
DS21093I-page 5
24LC164
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The first bit is
always a one. The next three bits of the control byte
are the device select bits (A2, A1, A0). They are used
to select which of the eight devices are to be accessed.
The A1 bit must be the inverse of the A1 device select
pin.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect
the three most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one, a read operation is
selected. When set to ‘
0
’ a write operation is selected.
Following the start condition, the 24LC164 looks for the
slave address for the device selected. Depending on
the state of the R/W bit, the 24LC164 will select a read
or write operation.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
4.0
WRITE OPERATION
4.1
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic LOW, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC164. After
receiving another acknowledge signal from the
24LC164, the master device will transmit the data word
to be written into the addressed memory location. The
24LC164 acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle. During this time the 24LC164 will not generate
acknowledge signals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC164 in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 16 data bytes to the
24LC164 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
Operation
Control Code
Block Select
R/W
Read
1
A2 A1 A0
Block Address
1
Write
1
A2 A1 A0
Block Address
0
SLAVE ADDRESS
1
A2
A1
A0
B2
B1
B0
R/W
A
START
READ/WRITE
MSB
LSB
Note:
Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write com-
mand attempts to write across a physi-
cal page boundary, the result is that the
data wraps around to the beginning of
the current page (overwriting data pre-
viously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for
the application software to prevent
page write operations that would
attempt to cross a page boundary.
24LC164
DS21093I-page 6
2004 Microchip Technology Inc.
FIGURE 4-1:
BYTE WRITE
FIGURE 4-2:
PAGE WRITE
S
P
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
A
C
K
A
C
K
CONTROL
BYTE
WORD
ADDRESS
DATA
1
A
2
A
1
A
0
B
2
B
1
B
0
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
DATA (n)
DATA (n + 15)
DATA (n + 1)
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
2
A
1
A
0
B
2
B
1
B
0
2004 Microchip Technology Inc.
DS21093I-page 7
24LC164
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W =
0
). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
6.0
WRITE PROTECTION
The 24LC164 can be used as a serial ROM when the
WP pin is connected to V
CC
. Programming will be
inhibited and the entire memory will be write-protected.
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to ‘
1
’. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1
Current Address Read
The 24LC164 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n +
1
. Upon receipt of the slave address
with R/W bit set to ‘
1
’, the 24LC164 issues an acknowl-
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer but does generate a stop
condition and the 24LC164 discontinues transmission
(Figure 7-1).
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC164 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a ‘
1
’. The 24LC164 will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC164 dis-
continues transmission (Figure 7-2).
7.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC164 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC164 to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC164 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows an entire device memory contents to be serially
read during one operation.
7.4
Noise Protection
The 24LC164 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24LC164
DS21093I-page 8
2004 Microchip Technology Inc.
FIGURE 7-1:
CURRENT ADDRESS READ
FIGURE 7-2:
RANDOM READ
FIGURE 7-3:
SEQUENTIAL READ
8.0
PIN DESCRIPTIONS
8.1
SDA Serial Address/Data Input/
Output
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pul-
lup resistor to V
CC
(typical 10k
Ω
for 100 kHz, 2k
Ω
for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3
WP
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC164 as a
serial ROM when WP is enabled (tied to V
CC
).
8.4
A0, A1, A2
These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24LC164 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight 24LC164s may be connected to the same
bus. These pins must be connected to either V
SS
or
V
CC
.
CONTROL
A
C
K
S
T
A
R
T
S
T
O
P
DATA (n)
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
N
O
S 1 A2 A1A0B2 B1B0
BYTE
P
S
P
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
A
C
K
WORD
ADDRESS (n)
CONTROL
BYTE
S
T
A
R
T
DATA (n)
A
C
K
A
C
K
N
O
A
C
K
1 A2 A1A0B2B1B0
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
A
C
K
N
O
A
C
K
DATA (n)
DATA (n + 1)
DATA (n + 2)
DATA (n + X)
A
C
K
A
C
K
A
C
K
Note:
The level on A1 is compared to the
inverse of the slave address.
2004 Microchip Technology Inc.
DS21093I-page 9
24LC164
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead PDIP (300 mil)
Example
8-Lead SOIC (150 mil)
Example
Legend: XX...X
Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
Week code (week of January 1 is week ‘01’)
NNN
Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
XXXXXXXX
XXXXXNNN
YYWW
24LC164
XXXXXNNN
XXXXXXXX
XXXXYYWW
NNN
24LC164
XXXX0025
NNN
0025
24LC164
DS21093I-page 10
2004 Microchip Technology Inc.
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
MIN
NOM
MAX
Number of Pins
n
8
8
Pitch
p
.100
2.54
Top to Seating Plane
A
.140
.155
.170
3.56
3.94
4.32
Molded Package Thickness
A2
.115
.130
.145
2.92
3.30
3.68
Base to Seating Plane
A1
.015
0.38
Shoulder to Shoulder Width
E
.300
.313
.325
7.62
7.94
8.26
Molded Package Width
E1
.240
.250
.260
6.10
6.35
6.60
Overall Length
D
.360
.373
.385
9.14
9.46
9.78
Tip to Seating Plane
L
.125
.130
.135
3.18
3.30
3.43
Lead Thickness
c
.008
.012
.015
0.20
0.29
0.38
Upper Lead Width
B1
.045
.058
.070
1.14
1.46
1.78
Lower Lead Width
B
.014
.018
.022
0.36
0.46
0.56
Overall Row Spacing
§
eB
.310
.370
.430
7.87
9.40
10.92
Mold Draft Angle Top
α
5
10
15
5
10
15
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic