IRFR7446PbF Product Datasheet

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background image

Fig 1.   Typical On-Resistance vs. Gate Voltage

Fig 2.  Maximum Drain Current vs. Case Temperature

HEXFET

®

 Power MOSFET

Benefits

l

Improved  Gate, Avalanche and Dynamic  dV/dt
Ruggedness

l

Fully Characterized Capacitance and Avalanche

     SOA

l

Enhanced body diode dv/dt and dI/dt Capability

Lead-Free

G

D

S

Gate

Drain

Source

Applications

Brushed Motor drive applications

BLDC Motor drive applications

PWM Inverterized topologies

Battery powered circuits

Half-bridge and full-bridge topologies

Synchronous rectifier applications

Resonant mode power supplies

OR-ing and redundant power switches

DC/DC and AC/DC converters

D-Pak

IRFR7446TRPbF

G

S

D

25

50

75

100

125

150

175

 TC,  Case Temperature (°C)

0

20

40

60

80

100

120

I D

,  

D

ra

in

 C

ur

re

nt

 (

A

)

LIMITED BY PACKAGE

4

8

12

16

20

VGS, Gate-to-Source Voltage (V)

2

4

6

8

10

R

D

S

(o

n)

,  

D

ra

in

-t

-S

ou

rc

O

R

es

is

ta

nc

(m

Ω

)

TJ = 25°C

TJ = 125°C

ID = 56A

Ordering Information

Form

Quantity

IRFR7446PBF

D-PAK

Tube/Bulk

75

IRFR7446PBF

IRFR7446TRPBF

D-PAK

Tape and Reel

2000

IRFR7446TRPBF

Orderable part number

Package Type

Standard Pack

Complete Part Number

D

S

G

V

DSS

40V

R

DS(on)

   typ.

3.0mΩ

              max.

3.9m

Ω

I

(Silicon Limited)

120Ac

I

(Package Limited)

56A 

Strong

IR

FET™

IRFR7446PbF

  

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Notes:



Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 56A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)

‚

Repetitive rating;  pulse width limited by max. junction
temperature.

ƒ

Limited by T

Jmax

, starting T

= 25°C, L = 0.08mH

R

= 50

Ω, I

AS 

= 56A, V

GS

 =10V.

„

I

SD 

≤ 100A, di/dt ≤ 1306A/μs, V

DD 

≤ V

(BR)DSS

, T

≤ 175°C.

…

Pulse width 

≤ 400μs; duty cycle ≤ 2%.

†

C

oss

 eff. (TR) is a fixed capacitance that gives the same charging time

as C

oss 

while V

DS 

is rising from 0 to 80% V

DSS

.

‡

C

oss

 eff. (ER) is a fixed capacitance that gives the same energy as

C

oss 

while V

DS 

is rising from 0 to 80% V

DSS

.

ˆ

When mounted on 1" square PCB (FR-4 or G-10 Material).  For recom
mended footprint and soldering techniques refer to application note #AN-994.

‰

R

θ 

is measured at T

J

 approximately 90°C.

Š

Limited by T

Jmax 

starting

 

T

= 25°C, L= 1mH, R

= 50

Ω, I

AS 

= 22A, V

GS

 =10V.

*

L

D

 and L

S

 are Internal Drain Inductance and Internal Source Inductance

Static @ T

J

 = 25°C (unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Units

V

(BR)DSS

Drain-to-Source Breakdown Voltage

40

–––

–––

V

ΔV

(BR)DSS

/

ΔT

Breakdown Voltage Temp. Coefficient

–––

26

–––

mV/°C

R

DS(on)

Static Drain-to-Source On-Resistance

–––

3.0

3.9

m

Ω

4.4

–––

V

GS(th)

Gate Threshold Voltage

2.2

3.0

3.9

V

I

DSS

Drain-to-Source Leakage Current

–––

–––

1.0

μA

–––

–––

150

I

GSS

Gate-to-Source Forward Leakage

–––

–––

100

nA

Gate-to-Source Reverse Leakage

–––

–––

-100

R

G

Internal Gate Resistance

–––

1.5

–––

Ω

V

GS

 = 20V

V

GS

 = -20V

V

GS

 = 6.0V, I

D

 = 28A 

g

V

DS

 = V

GS

, I

D

 = 100μA

Conditions

V

GS

 = 0V, I

D

 = 250μA

d

Reference to 25°C, I

D

 = 1mA

V

GS

 = 10V, I

D

 = 56A 

g

V

DS

 = 40V, V

GS

 = 0V

V

DS

 = 40V, V

GS

 = 0V, T

J

 = 125°C

Absolute Maximum Ratings

Symbol

Parameter

Units

I

D

 @ T

C

 = 25°C

Continuous Drain Current, V

GS

 @ 10V (Silicon Limited)

I

D

 @ T

C

 = 100°C

Continuous Drain Current, V

GS

 @ 10V (Silicon Limited)

I

D

 @ T

C

 = 25°C

Continuous Drain Current, V

GS

 @ 10V (Wire Bond Limited)

I

DM

Pulsed Drain Current 

d

P

D

 @T

C

 = 25°C

Maximum Power Dissipation  

W

Linear Derating Factor

W/°C

V

GS

Gate-to-Source Voltage

V

T

Operating Junction and

T

STG

Storage Temperature Range

Soldering Temperature, for 10 seconds (1.6mm from case)

Avalanche Characteristics

E

AS (Thermally limited) 

Single Pulse Avalanche Energy 

e

E

AS (Thermally limited) 

Single Pulse Avalanche Energy  

l

I

AR

Avalanche Current 

d

A

E

AR

Repetitive Avalanche Energy 

d

mJ

Thermal Resistance

Symbol

Parameter

Typ.

Max.

Units

R

θJC 

Junction-to-Case 

k

–––

1.52

R

θJA 

–––

50

R

θJA 

Junction-to-Ambient 

k

–––

110

251

 ± 20

0.66

Max.

120

c

84

c

520

56

mJ

-55  to + 175

See Fig 15,16, 23a, 23b

Junction-to-Ambient (PCB Mount) 

j

A

°C

300

98

125

°C/W

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IRFR7446PbF

  

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S

D

G

Dynamic @ T

J

 = 25°C (unless otherwise specified)

Symbol

Parameter

Min. Typ. Max. Units

gfs

Forward Transconductance

170

–––

–––

S

Q

g

Total Gate Charge

–––

65

130

nC

Q

gs

Gate-to-Source Charge

–––

18

–––

Q

gd

Gate-to-Drain ("Miller") Charge

–––

22

–––

Q

sync

Total Gate Charge Sync. (Q

g

 - Q

gd

)

–––

43

–––

t

d(on)

Turn-On Delay Time

–––

9.8

–––

ns

t

r

Rise Time

–––

13

–––

t

d(off)

Turn-Off Delay Time

–––

32

–––

t

f

Fall Time

–––

20

–––

C

iss

Input Capacitance

–––

3150

–––

pF

C

oss

Output Capacitance

–––

480

–––

C

rss

Reverse Transfer Capacitance

–––

330

–––

C

oss

 eff. (ER) Effective Output Capacitance (Energy Related) 

–––

570

–––

C

oss

 eff. (TR) Effective Output Capacitance (Time Related)

–––

680

–––

Diode Characteristics

Symbol

        Parameter

Min. Typ. Max. Units

I

S

Continuous Source Current 

–––

––– 120c

A

(Body Diode)

I

SM

Pulsed Source Current

–––

–––

480

A

(Body Diode)

d

V

SD

Diode Forward Voltage

–––

0.9

1.3

V

dv/dt

Peak Diode Recovery f

–––

4.8

–––

V/ns

t

rr

Reverse Recovery Time

–––

20

–––

ns

T

J

 = 25°C

V

R

 = 34V,

–––

21

–––

T

J

 = 125°C

I

F

 = 56A

Q

rr

Reverse Recovery Charge

–––

13

–––

nC T

J

 = 25°C

di/dt = 100A/μs g

–––

13

–––

T

J

 = 125°C

I

RRM

Reverse Recovery Current

–––

1.8

–––

A

T

J

 = 25°C

t

on

Forward Turn-On Time

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 

*

T

J

 = 25°C, I

S

 = 56A, V

GS

 = 0V 

Conditions

V

GS

 = 10V g

V

GS

 = 0V

V

DS

 = 25V

ƒ = 1.0 MHz,  See Fig. 5
V

GS

 = 0V, V

DS

 = 0V to 32V 

i  See Fig. 12

V

GS

 = 0V, V

DS

 = 0V to 32V 

h

V

GS

 = 10V

g

V

DD

 = 20V

I

D

 = 56A, V

DS

 =0V, V

GS

 = 10V

T

J

 = 175°C, I

S

 = 56A, V

DS

 = 40V g

integral reverse
p-n junction diode.

MOSFET symbol
showing  the

I

D

 = 30A

R

G

 = 2.7Ω

Conditions

V

DS

 = 10V, I

D

 = 56A

I

D

 =56A

V

DS

 =20V

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Fig 3.  Typical Output Characteristics

Fig 5.  Typical Transfer Characteristics

Fig 6.  Normalized On-Resistance vs. Temperature

Fig 4.  Typical Output Characteristics

Fig 8.  Typical Gate Charge vs. Gate-to-Source Voltage

Fig 7.  Typical Capacitance vs. Drain-to-Source Voltage

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.1

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

≤ 60μs PULSE WIDTH

Tj = 25°C

4.3V

VGS

TOP          

15V

10V

7.0V

6.0V

5.5V

5.0V

4.5V

BOTTOM

4.3V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

≤ 60μs PULSE WIDTH

Tj = 175°C

4.3V

VGS

TOP          

15V

10V

7.0V

6.0V

5.5V

5.0V

4.5V

BOTTOM

4.3V

2.0

3.0

4.0

5.0

6.0

7.0

8.0

VGS, Gate-to-Source Voltage (V)

0.1

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

VDS = 10V
≤ 60μs PULSE WIDTH

TJ = 25°C

TJ = 175°C

1

10

100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

100000

C

, C

ap

ac

ita

nc

(p

F

)

Coss

Crss

Ciss

VGS   = 0V,       f = 1 MHZ

Ciss   = Cgs + Cgd,  Cds SHORTED
Crss   = Cgd 
Coss  = Cds + Cgd

0

20

40

60

80

100

 QG  Total Gate Charge (nC)

0

4

8

12

16

V

G

S

, G

at

e-

to

-S

ou

rc

V

ol

ta

ge

 (

V

)

VDS= 32V

VDS= 20V

ID= 56A

-60 -40 -20 0

20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

R

D

S

(o

n)

 , 

D

ra

in

-t

o-

S

ou

rc

O

R

es

is

ta

nc

   

   

   

   

   

   

   

 (

N

or

m

al

iz

ed

)

ID = 56A

VGS = 10V

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Fig 10.  Maximum Safe Operating Area

Fig 11.  Drain-to-Source Breakdown Voltage

Fig 9.  Typical Source-Drain Diode

Forward Voltage

Fig 12.  Typical C

OSS

 Stored Energy

Fig 13.   Typical On-Resistance vs. Drain Current

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

VSD, Source-to-Drain Voltage (V)

0.1

1

10

100

1000

I S

D

, R

ev

er

se

 D

ra

in

 C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 175°C

VGS = 0V

-60 -40 -20 0 20 40 60 80 100120140160180

TJ , Temperature ( °C )

40

41

42

43

44

45

46

47

48

49

V

(B

R

)D

S

S

,  

D

ra

in

-t

o-

S

ou

rc

B

re

ak

do

w

V

ol

ta

ge

 (

V

)

Id = 1.0mA

0

10

20

30

40

VDS, Drain-to-Source Voltage (V)

0.0

0.1

0.2

0.3

0.4

E

ne

rg

J)

0

20 40 60 80 100 120 140 160 180 200

ID, Drain Current (A)

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

R

D

S

(o

n)

,  

D

ra

in

-t

-S

ou

rc

O

R

es

is

ta

nc

(m

Ω

)

VGS = 5.5V

VGS = 6.0V

VGS = 7.0V

VGS = 8.0V

VGS =10V

0.1

1

10

VDS,  Drain-toSource Voltage (V)

0.1

1

10

100

1000

I D

,  

D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

100μsec

DC

L

imited by Package

OPERATION IN THIS AREA 
LIMITED BY RDS(on)

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Fig 14.  Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 15.  Typical Avalanche Current vs.Pulsewidth

Fig 16.  Maximum Avalanche Energy vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T

jmax

. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT

jmax

 is not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 23a, 23b.
4. P

D (ave) 

= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

during avalanche).

6. I

av 

= Allowable avalanche current.

7. 

ΔT

 = 

Allowable rise in junction temperature, not to exceed

 

T

jmax 

(assumed as

25°C in Figure 14, 15).
t

av = 

Average time in avalanche.

D = Duty cycle in avalanche =  t

av 

·f

Z

thJC

(D, t

av

) = Transient thermal resistance, see Figures 14)

P

D (ave)

 = 1/2 ( 1.3·BV·I

av

) =

 DT/ Z

thJC

I

av 

=

 

2

DT/ [1.3·BV·Z

th

]

E

AS (AR)

 = P

D (ave)

·t

av

1E-006

1E-005

0.0001

0.001

0.01

0.1

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

1

10

T

he

rm

al

 R

es

po

ns

Z  

th

JC

 )

 °

C

/W

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

25

50

75

100

125

150

175

Starting TJ , Junction Temperature (°C)

0

20

40

60

80

100

120

140

E

A

R

 ,

 A

va

la

nc

he

 E

ne

rg

(m

J)

TOP          Single Pulse                
BOTTOM   1.0% Duty Cycle
ID = 56A

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

0.1

1

10

100

A

va

la

nc

he

 C

ur

re

nt

 (

A

)

Allowed avalanche Current vs avalanche 
pulsewidth, tav, assuming ΔΤ j = 25°C and 

Tstart = 150°C.

Allowed avalanche Current vs avalanche 
pulsewidth, tav, assuming ΔTj = 150°C and 

Tstart =25°C (Single Pulse)

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Fig. 18 - Typical Recovery Current vs. di

f

/dt

Fig 17.  Threshold Voltage vs. Temperature

Fig. 20 - Typical Stored Charge vs. di

f

/dt

Fig. 19 - Typical Recovery Current vs. di

f

/dt

Fig. 21 - Typical Stored Charge vs. di

f

/dt

-75 -50 -25

0

25

50

75 100 125 150 175

TJ , Temperature ( °C )

1.5

2.0

2.5

3.0

3.5

4.0

4.5

V

G

S

(t

h)

 G

at

th

re

sh

ol

V

ol

ta

ge

 (

V

)

ID =50μA

ID = 250μA

ID = 1.0mA

ID = 1.0A

0

200

400

600

800

1000

diF /dt (A/μs)

0

2

4

6

I R

R

M

 (

A

)

IF = 34A
VR = 34V
TJ = 25°C
TJ = 125°C

0

200

400

600

800

1000

diF /dt (A/μs)

0

2

4

6

I R

R

M

 (

A

)

IF = 56A
VR = 34V
TJ = 25°C
TJ = 125°C

0

200

400

600

800

1000

diF /dt (A/μs)

0

20

40

60

80

Q

R

R

 (

nC

)

IF = 34A
VR = 34V
TJ = 25°C
TJ = 125°C

0

200

400

600

800

1000

diF /dt (A/μs)

0

20

40

60

80

Q

R

R

 (

nC

)

IF = 56A
VR = 34V
TJ = 25°C
TJ = 125°C

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IRFR7446PbF

  

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Fig 24a.  Switching Time Test Circuit

Fig 24b.  Switching Time Waveforms

Fig 23b.  Unclamped Inductive Waveforms

Fig 23a.  Unclamped Inductive Test Circuit

tp

V

(BR)DSS

I

AS

RG

IAS

0.01

Ω

tp

D.U.T

L

VDS

+

- VDD

DRIVER

A

15V

20V

V

GS

Fig 25a.  Gate Charge Test Circuit

Fig 25b.   Gate Charge Waveform

Vds

Vgs

Id

Vgs(th)

Qgs1 Qgs2

Qgd

Qgodr

Fig 22. 

Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET

®

 Power MOSFETs

Circuit Layout Considerations

   •  Low Stray Inductance

   •  Ground Plane

   •  Low Leakage Inductance

      Current Transformer

P.W.

Period

di/dt

Diode Recovery

dv/dt

Ripple 

≤ 5%

Body Diode  Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

V

GS

=10V

V

DD

I

SD

Driver Gate Drive

D.U.T. I

SD

Waveform

D.U.T. V

DS

Waveform

Inductor Curent

D = 

P.W.

Period

*

 V

GS

 = 5V for Logic Level Devices

*

+

-

+

+

+

-

-

-

ƒ

„

‚

R

G

V

DD

•  dv/dt controlled by R

G

•  Driver same type as D.U.T.

•  I

SD

 controlled by Duty Factor "D"

•  D.U.T. - Device Under Test

D.U.T



Inductor Current

D.U.T.

V

DS

I

D

I

G

3mA

V

GS

.3

μF

50K

Ω

.2

μF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

+

-

V

DS

90%

10%
V

GS

t

d(on)

t

r

t

d(off)

t

f

V

DS

Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

R

D

V

GS

R

G

D.U.T.

10V

+

-

V

DD

V

GS

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IRFR7446PbF

  

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D-Pak (TO-252AA) Part Marking Information

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

INTERNATIONAL

ASSEMBLED ON WW 16, 2001
IN THE ASSEMBLY LINE "A"

OR

Note: "P" in assembly line position

EXAMPLE:

LOT CODE 1234

THIS IS AN IRFR120
WITH ASSEMBLY

indicates "Lead-Free"

PRODUCT (OPTIONAL)

P =  DESIGNATES LEAD-FREE

A =  ASSEMBLY SITE CODE

PART NUMBER

WEEK 16

DATE CODE
YEAR 1 =  2001

RECTIFIER

INTERNATIONAL

LOGO

LOT CODE

ASSEMBLY

34

12

IRFR120

116A

LINE A

34

RECTIFIER

LOGO

IRFR120

12

ASSEMBLY

LOT CODE

YEAR 1 =  2001

DATE CODE

PART NUMBER

WEEK 16

"P" in assembly line position indicates

"Lead-Free" qualification to the consumer-level

P =  DESIGNATES LEAD-FREE

PRODUCT QUALIFIED TO THE

CONSUMER LEVEL (OPTIONAL)

Note: For the most current drawing please refer to IR website at: 

http://www.irf.com/package/

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IRFR7446PbF

  

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D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TR

16.3 ( .641 )
15.7 ( .619 )

8.1 ( .318 )
7.9 ( .312 )

12.1 ( .476 )
11.9 ( .469 )

FEED DIRECTION

FEED DIRECTION

16.3 ( .641 )
15.7 ( .619 )

TRR

TRL

NOTES :
1.  CONTROLLING DIMENSION : MILLIMETER.
2.  ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3.  OUTLINE CONFORMS TO EIA-481 & EIA-541.

NOTES :
1. OUTLINE CONFORMS TO EIA-481.

16 mm

  13 INCH

Note: For the most current drawing please refer to IR website at: 

http://www.irf.com/package/

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background image

Fig 1.   Typical On-Resistance vs. Gate Voltage

Fig 2.  Maximum Drain Current vs. Case Temperature

HEXFET

®

 Power MOSFET

Benefits

l

Improved  Gate, Avalanche and Dynamic  dV/dt
Ruggedness

l

Fully Characterized Capacitance and Avalanche

     SOA

l

Enhanced body diode dv/dt and dI/dt Capability

Lead-Free

G

D

S

Gate

Drain

Source

Applications

Brushed Motor drive applications

BLDC Motor drive applications

PWM Inverterized topologies

Battery powered circuits

Half-bridge and full-bridge topologies

Synchronous rectifier applications

Resonant mode power supplies

OR-ing and redundant power switches

DC/DC and AC/DC converters

D-Pak

IRFR7446TRPbF

G

S

D

25

50

75

100

125

150

175

 TC,  Case Temperature (°C)

0

20

40

60

80

100

120

I D

,  

D

ra

in

 C

ur

re

nt

 (

A

)

LIMITED BY PACKAGE

4

8

12

16

20

VGS, Gate-to-Source Voltage (V)

2

4

6

8

10

R

D

S

(o

n)

,  

D

ra

in

-t

-S

ou

rc

O

R

es

is

ta

nc

(m

Ω

)

TJ = 25°C

TJ = 125°C

ID = 56A

Ordering Information

Form

Quantity

IRFR7446PBF

D-PAK

Tube/Bulk

75

IRFR7446PBF

IRFR7446TRPBF

D-PAK

Tape and Reel

2000

IRFR7446TRPBF

Orderable part number

Package Type

Standard Pack

Complete Part Number

D

S

G

V

DSS

40V

R

DS(on)

   typ.

3.0mΩ

              max.

3.9m

Ω

I

(Silicon Limited)

120Ac

I

(Package Limited)

56A 

Strong

IR

FET™

IRFR7446PbF

  

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Notes:



Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 56A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)

‚

Repetitive rating;  pulse width limited by max. junction
temperature.

ƒ

Limited by T

Jmax

, starting T

= 25°C, L = 0.08mH

R

= 50

Ω, I

AS 

= 56A, V

GS

 =10V.

„

I

SD 

≤ 100A, di/dt ≤ 1306A/μs, V

DD 

≤ V

(BR)DSS

, T

≤ 175°C.

…

Pulse width 

≤ 400μs; duty cycle ≤ 2%.

†

C

oss

 eff. (TR) is a fixed capacitance that gives the same charging time

as C

oss 

while V

DS 

is rising from 0 to 80% V

DSS

.

‡

C

oss

 eff. (ER) is a fixed capacitance that gives the same energy as

C

oss 

while V

DS 

is rising from 0 to 80% V

DSS

.

ˆ

When mounted on 1" square PCB (FR-4 or G-10 Material).  For recom
mended footprint and soldering techniques refer to application note #AN-994.

‰

R

θ 

is measured at T

J

 approximately 90°C.

Š

Limited by T

Jmax 

starting

 

T

= 25°C, L= 1mH, R

= 50

Ω, I

AS 

= 22A, V

GS

 =10V.

*

L

D

 and L

S

 are Internal Drain Inductance and Internal Source Inductance

Static @ T

J

 = 25°C (unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Units

V

(BR)DSS

Drain-to-Source Breakdown Voltage

40

–––

–––

V

ΔV

(BR)DSS

/

ΔT

Breakdown Voltage Temp. Coefficient

–––

26

–––

mV/°C

R

DS(on)

Static Drain-to-Source On-Resistance

–––

3.0

3.9

m

Ω

4.4

–––

V

GS(th)

Gate Threshold Voltage

2.2

3.0

3.9

V

I

DSS

Drain-to-Source Leakage Current

–––

–––

1.0

μA

–––

–––

150

I

GSS

Gate-to-Source Forward Leakage

–––

–––

100

nA

Gate-to-Source Reverse Leakage

–––

–––

-100

R

G

Internal Gate Resistance

–––

1.5

–––

Ω

V

GS

 = 20V

V

GS

 = -20V

V

GS

 = 6.0V, I

D

 = 28A 

g

V

DS

 = V

GS

, I

D

 = 100μA

Conditions

V

GS

 = 0V, I

D

 = 250μA

d

Reference to 25°C, I

D

 = 1mA

V

GS

 = 10V, I

D

 = 56A 

g

V

DS

 = 40V, V

GS

 = 0V

V

DS

 = 40V, V

GS

 = 0V, T

J

 = 125°C

Absolute Maximum Ratings

Symbol

Parameter

Units

I

D

 @ T

C

 = 25°C

Continuous Drain Current, V

GS

 @ 10V (Silicon Limited)

I

D

 @ T

C

 = 100°C

Continuous Drain Current, V

GS

 @ 10V (Silicon Limited)

I

D

 @ T

C

 = 25°C

Continuous Drain Current, V

GS

 @ 10V (Wire Bond Limited)

I

DM

Pulsed Drain Current 

d

P

D

 @T

C

 = 25°C

Maximum Power Dissipation  

W

Linear Derating Factor

W/°C

V

GS

Gate-to-Source Voltage

V

T

Operating Junction and

T

STG

Storage Temperature Range

Soldering Temperature, for 10 seconds (1.6mm from case)

Avalanche Characteristics

E

AS (Thermally limited) 

Single Pulse Avalanche Energy 

e

E

AS (Thermally limited) 

Single Pulse Avalanche Energy  

l

I

AR

Avalanche Current 

d

A

E

AR

Repetitive Avalanche Energy 

d

mJ

Thermal Resistance

Symbol

Parameter

Typ.

Max.

Units

R

θJC 

Junction-to-Case 

k

–––

1.52

R

θJA 

–––

50

R

θJA 

Junction-to-Ambient 

k

–––

110

251

 ± 20

0.66

Max.

120

c

84

c

520

56

mJ

-55  to + 175

See Fig 15,16, 23a, 23b

Junction-to-Ambient (PCB Mount) 

j

A

°C

300

98

125

°C/W

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S

D

G

Dynamic @ T

J

 = 25°C (unless otherwise specified)

Symbol

Parameter

Min. Typ. Max. Units

gfs

Forward Transconductance

170

–––

–––

S

Q

g

Total Gate Charge

–––

65

130

nC

Q

gs

Gate-to-Source Charge

–––

18

–––

Q

gd

Gate-to-Drain ("Miller") Charge

–––

22

–––

Q

sync

Total Gate Charge Sync. (Q

g

 - Q

gd

)

–––

43

–––

t

d(on)

Turn-On Delay Time

–––

9.8

–––

ns

t

r

Rise Time

–––

13

–––

t

d(off)

Turn-Off Delay Time

–––

32

–––

t

f

Fall Time

–––

20

–––

C

iss

Input Capacitance

–––

3150

–––

pF

C

oss

Output Capacitance

–––

480

–––

C

rss

Reverse Transfer Capacitance

–––

330

–––

C

oss

 eff. (ER) Effective Output Capacitance (Energy Related) 

–––

570

–––

C

oss

 eff. (TR) Effective Output Capacitance (Time Related)

–––

680

–––

Diode Characteristics

Symbol

        Parameter

Min. Typ. Max. Units

I

S

Continuous Source Current 

–––

––– 120c

A

(Body Diode)

I

SM

Pulsed Source Current

–––

–––

480

A

(Body Diode)

d

V

SD

Diode Forward Voltage

–––

0.9

1.3

V

dv/dt

Peak Diode Recovery f

–––

4.8

–––

V/ns

t

rr

Reverse Recovery Time

–––

20

–––

ns

T

J

 = 25°C

V

R

 = 34V,

–––

21

–––

T

J

 = 125°C

I

F

 = 56A

Q

rr

Reverse Recovery Charge

–––

13

–––

nC T

J

 = 25°C

di/dt = 100A/μs g

–––

13

–––

T

J

 = 125°C

I

RRM

Reverse Recovery Current

–––

1.8

–––

A

T

J

 = 25°C

t

on

Forward Turn-On Time

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 

*

T

J

 = 25°C, I

S

 = 56A, V

GS

 = 0V 

Conditions

V

GS

 = 10V g

V

GS

 = 0V

V

DS

 = 25V

ƒ = 1.0 MHz,  See Fig. 5
V

GS

 = 0V, V

DS

 = 0V to 32V 

i  See Fig. 12

V

GS

 = 0V, V

DS

 = 0V to 32V 

h

V

GS

 = 10V

g

V

DD

 = 20V

I

D

 = 56A, V

DS

 =0V, V

GS

 = 10V

T

J

 = 175°C, I

S

 = 56A, V

DS

 = 40V g

integral reverse
p-n junction diode.

MOSFET symbol
showing  the

I

D

 = 30A

R

G

 = 2.7Ω

Conditions

V

DS

 = 10V, I

D

 = 56A

I

D

 =56A

V

DS

 =20V

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Fig 3.  Typical Output Characteristics

Fig 5.  Typical Transfer Characteristics

Fig 6.  Normalized On-Resistance vs. Temperature

Fig 4.  Typical Output Characteristics

Fig 8.  Typical Gate Charge vs. Gate-to-Source Voltage

Fig 7.  Typical Capacitance vs. Drain-to-Source Voltage

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.1

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

≤ 60μs PULSE WIDTH

Tj = 25°C

4.3V

VGS

TOP          

15V

10V

7.0V

6.0V

5.5V

5.0V

4.5V

BOTTOM

4.3V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

≤ 60μs PULSE WIDTH

Tj = 175°C

4.3V

VGS

TOP          

15V

10V

7.0V

6.0V

5.5V

5.0V

4.5V

BOTTOM

4.3V

2.0

3.0

4.0

5.0

6.0

7.0

8.0

VGS, Gate-to-Source Voltage (V)

0.1

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

VDS = 10V
≤ 60μs PULSE WIDTH

TJ = 25°C

TJ = 175°C

1

10

100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

100000

C

, C

ap

ac

ita

nc

(p

F

)

Coss

Crss

Ciss

VGS   = 0V,       f = 1 MHZ

Ciss   = Cgs + Cgd,  Cds SHORTED
Crss   = Cgd 
Coss  = Cds + Cgd

0

20

40

60

80

100

 QG  Total Gate Charge (nC)

0

4

8

12

16

V

G

S

, G

at

e-

to

-S

ou

rc

V

ol

ta

ge

 (

V

)

VDS= 32V

VDS= 20V

ID= 56A

-60 -40 -20 0

20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

R

D

S

(o

n)

 , 

D

ra

in

-t

o-

S

ou

rc

O

R

es

is

ta

nc

   

   

   

   

   

   

   

 (

N

or

m

al

iz

ed

)

ID = 56A

VGS = 10V

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Fig 10.  Maximum Safe Operating Area

Fig 11.  Drain-to-Source Breakdown Voltage

Fig 9.  Typical Source-Drain Diode

Forward Voltage

Fig 12.  Typical C

OSS

 Stored Energy

Fig 13.   Typical On-Resistance vs. Drain Current

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

VSD, Source-to-Drain Voltage (V)

0.1

1

10

100

1000

I S

D

, R

ev

er

se

 D

ra

in

 C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 175°C

VGS = 0V

-60 -40 -20 0 20 40 60 80 100120140160180

TJ , Temperature ( °C )

40

41

42

43

44

45

46

47

48

49

V

(B

R

)D

S

S

,  

D

ra

in

-t

o-

S

ou

rc

B

re

ak

do

w

V

ol

ta

ge

 (

V

)

Id = 1.0mA

0

10

20

30

40

VDS, Drain-to-Source Voltage (V)

0.0

0.1

0.2

0.3

0.4

E

ne

rg

J)

0

20 40 60 80 100 120 140 160 180 200

ID, Drain Current (A)

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

R

D

S

(o

n)

,  

D

ra

in

-t

-S

ou

rc

O

R

es

is

ta

nc

(m

Ω

)

VGS = 5.5V

VGS = 6.0V

VGS = 7.0V

VGS = 8.0V

VGS =10V

0.1

1

10

VDS,  Drain-toSource Voltage (V)

0.1

1

10

100

1000

I D

,  

D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

100μsec

DC

L

imited by Package

OPERATION IN THIS AREA 
LIMITED BY RDS(on)

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Fig 14.  Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 15.  Typical Avalanche Current vs.Pulsewidth

Fig 16.  Maximum Avalanche Energy vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T

jmax

. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT

jmax

 is not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 23a, 23b.
4. P

D (ave) 

= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

during avalanche).

6. I

av 

= Allowable avalanche current.

7. 

ΔT

 = 

Allowable rise in junction temperature, not to exceed

 

T

jmax 

(assumed as

25°C in Figure 14, 15).
t

av = 

Average time in avalanche.

D = Duty cycle in avalanche =  t

av 

·f

Z

thJC

(D, t

av

) = Transient thermal resistance, see Figures 14)

P

D (ave)

 = 1/2 ( 1.3·BV·I

av

) =

 DT/ Z

thJC

I

av 

=

 

2

DT/ [1.3·BV·Z

th

]

E

AS (AR)

 = P

D (ave)

·t

av

1E-006

1E-005

0.0001

0.001

0.01

0.1

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

1

10

T

he

rm

al

 R

es

po

ns

Z  

th

JC

 )

 °

C

/W

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

25

50

75

100

125

150

175

Starting TJ , Junction Temperature (°C)

0

20

40

60

80

100

120

140

E

A

R

 ,

 A

va

la

nc

he

 E

ne

rg

(m

J)

TOP          Single Pulse                
BOTTOM   1.0% Duty Cycle
ID = 56A

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

0.1

1

10

100

A

va

la

nc

he

 C

ur

re

nt

 (

A

)

Allowed avalanche Current vs avalanche 
pulsewidth, tav, assuming ΔΤ j = 25°C and 

Tstart = 150°C.

Allowed avalanche Current vs avalanche 
pulsewidth, tav, assuming ΔTj = 150°C and 

Tstart =25°C (Single Pulse)

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Fig. 18 - Typical Recovery Current vs. di

f

/dt

Fig 17.  Threshold Voltage vs. Temperature

Fig. 20 - Typical Stored Charge vs. di

f

/dt

Fig. 19 - Typical Recovery Current vs. di

f

/dt

Fig. 21 - Typical Stored Charge vs. di

f

/dt

-75 -50 -25

0

25

50

75 100 125 150 175

TJ , Temperature ( °C )

1.5

2.0

2.5

3.0

3.5

4.0

4.5

V

G

S

(t

h)

 G

at

th

re

sh

ol

V

ol

ta

ge

 (

V

)

ID =50μA

ID = 250μA

ID = 1.0mA

ID = 1.0A

0

200

400

600

800

1000

diF /dt (A/μs)

0

2

4

6

I R

R

M

 (

A

)

IF = 34A
VR = 34V
TJ = 25°C
TJ = 125°C

0

200

400

600

800

1000

diF /dt (A/μs)

0

2

4

6

I R

R

M

 (

A

)

IF = 56A
VR = 34V
TJ = 25°C
TJ = 125°C

0

200

400

600

800

1000

diF /dt (A/μs)

0

20

40

60

80

Q

R

R

 (

nC

)

IF = 34A
VR = 34V
TJ = 25°C
TJ = 125°C

0

200

400

600

800

1000

diF /dt (A/μs)

0

20

40

60

80

Q

R

R

 (

nC

)

IF = 56A
VR = 34V
TJ = 25°C
TJ = 125°C

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Fig 24a.  Switching Time Test Circuit

Fig 24b.  Switching Time Waveforms

Fig 23b.  Unclamped Inductive Waveforms

Fig 23a.  Unclamped Inductive Test Circuit

tp

V

(BR)DSS

I

AS

RG

IAS

0.01

Ω

tp

D.U.T

L

VDS

+

- VDD

DRIVER

A

15V

20V

V

GS

Fig 25a.  Gate Charge Test Circuit

Fig 25b.   Gate Charge Waveform

Vds

Vgs

Id

Vgs(th)

Qgs1 Qgs2

Qgd

Qgodr

Fig 22. 

Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET

®

 Power MOSFETs

Circuit Layout Considerations

   •  Low Stray Inductance

   •  Ground Plane

   •  Low Leakage Inductance

      Current Transformer

P.W.

Period

di/dt

Diode Recovery

dv/dt

Ripple 

≤ 5%

Body Diode  Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

V

GS

=10V

V

DD

I

SD

Driver Gate Drive

D.U.T. I

SD

Waveform

D.U.T. V

DS

Waveform

Inductor Curent

D = 

P.W.

Period

*

 V

GS

 = 5V for Logic Level Devices

*

+

-

+

+

+

-

-

-

ƒ

„

‚

R

G

V

DD

•  dv/dt controlled by R

G

•  Driver same type as D.U.T.

•  I

SD

 controlled by Duty Factor "D"

•  D.U.T. - Device Under Test

D.U.T



Inductor Current

D.U.T.

V

DS

I

D

I

G

3mA

V

GS

.3

μF

50K

Ω

.2

μF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

+

-

V

DS

90%

10%
V

GS

t

d(on)

t

r

t

d(off)

t

f

V

DS

Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

R

D

V

GS

R

G

D.U.T.

10V

+

-

V

DD

V

GS

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D-Pak (TO-252AA) Part Marking Information

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

INTERNATIONAL

ASSEMBLED ON WW 16, 2001
IN THE ASSEMBLY LINE "A"

OR

Note: "P" in assembly line position

EXAMPLE:

LOT CODE 1234

THIS IS AN IRFR120
WITH ASSEMBLY

indicates "Lead-Free"

PRODUCT (OPTIONAL)

P =  DESIGNATES LEAD-FREE

A =  ASSEMBLY SITE CODE

PART NUMBER

WEEK 16

DATE CODE
YEAR 1 =  2001

RECTIFIER

INTERNATIONAL

LOGO

LOT CODE

ASSEMBLY

34

12

IRFR120

116A

LINE A

34

RECTIFIER

LOGO

IRFR120

12

ASSEMBLY

LOT CODE

YEAR 1 =  2001

DATE CODE

PART NUMBER

WEEK 16

"P" in assembly line position indicates

"Lead-Free" qualification to the consumer-level

P =  DESIGNATES LEAD-FREE

PRODUCT QUALIFIED TO THE

CONSUMER LEVEL (OPTIONAL)

Note: For the most current drawing please refer to IR website at: 

http://www.irf.com/package/

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D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TR

16.3 ( .641 )
15.7 ( .619 )

8.1 ( .318 )
7.9 ( .312 )

12.1 ( .476 )
11.9 ( .469 )

FEED DIRECTION

FEED DIRECTION

16.3 ( .641 )
15.7 ( .619 )

TRR

TRL

NOTES :
1.  CONTROLLING DIMENSION : MILLIMETER.
2.  ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3.  OUTLINE CONFORMS TO EIA-481 & EIA-541.

NOTES :
1. OUTLINE CONFORMS TO EIA-481.

16 mm

  13 INCH

Note: For the most current drawing please refer to IR website at: 

http://www.irf.com/package/

Maker
Infineon Technologies