IRFHM8235PBF Product Datasheet

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IRFHM8235PbF 

HEXFET

® 

Power MOSFET 

Base part number  

Package Type  

Standard Pack 

Form 

Quantity 

IRFHM8235PbF 

PQFN 3.3 mm x 3.3 mm 

Tape and Reel 

4000 

IRFHM8235TRPbF 

Orderable Part Number   

V

DSS 

25 

R

DS(on) 

max 

(@ V

GS 

= 10V) 

7.7

(@ V

GS 

= 4.5V) 

13.4 

Qg

 (typical) 

7.7

nC 

I

D  

(@T

C (Bottom)

 = 25°C) 

25 A 

m



V

GS 

max

 

±20 

Features 

 

Benefits 

Low Thermal Resistance to PCB (<4.1°C/W) 

 

Enable better Thermal Dissipation 

Low Profile (<1.05mm)         

 

Increased Power Density 

Industry-Standard Pin out     

results in Multi-Vendor Compatibility 

Compatible with Existing Surface Mount Techniques                                              



Easier Manufacturing 

RoHS Compliant, Halogen-Free 

 

Environmentally Friendlier 

MSL1, Consumer Qualification 

 

Increased Reliability 

Notes  through  are on page 10 

Absolute Maximum Ratings 

 

 

 

  

Parameter Max. 

Units 

V

GS 

Gate-to-Source Voltage 

 ± 20 

I

D

 @ T

A

 = 25°C 

Continuous Drain Current, V

GS

 @ 10V 

16 

I

D

 @ T

C(Bottom)

 = 25°C 

Continuous Drain Current, V

GS

 @ 10V  

50 

I

D

 @ T

C(Bottom)

 = 100°C 

Continuous Drain Current, V

GS

 @ 10V  

32 

I

DM 

Pulsed Drain Current  240 

P

D

 @T

A

 = 25°C 

Power Dissipation  3.0 

P

D

 @T

C(Bottom)

 = 25°C 

Power Dissipation  30 

  

Linear Derating Factor  0.024 

W/°C 

T

J  

Operating Junction and 

-55  to + 150 

°C 

T

STG 

Storage Temperature Range 

  

I

D

 @ T

A

 = 70°C 

Continuous Drain Current, V

GS

 @ 10V 

13 

I

D

 @ T

C

 = 25°C 

Continuous Drain Current, V

GS

 @ 10V  

(Source Bonding Technology Limited) 

25 

Applications  


Control MOSFET for synchronous buck converter 

 

PQFN 3.3X3.3 mm 

 

 

2016-2-23 

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IRFHM8235PbF 

 

2016-2-23 

Thermal Resistance  

 

 

 

  

Parameter Typ. 

Max. 

Units 

R

JC

 (Bottom)  Junction-to-Case  ––– 

4.1 

R

JC

 (Top) 

Junction-to-Case  ––– 

42 

R

JA

  

Junction-to-Ambient  ––– 

42 

R

JA

 (<10s) 

Junction-to-Ambient  ––– 

28 

  °C/W     

Avalanche Characteristics 

 

 

 

 

 

 

 

  

Parameter  

 

Typ. 

Max. 

Units 

E

AS 

Single Pulse Avalanche Energy   

  ––– 

41 

mJ 

D

S

G

Static @ T

J

 = 25°C (unless otherwise specified) 

 

 

 

 

 

  

Parameter Min. 

Typ. 

Max. 

Units 

Conditions 

BV

DSS 

Drain-to-Source Breakdown Voltage 

25 

––– 

––– 

V

GS

 = 0V, I

D

 = 250µA 

BV

DSS

/

T

J  

Breakdown Voltage Temp. Coefficient 

––– 

19 

–––  mV/°C  Reference to 25°C, I

D

 = 1.0mA  

R

DS(on) 

Static Drain-to-Source On-Resistance 

––– 

6.2 

7.7 

m

 

V

GS

 = 10V, I

D

 = 20A  

  

  

––– 10.3 13.4 

V

GS

 = 4.5V, I

D

 = 16A  

V

GS(th) 

Gate Threshold Voltage 

1.35 

1.8 

2.35 

V

DS

 = V

GS

, I

D

 = 25µA   

V

GS(th) 

Gate Threshold Voltage Coefficient 

––– 

-5.9 

–––  mV/°C 

I

DSS 

Drain-to-Source Leakage Current 

––– 

––– 

1.0 

µA  

V

DS

 = 20V, V

GS

 = 0V 

 

 

––– ––– 150 

V

DS

 = 20V, V

GS

 = 0V, T

J

 = 125°C 

I

GSS 

Gate-to-Source Forward Leakage 

––– 

––– 

100 

nA 

V

GS

 = 20V 

  

Gate-to-Source Reverse Leakage 

––– 

––– 

-100 

V

GS

 = -20V 

gfs Forward 

Transconductance 

43 

––– 

––– 

V

DS

 = 10V, I

D

 = 20A 

Q

Total Gate Charge  

––– 

16 

––– 

nC  V

GS

 = 10V, V

DS

 = 13V, I

D

 = 20A  

Q

Total Gate Charge  

––– 

7.7 

12 

nC  

  

Q

gs1 

Pre-Vth Gate-to-Source Charge 

––– 

1.9 

––– 

V

DS

 = 13V 

Q

gs2 

Post-Vth Gate-to-Source Charge 

––– 

1.3 

––– 

V

GS

 = 4.5V  

Q

gd 

Gate-to-Drain Charge 

––– 

2.7 

––– 

I

D

 = 20A 

Q

godr 

Gate Charge Overdrive 

––– 

1.5 

––– 

  

Q

sw 

Switch Charge (Q

gs2

 + Q

gd

) ––– 

4.0 

––– 

  

Q

oss 

Output Charge 

––– 

6.4 

––– 

nC  V

DS

 = 16V, V

GS

 = 0V 

R

Gate Resistance 

––– 

1.6 

––– 

 

  

t

d(on) 

Turn-On Delay Time 

––– 

7.9 

––– 

ns  

V

DD

 = 13V, V

GS

 = 4.5V 

t

Rise Time 

––– 

16 

––– 

I

D

 = 20A 

t

d(off) 

Turn-Off Delay Time 

––– 

7.5 

––– 

R

G

=1.8

 

t

Fall Time 

––– 

5.2 

––– 

  

C

iss 

Input Capacitance 

––– 

1040 

––– 

V

GS

 = 0V 

C

oss 

Output Capacitance 

––– 

300 

––– 

V

DS

 = 10V 

C

rss 

Reverse Transfer Capacitance 

––– 

120 

––– 

ƒ = 1.0MHz 

pF  

Diode Characteristics 

 

 

 

 

 

 

 

  

        Parameter 

Min.  Typ.  Max.  Units 

Conditions 

I

Continuous Source Current  

––– ––– 25 

MOSFET symbol 

  

(Body Diode) 

showing  the 

I

SM 

Pulsed Source Current 

––– ––– 240 

integral reverse 

  

(Body Diode)  

p-n junction diode. 

V

SD 

Diode Forward Voltage 

–––  –––  1.0 

V  T

J

 = 25°C, I

S

 = 20A, V

GS

 = 0V  

t

rr 

Reverse Recovery Time 

––– 

10 

15 

ns  T

J

 = 25°C, I

F

 = 20A, V

DD

 = 13V 

Q

rr 

Reverse Recovery Charge 

–––  4.9 

7.4 

nC  di/dt = 300A/µs   

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IRFHM8235PbF 

 

2016-2-23 

Fig 1.  Typical Output Characteristics 

Fig 4.  Normalized On-Resistance vs. Temperature 

Fig 5.  Typical Capacitance vs. Drain-to-Source Voltage 

Fig 6.  Typical Gate Charge vs. Gate-to-Source Voltage 

Fig 3.  Typical Transfer Characteristics 

Fig 2.  Typical Output Characteristics 

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.01

0.1

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

VGS

TOP          

10V
7.0V
4.5V
4.0V
3.5V
3.0V
2.8V

BOTTOM

2.5V

60µs PULSE WIDTH

Tj = 25°C

2.5V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.1

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

u

rr

e

nt

 (

A

)

2.5V

60µs PULSE WIDTH

Tj = 150°C

VGS

TOP          

10V
7.0V
4.5V
4.0V
3.5V
3.0V
2.8V

BOTTOM

2.5V

1.0

2.5

4.0

5.5

7.0

8.5

10.0 11.5

VGS, Gate-to-Source Voltage (V)

0.1

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

e

 C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 150°C

VDS = 10V
60µs PULSE WIDTH

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ , Junction Temperature (°C)

0.6

0.8

1.0

1.2

1.4

1.6

R

D

S

(o

n)

 , 

D

ra

in

-t

o-

S

ou

rc

O

R

es

is

ta

nc

   

   

   

   

   

   

  

  (

N

or

m

al

iz

ed

)

ID = 20A
VGS = 10V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

10

100

1000

10000

C

, C

ap

ac

ita

nc

(p

F

)

VGS   = 0V,       f = 1 MHZ

Ciss    = Cgs + Cgd,  Cds SHORTED
Crss   = Cgd 
Coss   = Cds + Cgd

Coss

Crss

Ciss

0

2

4

6

8

10 12 14 16 18 20

 QG,  Total Gate Charge (nC)

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

V

G

S

, G

a

te

-t

o-

S

ou

rc

V

ol

ta

ge

 (

V

)

VDS= 20V
VDS= 13V
VDS= 5.0V

ID= 20A

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IRFHM8235PbF 

 

2016-2-23 

Fig 8.  Maximum Safe Operating Area  

Fig 11.  Maximum Effective Transient Thermal Impedance, Junction-to-Case  

Fig 7.  Typical Source-Drain Diode Forward Voltage 

Fig 9.  Maximum Drain Current vs. Case Temperature 

Fig 10.  

Threshold Voltage Vs. Temperature 

0.0

0.5

1.0

1.5

2.0

2.5

VSD, Source-to-Drain Voltage (V)

0.1

1

10

100

1000

I S

D

, R

ev

er

se

 D

ra

in

 C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 150°C

VGS = 0V

-75 -50 -25

0

25

50

75 100 125 150

TJ , Temperature ( °C )

0.8

1.2

1.6

2.0

2.4

2.8

V

G

S

(t

h)

,  

G

at

th

re

sh

ol

d

 V

ol

ta

ge

 (

V

)

ID = 25µA
ID = 250µA
ID = 1.0mA
ID = 1.0A

1E-006

1E-005

0.0001

0.001

0.01

0.1

1

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

1

10

T

he

rma

l R

es

p

on

se

 (

 Z  

th

JC

 ) 

°C

/W

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE
( THERMAL RESPONSE )

Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.01

0.1

1

10

100

1000

I D

,  

D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

Tc = 25°C

Tj = 150°C

Single Pulse

10msec

1msec

OPERATION IN THIS AREA 
LIMITED BY RDS(on)

100µsec

DC

Limited by source 

bonding technology 

25

50

75

100

125

150

 TC , Case Temperature (°C)

0

11

22

33

44

55

I D

 ,

 D

ra

in

 C

ur

re

nt

 (

A

)

Limited by source 

bonding technology 

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IRFHM8235PbF 

 

2016-2-23 

Fig 12.  On-Resistance vs. Gate Voltage 

Fig 13.  Maximum Avalanche Energy vs. Drain Current 

Fig 14. Single avalanche event: pulse current vs. pulse width  

2

4

6

8

10

12

14

16

18

20

VGS, Gate -to -Source Voltage  (V)

0.0

4.0

8.0

12.0

16.0

20.0

24.0

R

D

S

(o

n

), 

 D

ra

in

-t

-S

ou

rc

O

R

e

si

st

an

ce

 (

m

)

ID = 20A

TJ = 25°C

TJ = 125°C

25

50

75

100

125

150

Starting TJ , Junction Temperature (°C)

0

20

40

60

80

100

120

140

160

180

E

A

S

 ,

 S

in

gl

e

 P

ul

se

 A

va

la

nc

he

 E

ne

rg

(m

J)

ID

TOP         4.0A

8.6A

BOTTOM 20A

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

0.1

1

10

100

A

va

la

nc

he

 C

ur

re

nt

 (

A

)

Allowed avalanche Current vs avalanche 
pulsewidth, tav, assuming 

 j = 25°C and 

Tstart = 125°C.

Allowed avalanche Current vs avalanche 
pulsewidth, tav, assuming 

Tj = 125°C and 

Tstart =25°C (Single Pulse)

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IRFHM8235PbF 

 

2016-2-23 

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET

® 

Power MOSFETs 

Fig 18a. Gate Charge Test Circuit 

Vds

Vgs

Id

Vgs(th)

Qgs1 Qgs2

Qgd

Qgodr

Fig 18b. Gate Charge Waveform 

Fig 16a.  Unclamped Inductive Test Circuit 

R G

I

AS

0.01

tp

D.U.T

L

VDS

+

- VDD

DRIVER

A

15V

20V

tp

V

(BR)DSS

I

AS

Fig 16b.  Unclamped Inductive Waveforms 

Fig 17a.  Switching Time Test Circuit 

Fig 17b.  Switching Time Waveforms 

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IRFHM8235PbF 

 

2016-2-23 

The typical application topology for this product is the synchronous buck converter. These converters operate at high 
frequencies (typically around 400 kHz). During turn-on and turn-off switching cycles, the high di/dt currents circulating 
in the parasitic elements of the circuit induce high voltage ringing which may exceed the device rating and lead to un-
desirable effects. One of the major contributors to the increase in parasitics is the PCB power circuit inductance.  
 
This section introduces a simple guideline that mitigates the effect of these parasitics on the performance of the circuit 
and provides reliable operation of the devices. 
 
To reduce high frequency switching noise and the effects of Electromagnetic Interference (EMI) when the control 
MOSFET (Q1) is turned on, the layout shown in Figure 19 is recommended. The input bypass capacitors, control 
MOSFET and output capacitors are placed in a tight loop to minimize parasitic inductance which in turn lowers the am-
plitude of the switch node ringing, and minimizes exposure of the MOSFETs to repetitive avalanche conditions.  
 
When the synchronous MOSFET (Q2) is turned on, high average DC current flows through the path indicated in Figure 
19. Therefore, the Q2 turn-on path should be laid out with a tight loop and wide traces at both ends of the inductor to 
minimize loop resistance. 

Placement and Layout Guidelines 

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IRFHM8235PbF 

 

2016-2-23 

For more information on board mounting, including footprint and stencil recommendation, please refer to application note 
AN-1136: 

http://www.irf.com/technical-info/appnotes/an-1136.pdf

 

For more information on package inspection techniques, please refer to application note AN-1154: 

http://www.irf.com/technical-info/appnotes/an-1154.pdf

 

PQFN 3.3 x 3.3 Outline “C” Package Details 

PQFN 3.3 x 3.3 Outline “G” Package Details 

5

8

7

6

#1

3

2

4

#1

2

3

4

8

7

6

5

5

8

7

6

1

3

2

4

1

2

3

4

8

7

6

5

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IRFHM8235PbF 

 

2016-2-23 

PQFN 3.3mm x 3.3mm Outline Tape and Reel 

Note: For the most current drawing please refer to IR website at 

http://www.irf.com/package/

 

Bo

W

P1

Ao

Ko

CODE

TAPE DIMENSIONS

REEL DIMENSIONS

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE 

Dimension design to accommodate the component width
Dimension design to accommodate the component lenght
Dimension design to accommodate the component thickness

Pitch between successive cavity centers

Overall width of the carrier tape

Bo

W

P1

Ao

Ko

DIMENSION (MM)

CODE

MIN

MAX

DIMENSION (INCH)

MIN

MAX

3.50

3.70

.138

.146

1.10

1.30

7.90

8.10

.043

.051

11.80

12.20

.311

.319

12.30

12.50

.465

.480

.484

.492

3.50

3.70

.138

.146

DESCRIPTION

W1

Qty

4000

Reel Diameter

13   Inches

 

 

 

PQFN 3.3mm x 3.3mm Outline Part Marking 

 

Note: For the most current drawing please refer to IR website at 

http://www.irf.com/package/

 

XXXX

?YWW?

XXXXX

INTERNATIONAL

RECTIFIER LOGO

PART NUMBER

MARKING CODE

(Per Marking Spec)

ASSEMBLY
SITE CODE

(Per SCOP 200-002)

DATE CODE

LOT CODE

(Eng Mode - Min last 4 digits of EATI#)

(Prod Mode - 4 digits of SPN code)

PIN 1

IDENTIFIER

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IRFHM8235PbF 

10 

 

2016-2-23 

Qualification Information

† 

 

Qualification Level 

Moisture Sensitivity Level  

PQFN 3.3mm x 3.3mm 

MSL1 

(per JEDEC J-STD-020D

†††

RoHS Compliant 

Yes 

Consumer

†† 

(per JEDEC JESD47F guidelines) 

† 

Qualification standards can be found at International Rectifier’s web site: 

http://www.irf.com/product-info/reliability/

 

††   Higher qualification ratings may be available should the user have such requirements.  Please contact your 
 

International Rectifier sales representative for further information: 

http://www.irf.com/whoto-call/salesrep/

 

†††  Applicable version of JEDEC standard at the time of product release.

 

Notes:

  

Repetitive rating;  pulse width limited by max. junction temperature. 

   

Starting T

J

 = 25°C, L = 0.21mH, R

G

 = 50

, I

AS

 = 20A.  

 

Pulse width 

 400µs; duty cycle  2%. 

   R

 is measured at T

J

 of approximately 90°C. 

  

When mounted on 1 inch square  2 oz copper pad on 1.5x1.5 in. board of FR-4 material. Please refer to AN-994  

     for more details: 

http://www.irf.com/technical-info/appnotes/an-994.pdf

 

  

Calculated continuous current based on maximum allowable junction temperature.  

  Current is limited to 25A by source bonding technology. 

  Pulse drain current is limited to 100A by source bonding technology. 

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background image

 

IRFHM8235PbF 

HEXFET

® 

Power MOSFET 

Base part number  

Package Type  

Standard Pack 

Form 

Quantity 

IRFHM8235PbF 

PQFN 3.3 mm x 3.3 mm 

Tape and Reel 

4000 

IRFHM8235TRPbF 

Orderable Part Number   

V

DSS 

25 

R

DS(on) 

max 

(@ V

GS 

= 10V) 

7.7

(@ V

GS 

= 4.5V) 

13.4 

Qg

 (typical) 

7.7

nC 

I

D  

(@T

C (Bottom)

 = 25°C) 

25 A 

m



V

GS 

max

 

±20 

Features 

 

Benefits 

Low Thermal Resistance to PCB (<4.1°C/W) 

 

Enable better Thermal Dissipation 

Low Profile (<1.05mm)         

 

Increased Power Density 

Industry-Standard Pin out     

results in Multi-Vendor Compatibility 

Compatible with Existing Surface Mount Techniques                                              



Easier Manufacturing 

RoHS Compliant, Halogen-Free 

 

Environmentally Friendlier 

MSL1, Consumer Qualification 

 

Increased Reliability 

Notes  through  are on page 10 

Absolute Maximum Ratings 

 

 

 

  

Parameter Max. 

Units 

V

GS 

Gate-to-Source Voltage 

 ± 20 

I

D

 @ T

A

 = 25°C 

Continuous Drain Current, V

GS

 @ 10V 

16 

I

D

 @ T

C(Bottom)

 = 25°C 

Continuous Drain Current, V

GS

 @ 10V  

50 

I

D

 @ T

C(Bottom)

 = 100°C 

Continuous Drain Current, V

GS

 @ 10V  

32 

I

DM 

Pulsed Drain Current  240 

P

D

 @T

A

 = 25°C 

Power Dissipation  3.0 

P

D

 @T

C(Bottom)

 = 25°C 

Power Dissipation  30 

  

Linear Derating Factor  0.024 

W/°C 

T

J  

Operating Junction and 

-55  to + 150 

°C 

T

STG 

Storage Temperature Range 

  

I

D

 @ T

A

 = 70°C 

Continuous Drain Current, V

GS

 @ 10V 

13 

I

D

 @ T

C

 = 25°C 

Continuous Drain Current, V

GS

 @ 10V  

(Source Bonding Technology Limited) 

25 

Applications  


Control MOSFET for synchronous buck converter 

 

PQFN 3.3X3.3 mm 

 

 

2016-2-23 

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IRFHM8235PbF 

 

2016-2-23 

Thermal Resistance  

 

 

 

  

Parameter Typ. 

Max. 

Units 

R

JC

 (Bottom)  Junction-to-Case  ––– 

4.1 

R

JC

 (Top) 

Junction-to-Case  ––– 

42 

R

JA

  

Junction-to-Ambient  ––– 

42 

R

JA

 (<10s) 

Junction-to-Ambient  ––– 

28 

  °C/W     

Avalanche Characteristics 

 

 

 

 

 

 

 

  

Parameter  

 

Typ. 

Max. 

Units 

E

AS 

Single Pulse Avalanche Energy   

  ––– 

41 

mJ 

D

S

G

Static @ T

J

 = 25°C (unless otherwise specified) 

 

 

 

 

 

  

Parameter Min. 

Typ. 

Max. 

Units 

Conditions 

BV

DSS 

Drain-to-Source Breakdown Voltage 

25 

––– 

––– 

V

GS

 = 0V, I

D

 = 250µA 

BV

DSS

/

T

J  

Breakdown Voltage Temp. Coefficient 

––– 

19 

–––  mV/°C  Reference to 25°C, I

D

 = 1.0mA  

R

DS(on) 

Static Drain-to-Source On-Resistance 

––– 

6.2 

7.7 

m

 

V

GS

 = 10V, I

D

 = 20A  

  

  

––– 10.3 13.4 

V

GS

 = 4.5V, I

D

 = 16A  

V

GS(th) 

Gate Threshold Voltage 

1.35 

1.8 

2.35 

V

DS

 = V

GS

, I

D

 = 25µA   

V

GS(th) 

Gate Threshold Voltage Coefficient 

––– 

-5.9 

–––  mV/°C 

I

DSS 

Drain-to-Source Leakage Current 

––– 

––– 

1.0 

µA  

V

DS

 = 20V, V

GS

 = 0V 

 

 

––– ––– 150 

V

DS

 = 20V, V

GS

 = 0V, T

J

 = 125°C 

I

GSS 

Gate-to-Source Forward Leakage 

––– 

––– 

100 

nA 

V

GS

 = 20V 

  

Gate-to-Source Reverse Leakage 

––– 

––– 

-100 

V

GS

 = -20V 

gfs Forward 

Transconductance 

43 

––– 

––– 

V

DS

 = 10V, I

D

 = 20A 

Q

Total Gate Charge  

––– 

16 

––– 

nC  V

GS

 = 10V, V

DS

 = 13V, I

D

 = 20A  

Q

Total Gate Charge  

––– 

7.7 

12 

nC  

  

Q

gs1 

Pre-Vth Gate-to-Source Charge 

––– 

1.9 

––– 

V

DS

 = 13V 

Q

gs2 

Post-Vth Gate-to-Source Charge 

––– 

1.3 

––– 

V

GS

 = 4.5V  

Q

gd 

Gate-to-Drain Charge 

––– 

2.7 

––– 

I

D

 = 20A 

Q

godr 

Gate Charge Overdrive 

––– 

1.5 

––– 

  

Q

sw 

Switch Charge (Q

gs2

 + Q

gd

) ––– 

4.0 

––– 

  

Q

oss 

Output Charge 

––– 

6.4 

––– 

nC  V

DS

 = 16V, V

GS

 = 0V 

R

Gate Resistance 

––– 

1.6 

––– 

 

  

t

d(on) 

Turn-On Delay Time 

––– 

7.9 

––– 

ns  

V

DD

 = 13V, V

GS

 = 4.5V 

t

Rise Time 

––– 

16 

––– 

I

D

 = 20A 

t

d(off) 

Turn-Off Delay Time 

––– 

7.5 

––– 

R

G

=1.8

 

t

Fall Time 

––– 

5.2 

––– 

  

C

iss 

Input Capacitance 

––– 

1040 

––– 

V

GS

 = 0V 

C

oss 

Output Capacitance 

––– 

300 

––– 

V

DS

 = 10V 

C

rss 

Reverse Transfer Capacitance 

––– 

120 

––– 

ƒ = 1.0MHz 

pF  

Diode Characteristics 

 

 

 

 

 

 

 

  

        Parameter 

Min.  Typ.  Max.  Units 

Conditions 

I

Continuous Source Current  

––– ––– 25 

MOSFET symbol 

  

(Body Diode) 

showing  the 

I

SM 

Pulsed Source Current 

––– ––– 240 

integral reverse 

  

(Body Diode)  

p-n junction diode. 

V

SD 

Diode Forward Voltage 

–––  –––  1.0 

V  T

J

 = 25°C, I

S

 = 20A, V

GS

 = 0V  

t

rr 

Reverse Recovery Time 

––– 

10 

15 

ns  T

J

 = 25°C, I

F

 = 20A, V

DD

 = 13V 

Q

rr 

Reverse Recovery Charge 

–––  4.9 

7.4 

nC  di/dt = 300A/µs   

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IRFHM8235PbF 

 

2016-2-23 

Fig 1.  Typical Output Characteristics 

Fig 4.  Normalized On-Resistance vs. Temperature 

Fig 5.  Typical Capacitance vs. Drain-to-Source Voltage 

Fig 6.  Typical Gate Charge vs. Gate-to-Source Voltage 

Fig 3.  Typical Transfer Characteristics 

Fig 2.  Typical Output Characteristics 

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.01

0.1

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

VGS

TOP          

10V
7.0V
4.5V
4.0V
3.5V
3.0V
2.8V

BOTTOM

2.5V

60µs PULSE WIDTH

Tj = 25°C

2.5V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.1

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

C

u

rr

e

nt

 (

A

)

2.5V

60µs PULSE WIDTH

Tj = 150°C

VGS

TOP          

10V
7.0V
4.5V
4.0V
3.5V
3.0V
2.8V

BOTTOM

2.5V

1.0

2.5

4.0

5.5

7.0

8.5

10.0 11.5

VGS, Gate-to-Source Voltage (V)

0.1

1

10

100

1000

I D

, D

ra

in

-t

o-

S

ou

rc

e

 C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 150°C

VDS = 10V
60µs PULSE WIDTH

-60 -40 -20 0 20 40 60 80 100 120 140 160

TJ , Junction Temperature (°C)

0.6

0.8

1.0

1.2

1.4

1.6

R

D

S

(o

n)

 , 

D

ra

in

-t

o-

S

ou

rc

O

R

es

is

ta

nc

   

   

   

   

   

   

  

  (

N

or

m

al

iz

ed

)

ID = 20A
VGS = 10V

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

10

100

1000

10000

C

, C

ap

ac

ita

nc

(p

F

)

VGS   = 0V,       f = 1 MHZ

Ciss    = Cgs + Cgd,  Cds SHORTED
Crss   = Cgd 
Coss   = Cds + Cgd

Coss

Crss

Ciss

0

2

4

6

8

10 12 14 16 18 20

 QG,  Total Gate Charge (nC)

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

V

G

S

, G

a

te

-t

o-

S

ou

rc

V

ol

ta

ge

 (

V

)

VDS= 20V
VDS= 13V
VDS= 5.0V

ID= 20A

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background image

 

IRFHM8235PbF 

 

2016-2-23 

Fig 8.  Maximum Safe Operating Area  

Fig 11.  Maximum Effective Transient Thermal Impedance, Junction-to-Case  

Fig 7.  Typical Source-Drain Diode Forward Voltage 

Fig 9.  Maximum Drain Current vs. Case Temperature 

Fig 10.  

Threshold Voltage Vs. Temperature 

0.0

0.5

1.0

1.5

2.0

2.5

VSD, Source-to-Drain Voltage (V)

0.1

1

10

100

1000

I S

D

, R

ev

er

se

 D

ra

in

 C

ur

re

nt

 (

A

)

TJ = 25°C

TJ = 150°C

VGS = 0V

-75 -50 -25

0

25

50

75 100 125 150

TJ , Temperature ( °C )

0.8

1.2

1.6

2.0

2.4

2.8

V

G

S

(t

h)

,  

G

at

th

re

sh

ol

d

 V

ol

ta

ge

 (

V

)

ID = 25µA
ID = 250µA
ID = 1.0mA
ID = 1.0A

1E-006

1E-005

0.0001

0.001

0.01

0.1

1

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

1

10

T

he

rma

l R

es

p

on

se

 (

 Z  

th

JC

 ) 

°C

/W

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE
( THERMAL RESPONSE )

Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.01

0.1

1

10

100

1000

I D

,  

D

ra

in

-t

o-

S

ou

rc

C

ur

re

nt

 (

A

)

Tc = 25°C

Tj = 150°C

Single Pulse

10msec

1msec

OPERATION IN THIS AREA 
LIMITED BY RDS(on)

100µsec

DC

Limited by source 

bonding technology 

25

50

75

100

125

150

 TC , Case Temperature (°C)

0

11

22

33

44

55

I D

 ,

 D

ra

in

 C

ur

re

nt

 (

A

)

Limited by source 

bonding technology 

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IRFHM8235PbF 

 

2016-2-23 

Fig 12.  On-Resistance vs. Gate Voltage 

Fig 13.  Maximum Avalanche Energy vs. Drain Current 

Fig 14. Single avalanche event: pulse current vs. pulse width  

2

4

6

8

10

12

14

16

18

20

VGS, Gate -to -Source Voltage  (V)

0.0

4.0

8.0

12.0

16.0

20.0

24.0

R

D

S

(o

n

), 

 D

ra

in

-t

-S

ou

rc

O

R

e

si

st

an

ce

 (

m

)

ID = 20A

TJ = 25°C

TJ = 125°C

25

50

75

100

125

150

Starting TJ , Junction Temperature (°C)

0

20

40

60

80

100

120

140

160

180

E

A

S

 ,

 S

in

gl

e

 P

ul

se

 A

va

la

nc

he

 E

ne

rg

(m

J)

ID

TOP         4.0A

8.6A

BOTTOM 20A

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

0.1

1

10

100

A

va

la

nc

he

 C

ur

re

nt

 (

A

)

Allowed avalanche Current vs avalanche 
pulsewidth, tav, assuming 

 j = 25°C and 

Tstart = 125°C.

Allowed avalanche Current vs avalanche 
pulsewidth, tav, assuming 

Tj = 125°C and 

Tstart =25°C (Single Pulse)

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IRFHM8235PbF 

 

2016-2-23 

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET

® 

Power MOSFETs 

Fig 18a. Gate Charge Test Circuit 

Vds

Vgs

Id

Vgs(th)

Qgs1 Qgs2

Qgd

Qgodr

Fig 18b. Gate Charge Waveform 

Fig 16a.  Unclamped Inductive Test Circuit 

R G

I

AS

0.01

tp

D.U.T

L

VDS

+

- VDD

DRIVER

A

15V

20V

tp

V

(BR)DSS

I

AS

Fig 16b.  Unclamped Inductive Waveforms 

Fig 17a.  Switching Time Test Circuit 

Fig 17b.  Switching Time Waveforms 

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background image

 

IRFHM8235PbF 

 

2016-2-23 

The typical application topology for this product is the synchronous buck converter. These converters operate at high 
frequencies (typically around 400 kHz). During turn-on and turn-off switching cycles, the high di/dt currents circulating 
in the parasitic elements of the circuit induce high voltage ringing which may exceed the device rating and lead to un-
desirable effects. One of the major contributors to the increase in parasitics is the PCB power circuit inductance.  
 
This section introduces a simple guideline that mitigates the effect of these parasitics on the performance of the circuit 
and provides reliable operation of the devices. 
 
To reduce high frequency switching noise and the effects of Electromagnetic Interference (EMI) when the control 
MOSFET (Q1) is turned on, the layout shown in Figure 19 is recommended. The input bypass capacitors, control 
MOSFET and output capacitors are placed in a tight loop to minimize parasitic inductance which in turn lowers the am-
plitude of the switch node ringing, and minimizes exposure of the MOSFETs to repetitive avalanche conditions.  
 
When the synchronous MOSFET (Q2) is turned on, high average DC current flows through the path indicated in Figure 
19. Therefore, the Q2 turn-on path should be laid out with a tight loop and wide traces at both ends of the inductor to 
minimize loop resistance. 

Placement and Layout Guidelines 

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background image

 

IRFHM8235PbF 

 

2016-2-23 

For more information on board mounting, including footprint and stencil recommendation, please refer to application note 
AN-1136: 

http://www.irf.com/technical-info/appnotes/an-1136.pdf

 

For more information on package inspection techniques, please refer to application note AN-1154: 

http://www.irf.com/technical-info/appnotes/an-1154.pdf

 

PQFN 3.3 x 3.3 Outline “C” Package Details 

PQFN 3.3 x 3.3 Outline “G” Package Details 

5

8

7

6

#1

3

2

4

#1

2

3

4

8

7

6

5

5

8

7

6

1

3

2

4

1

2

3

4

8

7

6

5

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background image

 

IRFHM8235PbF 

 

2016-2-23 

PQFN 3.3mm x 3.3mm Outline Tape and Reel 

Note: For the most current drawing please refer to IR website at 

http://www.irf.com/package/

 

Bo

W

P1

Ao

Ko

CODE

TAPE DIMENSIONS

REEL DIMENSIONS

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE 

Dimension design to accommodate the component width
Dimension design to accommodate the component lenght
Dimension design to accommodate the component thickness

Pitch between successive cavity centers

Overall width of the carrier tape

Bo

W

P1

Ao

Ko

DIMENSION (MM)

CODE

MIN

MAX

DIMENSION (INCH)

MIN

MAX

3.50

3.70

.138

.146

1.10

1.30

7.90

8.10

.043

.051

11.80

12.20

.311

.319

12.30

12.50

.465

.480

.484

.492

3.50

3.70

.138

.146

DESCRIPTION

W1

Qty

4000

Reel Diameter

13   Inches

 

 

 

PQFN 3.3mm x 3.3mm Outline Part Marking 

 

Note: For the most current drawing please refer to IR website at 

http://www.irf.com/package/

 

XXXX

?YWW?

XXXXX

INTERNATIONAL

RECTIFIER LOGO

PART NUMBER

MARKING CODE

(Per Marking Spec)

ASSEMBLY
SITE CODE

(Per SCOP 200-002)

DATE CODE

LOT CODE

(Eng Mode - Min last 4 digits of EATI#)

(Prod Mode - 4 digits of SPN code)

PIN 1

IDENTIFIER

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background image

 

IRFHM8235PbF 

10 

 

2016-2-23 

Qualification Information

† 

 

Qualification Level 

Moisture Sensitivity Level  

PQFN 3.3mm x 3.3mm 

MSL1 

(per JEDEC J-STD-020D

†††

RoHS Compliant 

Yes 

Consumer

†† 

(per JEDEC JESD47F guidelines) 

† 

Qualification standards can be found at International Rectifier’s web site: 

http://www.irf.com/product-info/reliability/

 

††   Higher qualification ratings may be available should the user have such requirements.  Please contact your 
 

International Rectifier sales representative for further information: 

http://www.irf.com/whoto-call/salesrep/

 

†††  Applicable version of JEDEC standard at the time of product release.

 

Notes:

  

Repetitive rating;  pulse width limited by max. junction temperature. 

   

Starting T

J

 = 25°C, L = 0.21mH, R

G

 = 50

, I

AS

 = 20A.  

 

Pulse width 

 400µs; duty cycle  2%. 

   R

 is measured at T

J

 of approximately 90°C. 

  

When mounted on 1 inch square  2 oz copper pad on 1.5x1.5 in. board of FR-4 material. Please refer to AN-994  

     for more details: 

http://www.irf.com/technical-info/appnotes/an-994.pdf

 

  

Calculated continuous current based on maximum allowable junction temperature.  

  Current is limited to 25A by source bonding technology. 

  Pulse drain current is limited to 100A by source bonding technology. 

Maker
Infineon Technologies