© 2000 Fairchild Semiconductor Corporation
DS006404
www.fairchildsemi.com
August 1992
Revised April 2000
DM74LS174
•
D
M
74LS17
5 Hex/
Quad D-
T
ype Fl
ip
-Fl
ops
w
ith
Clea
r
DM74LS174 • DM74LS175
Hex/Quad D-Type Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (175) versions feature complementary
outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
Features
■
DM74LS174 contains six flip-flops with single-rail
outputs
■
DM74LS175 contains four flip-flops with double-rail
outputs
■
Buffered clock and direct clear inputs
■
Individual data input to each flip-flop
■
Applications include:
Buffer/storage registers
Shift registers
Pattern generators
■
Typical clock frequency 40 MHz
■
Typical power dissipation per flip-flop 14 mW
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
DM74LS174
DM74LS175
Order Number
Package Number
Package Description
DM74LS174M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS174SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS174N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74LS175M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS175SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS175N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
DM74LS174
• DM74LS175
Function Table
(Each Flip-Flop)
H
=
HIGH Level (steady state)
L
=
LOW Level (steady state)
X
=
Don’t Care
↑
=
Transition from LOW-to-HIGH level
Q
0
=
The level of Q before the indicated steady-state input conditions were established.
†
=
DM74LS175 only
Logic Diagrams
DM74LS174
DM74LS175
Inputs
Outputs
Clear
Clock
D
Q
Q †
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q
0
Q
0
3
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DM74LS174
• D
M
74LS17
5
Absolute Maximum Ratings
(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
DM74LS174 Recommended Operating Conditions
Note 2: C
L
=
15 pF, R
L
=
2 k
Ω
, T
A
=
25
°
C and V
CC
=
5V.
Note 3: C
L
=
50 pF, R
L
=
2 k
Ω
, T
A
=
25
°
C and V
CC
=
5V.
Note 4: T
A
=
25
°
C and V
CC
=
5V.
DM74LS174 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 5: All typicals are at V
CC
=
5V, T
A
=
25
°
C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 7: With all outputs OPEN and 4.5V applied to all data and clear inputs, I
CC
is measured after a momentary ground, then 4.5V applied to the clock.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0
°
C to
+
70
°
C
Storage Temperature Range
−
65
°
C to
+
150
°
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
−
0.4
mA
I
OL
LOW Level Output Current
8
mA
f
CLK
Clock Frequency (Note 2)
0
30
MHz
f
CLK
Clock Frequency (Note 3)
0
25
MHz
t
W
Pulse Width
Clock
20
ns
(Note 4)
Clear
20
t
SU
Data Setup Time (Note 4)
20
ns
t
H
Data Hold Time (Note 4)
0
ns
t
REL
Clear Release Time (Note 4)
25
ns
T
A
Free Air Operating Temperature
0
70
°
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 5)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
−
18 mA
−
1.5
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max
2.7
3.4
V
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
OL
LOW
Level V
CC
=
Min, I
OL
=
Max
0.35
0.5
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
I
OL
=
4 mA, V
CC
=
Min
0.25
0.4
I
I
Input Current @ Max Input Voltage V
CC
=
Max, V
I
=
7V
0.1
mA
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V
20
µ
A
I
IL
LOW
Level V
CC
=
Max
Clock
−
0.4
Input Current
V
I
=
0.4V
Clear
−
0.4
mA
Data
−
0.36
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 6)
−
20
−
100
mA
I
CC
Supply Current
V
CC
=
Max (Note 7)
16
26
mA
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4
DM74LS174
• DM74LS175
DM74LS174 Switching Characteristics
at V
CC
=
5V and T
A
=
25
°
C
From (Input)
R
L
=
2 k
Ω
Symbol
Parameter
To (Output)
C
L
=
15 pF
C
L
=
50 pF
Units
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
30
25
MHz
t
PLH
Propagation Delay Time
Clock to Output
30
32
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clock to Output
30
36
ns
HIGH-to-LOW Level Output
t
PHL
Propagation Delay Time
Clear to Output
35
42
ns
HIGH-to-LOW Level Output
5
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DM74LS174
• D
M
74LS17
5
DM74LS175 Recommended Operating Conditions
Note 8: C
L
=
15 pF, R
L
=
2 k
Ω
, T
A
=
25
°
C and V
CC
=
5V.
Note 9: C
L
=
50 pF, R
L
=
2 k
Ω
, T
A
=
25
°
C and V
CC
=
5V.
Note 10: T
A
=
25
°
C and V
CC
=
5V.
DM74LS175 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 11: All typicals are at V
CC
=
5V, T
A
=
25
°
C.
Note 12: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 13: With all outputs OPEN and 4.5V applied to all data and clear inputs, I
CC
is measured after a momentary ground, then 4.5V applied to the clock
input.
DM74LS175 Switching Characteristics
at V
CC
=
5V and T
A
=
25
°
C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
−
0.4
mA
I
OL
LOW Level Output Current
8
mA
f
CLK
Clock Frequency (Note 8)
0
30
MHz
f
CLK
Clock Frequency (Note 9)
0
25
MHz
t
W
Pulse Width
Clock
20
ns
(Note 10)
Clear
20
t
SU
Data Setup Time (Note 10)
20
ns
t
H
Data Hold Time (Note 10)
0
ns
t
REL
Clear Release Time (Note 10)
25
ns
T
A
Free Air Operating Temperature
0
70
°
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 11)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
−
18 mA
−
1.5
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max
2.7
3.4
V
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
OL
LOW
Level V
CC
=
Min, I
OL
=
Max
0.35
0.5
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
I
OL
=
4 mA, V
CC
=
Min
0.25
0.4
I
I
Input Current @ Max Input Voltage V
CC
=
Max, V
I
=
7V
0.1
mA
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V
20
µ
A
I
IL
LOW
Level V
CC
=
Max
Clock
−
0.4
Input Current
V
I
=
0.4V
Clear
−
0.4
mA
Data
−
0.36
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 12)
−
20
−
100
mA
I
CC
Supply Current
V
CC
=
Max (Note 13)
11
18
mA
From (Input)
R
L
=
2 k
Ω
Symbol
Parameter
To (Output)
C
L
=
15 pF
C
L
=
50 pF
Units
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
30
25
MHz
t
PLH
Propagation Delay Time
Clock to Q or Q
30
32
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clock to Q or Q
30
36
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Clear to Q
25
29
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clear to Q
35
42
ns
HIGH-to-LOW Level Output
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6
DM74LS174
• DM74LS175
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
7
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DM74LS174
•
D
M
74LS17
5 Hex/
Quad D-
T
ype Fl
ip
-Fl
ops
w
ith
Clea
r
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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